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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id id15-20020a05600ca18f00b003a31f1edfa7sm1805798wmb.41.2022.07.18.06.59.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jul 2022 06:59:23 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 00/15] target-arm queue Date: Mon, 18 Jul 2022 14:59:05 +0100 Message-Id: <20220718135920.13667-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Some arm patches before softfreeze. These are all bug fixes. -- PMM The following changes since commit 0ebf76aae58324b8f7bf6af798696687f5f4c2a9: Merge tag 'nvme-next-pull-request' of git://git.infradead.org/qemu-nvme into staging (2022-07-15 15:38:13 +0100) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220718 for you to fetch changes up to 004c8a8bc569c8b18fca6fc90ffe3223daaf17b7: Align Raspberry Pi DMA interrupts with Linux DTS (2022-07-18 13:25:13 +0100) ---------------------------------------------------------------- target-arm queue: * hw/intc/armv7m_nvic: ICPRn must not unpend an IRQ that is being held high * target/arm: Fill in VL for tbflags when SME enabled and SVE disabled * target/arm: Fix aarch64_sve_change_el for SME * linux-user/aarch64: Do not clear PROT_MTE on mprotect * target/arm: Honour VTCR_EL2 bits in Secure EL2 * hw/adc: Fix CONV bit in NPCM7XX ADC CON register * hw/adc: Make adci[*] R/W in NPCM7XX ADC * target/arm: Don't set syndrome ISS for loads and stores with writeback * Align Raspberry Pi DMA interrupts with Linux DTS ---------------------------------------------------------------- Andrey Makarov (1): Align Raspberry Pi DMA interrupts with Linux DTS Hao Wu (2): hw/adc: Fix CONV bit in NPCM7XX ADC CON register hw/adc: Make adci[*] R/W in NPCM7XX ADC Peter Maydell (9): hw/intc/armv7m_nvic: ICPRn must not unpend an IRQ that is being held high target/arm: Define and use new regime_tcr_value() function target/arm: Calculate mask/base_mask in get_level1_table_address() target/arm: Fold regime_tcr() and regime_tcr_value() together target/arm: Fix big-endian host handling of VTCR target/arm: Store VTCR_EL2, VSTCR_EL2 registers as uint64_t target/arm: Store TCR_EL* registers as uint64_t target/arm: Honour VTCR_EL2 bits in Secure EL2 target/arm: Don't set syndrome ISS for loads and stores with writeback Richard Henderson (3): target/arm: Fill in VL for tbflags when SME enabled and SVE disabled target/arm: Fix aarch64_sve_change_el for SME linux-user/aarch64: Do not clear PROT_MTE on mprotect include/hw/arm/bcm2835_peripherals.h | 2 + target/arm/cpu.h | 38 ++++++++--- target/arm/internals.h | 34 +++++++--- accel/tcg/translate-all.c | 13 +++- hw/adc/npcm7xx_adc.c | 4 +- hw/arm/bcm2835_peripherals.c | 26 ++++++- hw/intc/armv7m_nvic.c | 9 ++- target/arm/cpu.c | 2 +- target/arm/debug_helper.c | 2 +- target/arm/helper.c | 128 ++++++++++++++++------------------- target/arm/ptw.c | 38 ++++++----- target/arm/tlb_helper.c | 2 +- target/arm/translate-a64.c | 4 +- tests/qtest/bcm2835-dma-test.c | 118 ++++++++++++++++++++++++++++++++ tests/qtest/npcm7xx_adc-test.c | 2 +- tests/qtest/meson.build | 3 +- 16 files changed, 306 insertions(+), 119 deletions(-) create mode 100644 tests/qtest/bcm2835-dma-test.c