From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D26CC43334 for ; Mon, 25 Jul 2022 02:08:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233075AbiGYCIW (ORCPT ); Sun, 24 Jul 2022 22:08:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34776 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231421AbiGYCIQ (ORCPT ); Sun, 24 Jul 2022 22:08:16 -0400 Received: from mail-pj1-x102d.google.com (mail-pj1-x102d.google.com [IPv6:2607:f8b0:4864:20::102d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4A48FEE3C for ; Sun, 24 Jul 2022 19:08:14 -0700 (PDT) Received: by mail-pj1-x102d.google.com with SMTP id bk6-20020a17090b080600b001f2138a2a7bso10240352pjb.1 for ; Sun, 24 Jul 2022 19:08:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2bb8XU1Bnk4jusD63lmk3Ol2o00AOfRxKRkmAkiDP4o=; b=fZIYHmc8N+T0x4kQRJbfoR40FVeWXHFoj1Ez9pMFcXxzgRhu2PqfTJX13WZ/W+RErc OPcB5PlL1q7UBLiBsWYp3lmlcvt9LTpbaSGcKj1OlF3D9EJ2VUaL0wG5GK4fm3QG6s3F CqsJ4rBlixoSyIwWe1Al7OeyD+ZwvQEXYZw1+eILqV8AEuRLuJ+TYwAvQon6qTm4+0Wu gWL3JwtDy4xRDqckeXp1Os7f93urL1kvSDpHRRwv7nzF1i1sITAxOcmqV6odWEh4z8OZ XhuLNTpmXovVM+mTrmFrG3WgCoM+U4Llhuo/N2j7RE1xvfb7kkfWmTc0wYInGzP5GKZs AqBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2bb8XU1Bnk4jusD63lmk3Ol2o00AOfRxKRkmAkiDP4o=; b=WGg6rllkwofRNuBo6jMTfzkOT2TCZNFtOlxUd4pJ5n+NgxL1osopHIOxHDJAW3mnkX CZr/RtFegGtXkZKXE/F9r7Cfb2cqK11wNqkaNT00kyeogoeFPvXuOClKOBeAjs5azBxL qxpJxJBkii0mqI6blvp3rFDdaBfqe0fWIW0j68a50EbGIC6ja3LYQ+IiiKtbYGsVQppb 8jniYdpyYut34gNWW24oshoTOluT/1UGSUimcZNXsn6G5rNh134PsO7Bi5D37ibmwjPo di8izbCU6rfcuEtLhV3Ew8F/kIncrLo+1fSDHPrPf+5N15Io/g6inG0wy4aqeA72ep6Z yMbg== X-Gm-Message-State: AJIora9pGWo2mD5FQzWmpmVbBwjEqdxfF7zeJmq7+VgQLGIZqYFdN5fa SXabK6CpV3798p+i3YeWHFRkmq4xvZk0jQ== X-Google-Smtp-Source: AGRyM1vZnZRBfbk7P18DqP3O8ruzD393p79BGSWNpGSjB7sr0RoO7KDfhkFVa9m61iUpftGqgqdWYg== X-Received: by 2002:a17:902:8a86:b0:16c:4292:9f56 with SMTP id p6-20020a1709028a8600b0016c42929f56mr10268982plo.36.1658714893200; Sun, 24 Jul 2022 19:08:13 -0700 (PDT) Received: from localhost ([2409:10:24a0:4700:e8ad:216a:2a9d:6d0c]) by smtp.gmail.com with ESMTPSA id b17-20020a170902d51100b0016c50179b1esm1691376plg.152.2022.07.24.19.08.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Jul 2022 19:08:12 -0700 (PDT) From: Stafford Horne To: LKML Cc: Bjorn Helgaas , Arnd Bergmann , Stafford Horne , Jonas Bonn , Stefan Kristiansson , Palmer Dabbelt , Peter Zijlstra , openrisc@lists.librecores.org Subject: [PATCH v3 2/3] openrisc: Add pci bus support Date: Mon, 25 Jul 2022 11:07:36 +0900 Message-Id: <20220725020737.1221739-3-shorne@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220725020737.1221739-1-shorne@gmail.com> References: <20220725020737.1221739-1-shorne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds required definitions to allow for PCI buses on OpenRISC. This is being tested on the OpenRISC QEMU virt platform which is in development. OpenRISC does not have IO ports so we keep the definition of IO_SPACE_LIMIT and PIO_RESERVED to be 0. Note, since commit 66bcd06099bb ("parport_pc: Also enable driver for PCI systems") all platforms that support PCI also need to support parallel port. We add a generic header to support compiling parallel port drivers, though they generally will not work as they require IO ports. Signed-off-by: Stafford Horne --- arch/openrisc/Kconfig | 5 ++++- arch/openrisc/include/asm/Kbuild | 1 + arch/openrisc/include/asm/io.h | 2 +- 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig index e814df4c483c..c7f282f60f64 100644 --- a/arch/openrisc/Kconfig +++ b/arch/openrisc/Kconfig @@ -20,8 +20,9 @@ config OPENRISC select GENERIC_IRQ_CHIP select GENERIC_IRQ_PROBE select GENERIC_IRQ_SHOW - select GENERIC_IOMAP + select GENERIC_PCI_IOMAP select GENERIC_CPU_DEVICES + select HAVE_PCI select HAVE_UID16 select GENERIC_ATOMIC64 select GENERIC_CLOCKEVENTS_BROADCAST @@ -32,6 +33,8 @@ config OPENRISC select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1 select ARCH_USE_QUEUED_RWLOCKS select OMPIC if SMP + select PCI_DOMAINS_GENERIC if PCI + select PCI_MSI if PCI select ARCH_WANT_FRAME_POINTERS select GENERIC_IRQ_MULTI_HANDLER select MMU_GATHER_NO_RANGE if MMU diff --git a/arch/openrisc/include/asm/Kbuild b/arch/openrisc/include/asm/Kbuild index 3386b9c1c073..c8c99b554ca4 100644 --- a/arch/openrisc/include/asm/Kbuild +++ b/arch/openrisc/include/asm/Kbuild @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 generic-y += extable.h generic-y += kvm_para.h +generic-y += parport.h generic-y += spinlock_types.h generic-y += spinlock.h generic-y += qrwlock_types.h diff --git a/arch/openrisc/include/asm/io.h b/arch/openrisc/include/asm/io.h index c298061c70a7..625ac6ad1205 100644 --- a/arch/openrisc/include/asm/io.h +++ b/arch/openrisc/include/asm/io.h @@ -17,7 +17,7 @@ #include /* - * PCI: can we really do 0 here if we have no port IO? + * PCI: We do not use IO ports in OpenRISC */ #define IO_SPACE_LIMIT 0 -- 2.36.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.librecores.org (lists.librecores.org [88.198.125.70]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6FD9C433EF for ; Mon, 25 Jul 2022 02:08:17 +0000 (UTC) Received: from [172.31.1.100] (localhost.localdomain [127.0.0.1]) by mail.librecores.org (Postfix) with ESMTP id 73E4320C6A; Mon, 25 Jul 2022 04:08:16 +0200 (CEST) Received: from mail-pl1-f169.google.com (mail-pl1-f169.google.com [209.85.214.169]) by mail.librecores.org (Postfix) with ESMTPS id E005520E49 for ; Mon, 25 Jul 2022 04:08:14 +0200 (CEST) Received: by mail-pl1-f169.google.com with SMTP id d7so9117537plr.9 for ; Sun, 24 Jul 2022 19:08:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2bb8XU1Bnk4jusD63lmk3Ol2o00AOfRxKRkmAkiDP4o=; b=fZIYHmc8N+T0x4kQRJbfoR40FVeWXHFoj1Ez9pMFcXxzgRhu2PqfTJX13WZ/W+RErc OPcB5PlL1q7UBLiBsWYp3lmlcvt9LTpbaSGcKj1OlF3D9EJ2VUaL0wG5GK4fm3QG6s3F CqsJ4rBlixoSyIwWe1Al7OeyD+ZwvQEXYZw1+eILqV8AEuRLuJ+TYwAvQon6qTm4+0Wu gWL3JwtDy4xRDqckeXp1Os7f93urL1kvSDpHRRwv7nzF1i1sITAxOcmqV6odWEh4z8OZ XhuLNTpmXovVM+mTrmFrG3WgCoM+U4Llhuo/N2j7RE1xvfb7kkfWmTc0wYInGzP5GKZs AqBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2bb8XU1Bnk4jusD63lmk3Ol2o00AOfRxKRkmAkiDP4o=; b=dX1pgFBZeonmdFS+p7j2pOwagKHCQ9LAOTFizFTd2hgj4Hr1qdVFpWhwXBJaesIvqn 2kG5e109xcCddf0F1/snxy4Jnvk69Z/39yZz83xnyWYPTFUtxpkdahZKp1iatXFJP+U5 ZRWLXrulc0tH5vGJo7BsdDgM7v9sTikIL/8kUjCMMaljhIqrZA4XaFSna8q+w71PCXhB TWCJsxKEt+ZWqkwjP+gKExEnH6dLzp0Y1FCbUa5/COM54SChyxLeyT9+81mpaNdt/+AG YxaKZ0LWey/oH09OugppasDYydg3lTLTwFkt71q7s2eoMm4shMG0dLUf7nmIEiC0gs3r HNLg== X-Gm-Message-State: AJIora8dBGJDBuWKYD+BbLZhX95pe8TJwqWCiDpfKyzxQ5dBMY421ZzP fEOOdGdrlHTNgXSbGzR0CyQ= X-Google-Smtp-Source: AGRyM1vZnZRBfbk7P18DqP3O8ruzD393p79BGSWNpGSjB7sr0RoO7KDfhkFVa9m61iUpftGqgqdWYg== X-Received: by 2002:a17:902:8a86:b0:16c:4292:9f56 with SMTP id p6-20020a1709028a8600b0016c42929f56mr10268982plo.36.1658714893200; Sun, 24 Jul 2022 19:08:13 -0700 (PDT) Received: from localhost ([2409:10:24a0:4700:e8ad:216a:2a9d:6d0c]) by smtp.gmail.com with ESMTPSA id b17-20020a170902d51100b0016c50179b1esm1691376plg.152.2022.07.24.19.08.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Jul 2022 19:08:12 -0700 (PDT) From: Stafford Horne To: LKML Subject: [PATCH v3 2/3] openrisc: Add pci bus support Date: Mon, 25 Jul 2022 11:07:36 +0900 Message-Id: <20220725020737.1221739-3-shorne@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220725020737.1221739-1-shorne@gmail.com> References: <20220725020737.1221739-1-shorne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: openrisc@lists.librecores.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: Discussion around the OpenRISC processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jonas Bonn , Arnd Bergmann , Peter Zijlstra , Palmer Dabbelt , openrisc@lists.librecores.org, Bjorn Helgaas Errors-To: openrisc-bounces@lists.librecores.org Sender: "OpenRISC" This patch adds required definitions to allow for PCI buses on OpenRISC. This is being tested on the OpenRISC QEMU virt platform which is in development. OpenRISC does not have IO ports so we keep the definition of IO_SPACE_LIMIT and PIO_RESERVED to be 0. Note, since commit 66bcd06099bb ("parport_pc: Also enable driver for PCI systems") all platforms that support PCI also need to support parallel port. We add a generic header to support compiling parallel port drivers, though they generally will not work as they require IO ports. Signed-off-by: Stafford Horne --- arch/openrisc/Kconfig | 5 ++++- arch/openrisc/include/asm/Kbuild | 1 + arch/openrisc/include/asm/io.h | 2 +- 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig index e814df4c483c..c7f282f60f64 100644 --- a/arch/openrisc/Kconfig +++ b/arch/openrisc/Kconfig @@ -20,8 +20,9 @@ config OPENRISC select GENERIC_IRQ_CHIP select GENERIC_IRQ_PROBE select GENERIC_IRQ_SHOW - select GENERIC_IOMAP + select GENERIC_PCI_IOMAP select GENERIC_CPU_DEVICES + select HAVE_PCI select HAVE_UID16 select GENERIC_ATOMIC64 select GENERIC_CLOCKEVENTS_BROADCAST @@ -32,6 +33,8 @@ config OPENRISC select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1 select ARCH_USE_QUEUED_RWLOCKS select OMPIC if SMP + select PCI_DOMAINS_GENERIC if PCI + select PCI_MSI if PCI select ARCH_WANT_FRAME_POINTERS select GENERIC_IRQ_MULTI_HANDLER select MMU_GATHER_NO_RANGE if MMU diff --git a/arch/openrisc/include/asm/Kbuild b/arch/openrisc/include/asm/Kbuild index 3386b9c1c073..c8c99b554ca4 100644 --- a/arch/openrisc/include/asm/Kbuild +++ b/arch/openrisc/include/asm/Kbuild @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 generic-y += extable.h generic-y += kvm_para.h +generic-y += parport.h generic-y += spinlock_types.h generic-y += spinlock.h generic-y += qrwlock_types.h diff --git a/arch/openrisc/include/asm/io.h b/arch/openrisc/include/asm/io.h index c298061c70a7..625ac6ad1205 100644 --- a/arch/openrisc/include/asm/io.h +++ b/arch/openrisc/include/asm/io.h @@ -17,7 +17,7 @@ #include /* - * PCI: can we really do 0 here if we have no port IO? + * PCI: We do not use IO ports in OpenRISC */ #define IO_SPACE_LIMIT 0 -- 2.36.1