All of lore.kernel.org
 help / color / mirror / Atom feed
From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 07/23] drm/i915/mtl: Add gmbus and gpio support
Date: Wed, 27 Jul 2022 18:34:04 -0700	[thread overview]
Message-ID: <20220728013420.3750388-8-radhakrishna.sripada@intel.com> (raw)
In-Reply-To: <20220728013420.3750388-1-radhakrishna.sripada@intel.com>

Add tables to map the GMBUS pin pairs to GPIO registers and port to DDC.
From spec we have registers GPIO_CTL[1-5] mapped to combo phys and
GPIO_CTL[9-14] are mapped to TC ports.

BSpec: 49306

Original Author: Brian J Lovin
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
 drivers/gpu/drm/i915/display/intel_gmbus.c | 17 +++++++++++++++++
 drivers/gpu/drm/i915/display/intel_gmbus.h |  1 +
 2 files changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
index a6ba7fb72339..542b8b2654be 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -116,6 +116,20 @@ static const struct gmbus_pin gmbus_pins_dg2[] = {
 	[GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
 };
 
+static const struct gmbus_pin gmbus_pins_mtp[] = {
+	[GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
+	[GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
+	[GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
+	[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
+	[GMBUS_PIN_5_MTP] = { "dpe", GPIOF },
+	[GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
+	[GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
+	[GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
+	[GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
+	[GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION },
+	[GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO },
+};
+
 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915,
 					     unsigned int pin)
 {
@@ -128,6 +142,9 @@ static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915,
 	} else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) {
 		pins = gmbus_pins_dg1;
 		size = ARRAY_SIZE(gmbus_pins_dg1);
+	} else if (INTEL_PCH_TYPE(i915) >= PCH_MTP) {
+		pins = gmbus_pins_mtp;
+		size = ARRAY_SIZE(gmbus_pins_mtp);
 	} else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) {
 		pins = gmbus_pins_icp;
 		size = ARRAY_SIZE(gmbus_pins_icp);
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.h b/drivers/gpu/drm/i915/display/intel_gmbus.h
index 8edc2e99cf53..20f704bd4e70 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.h
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.h
@@ -24,6 +24,7 @@ struct i2c_adapter;
 #define GMBUS_PIN_2_BXT		2
 #define GMBUS_PIN_3_BXT		3
 #define GMBUS_PIN_4_CNP		4
+#define GMBUS_PIN_5_MTP		5
 #define GMBUS_PIN_9_TC1_ICP	9
 #define GMBUS_PIN_10_TC2_ICP	10
 #define GMBUS_PIN_11_TC3_ICP	11
-- 
2.25.1


  parent reply	other threads:[~2022-07-28  1:38 UTC|newest]

Thread overview: 57+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-28  1:33 [Intel-gfx] [PATCH 00/23] Initial Meteorlake Support Radhakrishna Sripada
2022-07-28  1:33 ` [Intel-gfx] [PATCH 01/23] drm/i915: Read graphics/media/display arch version from hw Radhakrishna Sripada
2022-07-28  3:46   ` [Intel-gfx] [v1.1 " Radhakrishna Sripada
2022-08-10 11:02     ` Jani Nikula
2022-08-10 13:23       ` Jani Nikula
2022-08-18 14:58     ` Balasubramani Vivekanandan
2022-07-28 17:06   ` [Intel-gfx] [PATCH " kernel test robot
2022-07-28  1:33 ` [Intel-gfx] [PATCH 02/23] drm/i915: Parse and set stepping for platforms with GMD Radhakrishna Sripada
2022-07-28  1:34 ` [Intel-gfx] [PATCH 03/23] drm/i915/mtl: MMIO range is now 4MB Radhakrishna Sripada
2022-07-28  1:34 ` [Intel-gfx] [PATCH 04/23] drm/i915/mtl: Don't mask off CCS according to DSS fusing Radhakrishna Sripada
2022-07-28  1:34 ` [Intel-gfx] [PATCH 05/23] drm/i915/mtl: Define engine context layouts Radhakrishna Sripada
2022-07-28  1:34 ` [Intel-gfx] [PATCH 06/23] drm/i915/mtl: Add PCH support Radhakrishna Sripada
2022-07-28 21:28   ` Srivatsa, Anusha
2022-07-28  1:34 ` Radhakrishna Sripada [this message]
2022-08-01 21:33   ` [Intel-gfx] [PATCH 07/23] drm/i915/mtl: Add gmbus and gpio support Matt Roper
2022-07-28  1:34 ` [Intel-gfx] [PATCH 08/23] drm/i915/mtl: Add VBT port and AUX_CH mapping Radhakrishna Sripada
2022-08-01 21:45   ` Matt Roper
2022-07-28  1:34 ` [Intel-gfx] [PATCH 09/23] drm/i915/mtl: Add support for MTL in Display Init sequences Radhakrishna Sripada
2022-08-01 21:49   ` Matt Roper
2022-07-28  1:34 ` [Intel-gfx] [PATCH 10/23] drm/i915/mtl: Add display power wells Radhakrishna Sripada
2022-08-02  1:23   ` Matt Roper
2022-08-02 15:40     ` Matt Roper
2022-07-28  1:34 ` [Intel-gfx] [PATCH 11/23] drm/i915/mtl: Add DP AUX support on TypeC ports Radhakrishna Sripada
2022-08-02 15:41   ` Matt Roper
2022-07-28  1:34 ` [Intel-gfx] [PATCH 12/23] drm/i915/mtl: Fix rawclk for Meteorlake PCH Radhakrishna Sripada
2022-08-02  3:28   ` Matt Roper
2022-08-02  3:36     ` Caz Yokoyama
2022-07-28  1:34 ` [Intel-gfx] [PATCH 13/23] drm/i915/mtl: memory latency data from LATENCY_LPX_LPY for WM Radhakrishna Sripada
2022-08-02 16:12   ` Matt Roper
2022-08-10 11:09     ` Jani Nikula
2022-08-10 11:10       ` Jani Nikula
2022-07-28  1:34 ` [Intel-gfx] [PATCH 14/23] drm/i915/mtl: Add CDCLK Support Radhakrishna Sripada
2022-07-28  1:34 ` [Intel-gfx] [PATCH 15/23] drm/i915/mtl: Obtain SAGV values from MMIO instead of GT pcode mailbox Radhakrishna Sripada
2022-08-02 16:43   ` Matt Roper
2022-08-02 16:53   ` Caz Yokoyama
2022-08-10 11:14   ` Jani Nikula
2022-07-28  1:34 ` [Intel-gfx] [PATCH 16/23] drm/i915/mtl: Update memory bandwidth parameters Radhakrishna Sripada
2022-08-02 16:52   ` Matt Roper
2022-07-28  1:34 ` [Intel-gfx] [PATCH 17/23] drm/i915/mtl: Update MBUS_DBOX credits Radhakrishna Sripada
2022-08-02 17:14   ` Matt Roper
2022-08-03 13:55   ` Balasubramani Vivekanandan
2022-07-28  1:34 ` [Intel-gfx] [PATCH 18/23] drm/i915/mtl: DBUF handling is same as adlp Radhakrishna Sripada
2022-08-02 17:35   ` Matt Roper
2022-07-28  1:34 ` [Intel-gfx] [PATCH 19/23] drm/i915/display/mtl: Extend MBUS programming Radhakrishna Sripada
2022-08-02 17:39   ` Matt Roper
2022-07-28  1:34 ` [Intel-gfx] [PATCH 20/23] drm/i915/dmc: Load DMC on MTL Radhakrishna Sripada
2022-08-02 18:00   ` Matt Roper
2022-07-28  1:34 ` [Intel-gfx] [PATCH 21/23] drm/i915/dmc: MTL DMC debugfs entries Radhakrishna Sripada
2022-08-02 18:22   ` Matt Roper
2022-08-09 18:06     ` Srivatsa, Anusha
2022-07-28  1:34 ` [Intel-gfx] [PATCH 22/23] drm/i915/mtl: Update CHICKEN_TRANS* register addresses Radhakrishna Sripada
2022-08-10 11:21   ` Jani Nikula
2022-07-28  1:34 ` [Intel-gfx] [PATCH 23/23] drm/i915/mtl: Do not update GV point, mask value Radhakrishna Sripada
2022-07-28  1:54 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Initial Meteorlake Support Patchwork
2022-08-02  3:26 ` [Intel-gfx] [PATCH 00/23] " Matt Roper
2022-08-04  9:08 ` Jani Nikula
2022-08-04 13:10   ` Jani Nikula

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20220728013420.3750388-8-radhakrishna.sripada@intel.com \
    --to=radhakrishna.sripada@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.