From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B32BEC00144 for ; Mon, 1 Aug 2022 15:49:30 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id D1F93844E2; Mon, 1 Aug 2022 17:49:28 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="FOBvs/mI"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id A0241844BC; Mon, 1 Aug 2022 17:49:26 +0200 (CEST) Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 185AB844B6 for ; Mon, 1 Aug 2022 17:49:24 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=kabel@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 0EA7A60BFF; Mon, 1 Aug 2022 15:49:23 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id A8D90C433C1; Mon, 1 Aug 2022 15:49:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1659368962; bh=OddF8cf7gbMj0HW81evHBl1sIgZjMCbdnGa3NOy20uo=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=FOBvs/mIh9ExAuNk4JVgalU3BNQLP2qo55FISvi+E6rQSIzqKy5H5oRe7olePfC5B uUjpRQgo+FXd63LRqeKJduCDf8oQxhwQPH2xxOqNfClNhPBJXE1qXC4NyIZieMFATN DU1SqTAOfN00+Pxao55F+/99Gb2wdo7gJSgjtBG3EnjRn60NkTePbwq77N1o9bW8qE kN5PPoLJ0bpfHCYO8G+CKuX/npAvyI/+RHQNqU2xrIfoQa/NRtiaAznYJw1io39eJQ QN3TTO8wN0ua9/zpNT86obNlMAOZbUe0wzRB4TKoQeJ6UQtpQmK/P6PG63r9PefZBD 7xWHWhuDKaqgg== Date: Mon, 1 Aug 2022 17:49:19 +0200 From: Marek =?UTF-8?B?QmVow7pu?= To: Pali =?UTF-8?B?Um9ow6Fy?= Cc: Stefan Roese , u-boot@lists.denx.de Subject: Re: [PATCH 2/2] arm: mvebu: turris_omnia: Add support for design with SW reset signals Message-ID: <20220801174919.6982e055@dellmb> In-Reply-To: <20220729112907.8207-2-pali@kernel.org> References: <20220729112907.8207-1-pali@kernel.org> <20220729112907.8207-2-pali@kernel.org> X-Mailer: Claws Mail 3.19.0 (GTK+ 2.24.33; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean On Fri, 29 Jul 2022 13:29:07 +0200 Pali Roh=C3=A1r wrote: > New Turris Omnia HW board revision requires that software controls > peripheral reset signals, namely PERST# signals on mPCIe slots, ethernet > phy reset and lan switch reset. Those pins are connected to MCU controlled > by MCU i2c API as GPIOs. On new HW board revision those pins stay in reset > after board reset and software has to release these peripherals from reset > manually. MCU announce this requirement by FEAT_PERIPH_MCU bit in > CMD_GET_FEATURES command. >=20 > On older HW board revisions when FEAT_PERIPH_MCU is not announced, all > those reset signals are automatically released after board finish reset. >=20 > Detect FEAT_PERIPH_MCU bit in board_fix_fdt() and ft_board_setup() > functions and insert into device tree blob pcie "reset-gpios" and eth phy > "phy-reset-gpios" properties with corresponding MCU gpio definitions. > PCIe and eth PHY drivers then automatically release resets during device > initialization. Both U-Boot and Linux kernel drivers support those device > tree reset properties. >=20 > Initialization of lan switch on new HW board revision is more complicated. > Switch strapping pins are shared with switch RGMII pins. And strapping pi= ns > must be in specific configuration after releasing switch reset. Due to pin > sharing, it is first required to switch A385 side of switch pins into GPIO > mode, set strapping configuration, release switch from reset and after th= at > switch A385 pins back to RGMII mode. >=20 > Because this complicated setup is not supported by switch DSA drivers and > cannot be expressed easily in device tree, implement it manually in SPL > function spl_board_init(). So in proper U-Boot and OS/kernel would be lan > switch initialized and be in same configuration like it was on old HW boa= rd > revisions (where reset sequence did those steps at hardware level). >=20 > Signed-off-by: Pali Roh=C3=A1r Reviewed-by: Marek Beh=C3=BAn