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PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230016)(4636009)(346002)(136003)(39860400002)(376002)(396003)(46966006)(36840700001)(40470700004)(86362001)(478600001)(7696005)(40460700003)(41300700001)(36860700001)(6666004)(5660300002)(82310400005)(2906002)(81166007)(47076005)(40480700001)(26005)(2616005)(426003)(83380400001)(1076003)(356005)(336012)(82740400003)(70206006)(8936002)(8676002)(4326008)(70586007)(54906003)(6916009)(36756003)(186003)(316002)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Aug 2022 18:00:28.4759 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cf43b7bb-22e8-4891-df70-08da770c618f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT026.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7130 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: stylon.wang@amd.com, Tom Chung , Sunpeng.Li@amd.com, Harry.Wentland@amd.com, qingqing.zhuo@amd.com, Rodrigo.Siqueira@amd.com, roman.li@amd.com, solomon.chiu@amd.com, Aurabindo.Pillai@amd.com, wayne.lin@amd.com, Bhawanpreet.Lakha@amd.com, agustin.gutierrez@amd.com, pavle.kotarac@amd.com Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Rodrigo Siqueira In the DCN code, we can find some references to three different pipe split policies but no clear description. This commit adds some kernel-doc that explains more about these options and a little bit of their impact. Reviewed-by: Harry Wentland Acked-by: Tom Chung Signed-off-by: Rodrigo Siqueira --- drivers/gpu/drm/amd/display/dc/dc.h | 35 +++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index f2accacae85b..07feb8551436 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -385,9 +385,31 @@ enum dcc_option { DCC_HALF_REQ_DISALBE = 2, }; +/** + * enum pipe_split_policy - Pipe split strategy supported by DCN + * + * This enum is used to define the pipe split policy supported by DCN. By + * default, DC favors MPC_SPLIT_DYNAMIC. + */ enum pipe_split_policy { + /** + * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the + * pipe in order to bring the best trade-off between performance and + * power consumption. This is the recommended option. + */ MPC_SPLIT_DYNAMIC = 0, + + /** + * @MPC_SPLIT_DYNAMIC: Avoid pipe split, which means that DC will not + * try any sort of split optimization. + */ MPC_SPLIT_AVOID = 1, + + /** + * @MPC_SPLIT_DYNAMIC: With this option, DC will only try to optimize + * the pipe utilization when using a single display; if the user + * connects to a second display, DC will avoid pipe split. + */ MPC_SPLIT_AVOID_MULT_DISP = 2, }; @@ -622,6 +644,14 @@ struct dc_state; struct resource_pool; struct dce_hwseq; +/** + * struct dc_debug_options - DC debug struct + * + * This struct provides a simple mechanism for developers to change some + * configurations, enable/disable features, and activate extra debug options. + * This can be very handy to narrow down whether some specific feature is + * causing an issue or not. + */ struct dc_debug_options { bool native422_support; bool disable_dsc; @@ -641,6 +671,11 @@ struct dc_debug_options { bool disable_stutter; bool use_max_lb; enum dcc_option disable_dcc; + + /** + * @pipe_split_policy: Define which pipe split policy is used by the + * display core. + */ enum pipe_split_policy pipe_split_policy; bool force_single_disp_pipe_split; bool voltage_align_fclk; -- 2.25.1