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Fri, 5 Aug 2022 13:00:32 -0500 From: Tom Chung To: Subject: [PATCH 20/32] drm/amd/display: Document some of the DML structs Date: Sat, 6 Aug 2022 01:58:14 +0800 Message-ID: <20220805175826.2992171-21-chiahsuan.chung@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220805175826.2992171-1-chiahsuan.chung@amd.com> References: <20220805175826.2992171-1-chiahsuan.chung@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ed98178e-2fca-4322-2618-08da770c685e X-MS-TrafficTypeDiagnostic: MN2PR12MB4128:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: iojsaDEBJW3/hcTU/qBMQfhn2mv9BNnYZ9XwZP6Lk5LYGS8msjzxBdy6Gy0cZN2pELevLp2qXa09IsATIGxYukAUihUca6P7SisVH/TeFXdWST153V10MrDNB3qEpJ3jhlJSPLqTqlRN05j9+PFE1ZqzobxjzFWO9gI7B+6wdARC1OyemQsSgMA0IsIxckhm7ltBPiRoQP78fYFjybqeSN900/qIRu7RYgCZX0xeoHBS9N1w0ovWztpI5XyU5o/CcS1757Ahqp56l4Yuz1RV21+jRDLs45OVGdCaUJGffOyDgyC6F2h0zfIgaXBdQJyhqad7synygX+34bq0Gy4i5vrf++vCYRHH9HlbXVgr+DEuWQRZ1yVVm5fFs+7RSRLenE0qDCPcZdoxOaYM2yfsI0we5Mmub9A8xONFnWUukZC03iLU9xmpuMwKFMLR1RFaQ8lewXA7O4Ir7uROXFCYqK9IE3gEsl1dEK+/WTIdNL1PBQm4DleZN0a9H4h8gYyF3I8ddig6Ih+8YS4vcwWkvdv9i6OhqkV7yUvTwD7pZR0SaPKl2xVCgJ2mEZvSZv/AOtH3QtzqIemgMSZW0hoQ8j8B4ihMPAESxj57MdeKLJdhA9XPvaLCQdwRBVHHihOq+AHKvdEmDFUiZyWdfkZgLlf+T6n0H9PeO0b0SPZXAbYZa/sWaQVlX67aIUq4YJ8zkSo3m/R4rqZ/42zb7ljM9X+sgwIHpzGA41k5ETKYXTDto4vL3cS48JVtsmCBqIQiZYmAiOyngQCCpRYY/I4z2Fyuj4W1aUoLm0BKivntXZM7pIG41DGvWJuMbhe3wQ262F4TNfW0rIo75PTU/aIvwg== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230016)(4636009)(136003)(39860400002)(346002)(376002)(396003)(46966006)(36840700001)(40470700004)(26005)(36756003)(356005)(186003)(54906003)(1076003)(6916009)(40480700001)(82740400003)(4326008)(8676002)(82310400005)(81166007)(7696005)(86362001)(8936002)(6666004)(2616005)(70206006)(83380400001)(70586007)(2906002)(41300700001)(47076005)(426003)(40460700003)(478600001)(5660300002)(336012)(36860700001)(316002)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Aug 2022 18:00:40.0035 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ed98178e-2fca-4322-2618-08da770c685e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT068.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4128 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: stylon.wang@amd.com, Tom Chung , Sunpeng.Li@amd.com, Harry.Wentland@amd.com, qingqing.zhuo@amd.com, Rodrigo.Siqueira@amd.com, roman.li@amd.com, solomon.chiu@amd.com, Aurabindo.Pillai@amd.com, wayne.lin@amd.com, Bhawanpreet.Lakha@amd.com, agustin.gutierrez@amd.com, pavle.kotarac@amd.com Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Rodrigo Siqueira Reviewed-by: Harry Wentland Acked-by: Tom Chung Signed-off-by: Rodrigo Siqueira --- .../amd/display/dc/dml/display_mode_structs.h | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h index e8b094006d95..8538588e7754 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h @@ -26,6 +26,16 @@ #include "dc_features.h" #include "display_mode_enums.h" +/** + * DOC: overview + * + * Most of the DML code is automatically generated and tested via hardware + * description language. Usually, we use the reference _vcs_dpi in the code + * where VCS means "Verilog Compiled Simulator" and DPI stands for "Direct + * Programmer Interface". In other words, those structs can be used to + * interface with Verilog with other languages such as C. + */ + #ifndef __DISPLAY_MODE_STRUCTS_H__ #define __DISPLAY_MODE_STRUCTS_H__ @@ -159,6 +169,14 @@ struct _vcs_dpi_voltage_scaling_st { double dtbclk_mhz; }; +/** + * _vcs_dpi_soc_bounding_box_st: SOC definitions + * + * This struct maintains the SOC Bounding Box information for the ASIC; it + * defines things such as clock, voltage, performance, etc. Usually, we load + * these values from VBIOS; if something goes wrong, we use some hard-coded + * values, which will enable the ASIC to light up with limitations. + */ struct _vcs_dpi_soc_bounding_box_st { struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; /* @@ -166,6 +184,11 @@ struct _vcs_dpi_soc_bounding_box_st { * clock table. Do not use outside of *update_bw_boudning_box functions. */ struct _vcs_dpi_voltage_scaling_st _clock_tmp[DC__VOLTAGE_STATES]; + + /** + * @num_states: It represents the total of Display Power Management + * (DPM) supported by the specific ASIC. + */ unsigned int num_states; double sr_exit_time_us; double sr_enter_plus_exit_time_us; @@ -231,6 +254,14 @@ struct _vcs_dpi_soc_bounding_box_st { enum self_refresh_affinity allow_dram_self_refresh_or_dram_clock_change_in_vblank; }; +/** + * @_vcs_dpi_ip_params_st: IP configuraion for DCN blocks + * + * In this struct you can find the DCN configuration associated to the specific + * ASIC. For example, here we can save how many DPPs the ASIC is using and it + * is available. + * + */ struct _vcs_dpi_ip_params_st { bool use_min_dcfclk; bool clamp_min_dcfclk; @@ -283,6 +314,9 @@ struct _vcs_dpi_ip_params_st { unsigned int writeback_line_buffer_chroma_buffer_size; unsigned int max_page_table_levels; + /** + * @max_num_dpp: Maximum number of DPP supported in the target ASIC. + */ unsigned int max_num_dpp; unsigned int max_num_otg; unsigned int cursor_chunk_size; -- 2.25.1