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Fri, 5 Aug 2022 12:59:01 -0500 From: Tom Chung To: Subject: [PATCH 05/32] drm/amd/display: fix CAB allocation for multiple displays Date: Sat, 6 Aug 2022 01:57:59 +0800 Message-ID: <20220805175826.2992171-6-chiahsuan.chung@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220805175826.2992171-1-chiahsuan.chung@amd.com> References: <20220805175826.2992171-1-chiahsuan.chung@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 3eaef911-f717-4cb9-bafb-08da770c40b3 X-MS-TrafficTypeDiagnostic: BN8PR12MB4625:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: eBXsGHvKkeFxbWsal4XvGKAe7kkJ8ACSBCweM1zywaO3v5sru+TnZ2tqdu+dqiLtCkgPjPYIMSEFbuF+ojkgmxI8ICVxj4+vTF9Xb8RPzGNpwfPD5AeQEclmmHl4D5Qot6AebSmv5oqc3sT92siWSkw1UyDLyY4M2noazewrGEzq8XJr39twtPDFFfxPKtoynkqknikwoiQUt6BNOQcTjXZGmW7q8ZSeOYDCC+syWS7kncahxtJUQdSYZwpVA2G3xJJSZDXRrp2ZiGyniFf5cGWBK3iaeAnXcGYF6ookfGxDvb7FSM2awIcFySYlHkI/vk1McatxCFgij181LEUgB1815DKmv511SmXgAzY+BledFV3qrWIo0oCgRy/fWBs/0rqs28LwJ0k3EEzjcKM8uIoLK6ImRjikoDcYkL+FJGLw7u03kzZ8HNI/7O/0YOrqVXXkil3tAJHF7pEnqXzjgVsbTA8IPxWp9SfkrzhTC+2VZrhnmnwjgQW5dbRp1cclEP2OnESJoJWrCsqKYeJO0sCeMSsIFCEisAwjM7PwhF9VEuZawP7i74C0AgnuwwNMKfP6ah0pQBKGrFNwImzL5LFEWTcHDYW1293/Lf7rEljXb9oORUcDik8AsBdRuMVtq315DSnfztvRn/4Fob2aykrwkg21WIZRIAWvNEO41YTRj65ETEFpP+N1sWIKKpjTkDo2/yMopOckaqtANOI5nYyzMgS/yytg7SMAwBSVRgaYvDqjisqgeLSf4BWxIjYCphp/yZ5SdzHK++4/v6O1suSF72Jn6nIqRR2eoYcB3Pt4IShAbYFtrg57v8PumTpLtRchZcNuNSNFpn5J2FKfsA== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230016)(4636009)(376002)(396003)(346002)(39860400002)(136003)(36840700001)(40470700004)(46966006)(40460700003)(82740400003)(7696005)(41300700001)(86362001)(26005)(82310400005)(54906003)(478600001)(356005)(40480700001)(316002)(81166007)(426003)(36860700001)(47076005)(186003)(1076003)(6916009)(83380400001)(4326008)(8936002)(70206006)(2906002)(2616005)(336012)(8676002)(5660300002)(70586007)(36756003)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Aug 2022 17:59:33.2523 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3eaef911-f717-4cb9-bafb-08da770c40b3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT060.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB4625 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: stylon.wang@amd.com, Tom Chung , Sunpeng.Li@amd.com, Harry.Wentland@amd.com, qingqing.zhuo@amd.com, Rodrigo.Siqueira@amd.com, roman.li@amd.com, solomon.chiu@amd.com, Aurabindo Pillai , Alvin Lee , wayne.lin@amd.com, Bhawanpreet.Lakha@amd.com, agustin.gutierrez@amd.com, pavle.kotarac@amd.com Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Aurabindo Pillai [Why & How] When multiple displays are used, the underlying framebuffers could be two separate framebuffers, or a single large framebuffer. Fix the calculation logic for CAB to account for large framebuffer. Current logic assumes that any FB that the plane points to are independent. When a single FB is used on the system, this does 2 times allocation. Add a check to prevent duplicate allocation by checking if the base addresses are the same, and then ensuring that the if we allocate using the pitch, whole of the other fbs will be accounted for in the first allocation. Reviewed-by: Alvin Lee Acked-by: Tom Chung Signed-off-by: Aurabindo Pillai --- drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c index d38341f68b17..5ba503d80728 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c @@ -250,6 +250,7 @@ static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state *c uint32_t total_lines = 0; uint32_t lines_per_way = 0; uint32_t num_ways = 0; + uint32_t prev_addr_low = 0; for (i = 0; i < ctx->stream_count; i++) { stream = ctx->streams[i]; @@ -267,10 +268,20 @@ static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state *c plane = ctx->stream_status[i].plane_states[j]; // Calculate total surface size - surface_size = plane->plane_size.surface_pitch * + if (prev_addr_low != plane->address.grph.addr.u.low_part) { + /* if plane address are different from prev FB, then userspace allocated separate FBs*/ + surface_size += plane->plane_size.surface_pitch * plane->plane_size.surface_size.height * (plane->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4); + prev_addr_low = plane->address.grph.addr.u.low_part; + } else { + /* We have the same fb for all the planes. + * Xorg always creates one giant fb that holds all surfaces, + * so allocating it once is sufficient. + * */ + continue; + } // Convert surface size + starting address to number of cache lines required // (alignment accounted for) cache_lines_used += dcn32_cache_lines_for_surface(dc, surface_size, -- 2.25.1