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From: Tom Chung <chiahsuan.chung@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: stylon.wang@amd.com, Tom Chung <chiahsuan.chung@amd.com>,
	Sunpeng.Li@amd.com, Harry.Wentland@amd.com,
	qingqing.zhuo@amd.com, Rodrigo.Siqueira@amd.com,
	roman.li@amd.com, solomon.chiu@amd.com, Aurabindo.Pillai@amd.com,
	Alvin Lee <alvin.lee2@amd.com>,
	wayne.lin@amd.com, Chaitanya Dhere <chaitanya.dhere@amd.com>,
	Bhawanpreet.Lakha@amd.com, agustin.gutierrez@amd.com,
	pavle.kotarac@amd.com
Subject: [PATCH 06/32] drm/amd/display: Revert "fix 32 bit compilation errors in dc_dmub_srv.c"
Date: Sat, 6 Aug 2022 01:58:00 +0800	[thread overview]
Message-ID: <20220805175826.2992171-7-chiahsuan.chung@amd.com> (raw)
In-Reply-To: <20220805175826.2992171-1-chiahsuan.chung@amd.com>

From: Alvin Lee <alvin.lee2@amd.com>

[Description]
Revert commit that refactors SubVP calculation incorrectly.

Reviewed-by: Chaitanya Dhere <chaitanya.dhere@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 67 ++++++++++----------
 1 file changed, 33 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index 2d61c2a91cee..c7582f834a43 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -433,28 +433,27 @@ static void populate_subvp_cmd_drr_info(struct dc *dc,
 	pipe_data->pipe_config.vblank_data.drr_info.use_ramping = false; // for now don't use ramping
 	pipe_data->pipe_config.vblank_data.drr_info.drr_window_size_ms = 4; // hardcode 4ms DRR window for now
 
-	drr_frame_us = div64_s64(drr_timing->v_total * drr_timing->h_total,
-				 (int64_t)(drr_timing->pix_clk_100hz * 100) * 1000000);
+	drr_frame_us = drr_timing->v_total * drr_timing->h_total /
+			(double)(drr_timing->pix_clk_100hz * 100) * 1000000;
 	// P-State allow width and FW delays already included phantom_timing->v_addressable
-	mall_region_us = div64_s64(phantom_timing->v_addressable * phantom_timing->h_total,
-				   (int64_t)(phantom_timing->pix_clk_100hz * 100) * 1000000);
+	mall_region_us = phantom_timing->v_addressable * phantom_timing->h_total /
+			(double)(phantom_timing->pix_clk_100hz * 100) * 1000000;
 	min_drr_supported_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US;
-	min_vtotal_supported = div64_s64(drr_timing->pix_clk_100hz * 100 *
-					 (div64_s64((int64_t)min_drr_supported_us, 1000000)),
-					 (int64_t)drr_timing->h_total);
-
-	prefetch_us = div64_s64((phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total,
-				(int64_t)(phantom_timing->pix_clk_100hz * 100) * 1000000 +
-				dc->caps.subvp_prefetch_end_to_mall_start_us);
-	subvp_active_us = div64_s64(main_timing->v_addressable * main_timing->h_total,
-				    (int64_t)(main_timing->pix_clk_100hz * 100) * 1000000);
-	drr_active_us = div64_s64(drr_timing->v_addressable * drr_timing->h_total,
-				  (int64_t)(drr_timing->pix_clk_100hz * 100) * 1000000);
-	max_drr_vblank_us = div64_s64((int64_t)(subvp_active_us - prefetch_us - drr_active_us), 2) + drr_active_us;
+	min_vtotal_supported = drr_timing->pix_clk_100hz * 100 * ((double)min_drr_supported_us / 1000000) /
+			(double)drr_timing->h_total;
+
+	prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total /
+			(double)(phantom_timing->pix_clk_100hz * 100) * 1000000 +
+			dc->caps.subvp_prefetch_end_to_mall_start_us;
+	subvp_active_us = main_timing->v_addressable * main_timing->h_total /
+			(double)(main_timing->pix_clk_100hz * 100) * 1000000;
+	drr_active_us = drr_timing->v_addressable * drr_timing->h_total /
+			(double)(drr_timing->pix_clk_100hz * 100) * 1000000;
+	max_drr_vblank_us = (double)(subvp_active_us - prefetch_us - drr_active_us) / 2 + drr_active_us;
 	max_drr_mallregion_us = subvp_active_us - prefetch_us - mall_region_us;
 	max_drr_supported_us = max_drr_vblank_us > max_drr_mallregion_us ? max_drr_vblank_us : max_drr_mallregion_us;
-	max_vtotal_supported = div64_s64(drr_timing->pix_clk_100hz * 100 * (div64_s64((int64_t)max_drr_supported_us, 1000000)),
-					 (int64_t)drr_timing->h_total);
+	max_vtotal_supported = drr_timing->pix_clk_100hz * 100 * ((double)max_drr_supported_us / 1000000) /
+			(double)drr_timing->h_total;
 
 	pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported = min_vtotal_supported;
 	pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported = max_vtotal_supported;
@@ -548,10 +547,10 @@ static void update_subvp_prefetch_end_to_mall_start(struct dc *dc,
 	struct dc_crtc_timing *phantom_timing1 = &subvp_pipes[1]->stream->mall_stream_config.paired_stream->timing;
 	struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = NULL;
 
-	subvp0_prefetch_us = div64_s64((phantom_timing0->v_total - phantom_timing0->v_front_porch) * phantom_timing0->h_total,
-				       (int64_t)(phantom_timing0->pix_clk_100hz * 100) * 1000000 + dc->caps.subvp_prefetch_end_to_mall_start_us);
-	subvp1_prefetch_us = div64_s64((phantom_timing1->v_total - phantom_timing1->v_front_porch) * phantom_timing1->h_total,
-				       (int64_t)(phantom_timing1->pix_clk_100hz * 100) * 1000000 + dc->caps.subvp_prefetch_end_to_mall_start_us);
+	subvp0_prefetch_us = (phantom_timing0->v_total - phantom_timing0->v_front_porch) * phantom_timing0->h_total /
+				(double)(phantom_timing0->pix_clk_100hz * 100) * 1000000 + dc->caps.subvp_prefetch_end_to_mall_start_us;
+	subvp1_prefetch_us = (phantom_timing1->v_total - phantom_timing1->v_front_porch) * phantom_timing1->h_total /
+					(double)(phantom_timing1->pix_clk_100hz * 100) * 1000000 + dc->caps.subvp_prefetch_end_to_mall_start_us;
 
 	// Whichever SubVP PIPE has the smaller prefetch (including the prefetch end to mall start time)
 	// should increase it's prefetch time to match the other
@@ -559,16 +558,16 @@ static void update_subvp_prefetch_end_to_mall_start(struct dc *dc,
 		pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[1];
 		prefetch_delta_us = subvp0_prefetch_us - subvp1_prefetch_us;
 		pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines =
-			div64_s64(((div64_s64((int64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us), 1000000)) *
-				   (phantom_timing1->pix_clk_100hz * 100) + phantom_timing1->h_total - 1),
-				  (int64_t)phantom_timing1->h_total);
+					(((double)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) / 1000000) *
+					(phantom_timing1->pix_clk_100hz * 100) + phantom_timing1->h_total - 1) /
+					(double)phantom_timing1->h_total;
 	} else if (subvp1_prefetch_us >  subvp0_prefetch_us) {
 		pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[0];
 		prefetch_delta_us = subvp1_prefetch_us - subvp0_prefetch_us;
 		pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines =
-			div64_s64(((div64_s64((int64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us), 1000000)) *
-				   (phantom_timing0->pix_clk_100hz * 100) + phantom_timing0->h_total - 1),
-				  (int64_t)phantom_timing0->h_total);
+					(((double)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) / 1000000) *
+					(phantom_timing0->pix_clk_100hz * 100) + phantom_timing0->h_total - 1) /
+					(double)phantom_timing0->h_total;
 	}
 }
 
@@ -619,13 +618,13 @@ static void populate_subvp_cmd_pipe_info(struct dc *dc,
 
 	// Round up
 	pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines =
-		div64_s64(((div64_s64((int64_t)dc->caps.subvp_prefetch_end_to_mall_start_us, 1000000)) *
-			   (phantom_timing->pix_clk_100hz * 100) + phantom_timing->h_total - 1),
-			  (int64_t)phantom_timing->h_total);
+			(((double)dc->caps.subvp_prefetch_end_to_mall_start_us / 1000000) *
+			(phantom_timing->pix_clk_100hz * 100) + phantom_timing->h_total - 1) /
+			(double)phantom_timing->h_total;
 	pipe_data->pipe_config.subvp_data.processing_delay_lines =
-		div64_s64(((div64_s64((int64_t)dc->caps.subvp_fw_processing_delay_us, 1000000)) *
-			   (phantom_timing->pix_clk_100hz * 100) + phantom_timing->h_total - 1),
-			  (int64_t)phantom_timing->h_total);
+			(((double)dc->caps.subvp_fw_processing_delay_us / 1000000) *
+			(phantom_timing->pix_clk_100hz * 100) + phantom_timing->h_total - 1) /
+			(double)phantom_timing->h_total;
 	// Find phantom pipe index based on phantom stream
 	for (j = 0; j < dc->res_pool->pipe_count; j++) {
 		struct pipe_ctx *phantom_pipe = &context->res_ctx.pipe_ctx[j];
-- 
2.25.1


  parent reply	other threads:[~2022-08-05 17:59 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-05 17:57 [PATCH 00/32] DC Patches July 29 2022 Tom Chung
2022-08-05 17:57 ` [PATCH 01/32] drm/amd/display: Use pixels per container logic for DCN314 DCCG dividers Tom Chung
2022-08-05 17:57 ` [PATCH 02/32] drm/amd/display: Create FPU files for DCN314 Tom Chung
2022-08-05 17:57 ` [PATCH 03/32] drm/amd/display: Move populate dml pipes from DCN314 to dml Tom Chung
2022-08-05 17:57 ` [PATCH 04/32] drm/amd/display: Drop FPU flags from Makefile Tom Chung
2022-08-05 17:57 ` [PATCH 05/32] drm/amd/display: fix CAB allocation for multiple displays Tom Chung
2022-08-05 17:58 ` Tom Chung [this message]
2022-08-05 17:58 ` [PATCH 07/32] drm/amd/display: Add a variable to update FCLK latency Tom Chung
2022-08-05 17:58 ` [PATCH 08/32] drm/amd/display: Refactor SubVP calculation to remove FPU Tom Chung
2022-08-05 17:58 ` [PATCH 09/32] drm/amd/display: Fix TMDS 4K@60Hz YCbCr420 corruption issue Tom Chung
2022-08-05 17:58 ` [PATCH 10/32] drm/amd/display: Device flash garbage before get in OS Tom Chung
2022-08-05 17:58 ` [PATCH 11/32] drm/amd/display: Add 16 lines margin for SubVP Tom Chung
2022-08-05 17:58 ` [PATCH 12/32] drm/amd/display: Avoid MPC infinite loop Tom Chung
2022-08-05 17:58 ` [PATCH 13/32] drm/amd/display: Fix subvp calculations Tom Chung
2022-08-05 17:58 ` [PATCH 14/32] drm/amd/display: Fix HDMI VSIF V3 incorrect issue Tom Chung
2022-08-05 17:58 ` [PATCH 15/32] drm/amd/display: Add documentation to some of the cursor struct Tom Chung
2022-08-05 17:58 ` [PATCH 16/32] drm/amd/display: Add basic kernel doc to CRC code under DC Tom Chung
2022-08-05 17:58 ` [PATCH 17/32] drm/amd/display: Add some extra kernel doc to amdgpu_dm Tom Chung
2022-08-05 17:58 ` [PATCH 18/32] drm/amd/display: Document pipe split policy Tom Chung
2022-08-05 17:58 ` [PATCH 19/32] drm/amd/display: Expand documentation for timing Tom Chung
2022-08-05 17:58 ` [PATCH 20/32] drm/amd/display: Document some of the DML structs Tom Chung
2022-08-05 17:58 ` [PATCH 21/32] drm/amd/display: Allow alternate prefetch modes in DML for DCN32 Tom Chung
2022-08-05 17:58 ` [PATCH 22/32] drm/amd/display: Fix Compile-time Warning Tom Chung
2022-08-05 17:58 ` [PATCH 23/32] drm/amd/display: Fix VPG instancing for dcn314 HPO Tom Chung
2022-08-05 17:58 ` [PATCH 24/32] drm/amd/display: Check correct bounds for stream encoder instances for DCN303 Tom Chung
2022-08-05 17:58   ` Tom Chung
2022-08-05 17:58 ` [PATCH 25/32] drm/amd/display: Enable SubVP by default on DCN32 & DCN321 Tom Chung
2022-08-05 17:58 ` [PATCH 26/32] drm/amd/display: Correct DTBCLK for dcn314 Tom Chung
2022-08-05 17:58 ` [PATCH 27/32] drm/amd/display: Revert "attempt to fix the logic in commit_planes_for_stream()" Tom Chung
2022-08-05 17:58 ` [PATCH 28/32] drm/amd/display: For stereo keep "FLIP_ANY_FRAME" Tom Chung
2022-08-05 17:58 ` [PATCH 29/32] drm/amd/display: Don't try to enter MALL SS if stereo3d Tom Chung
2022-08-05 17:58 ` [PATCH 30/32] drm/amd/display: clear optc underflow before turn off odm clock Tom Chung
2022-08-05 17:58 ` [PATCH 31/32] drm/amd/display: Fix TDR eDP and USB4 display light up issue Tom Chung
2022-08-05 17:58 ` [PATCH 32/32] drm/amd/display: 3.2.197 Tom Chung
2022-08-08 15:38 ` [PATCH 00/32] DC Patches July 29 2022 Wheeler, Daniel

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