From: kernel test robot <lkp@intel.com>
To: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: llvm@lists.linux.dev, kbuild-all@lists.01.org
Subject: Re: [RFC PATCH 3/4] cxl: CXL Performance Monitoring Unit driver
Date: Sat, 13 Aug 2022 06:24:23 +0800 [thread overview]
Message-ID: <202208130612.shIDJG3a-lkp@intel.com> (raw)
In-Reply-To: <20220812151214.2025-4-Jonathan.Cameron@huawei.com>
Hi Jonathan,
[FYI, it's a private test report for your RFC patch.]
[auto build test WARNING on linus/master]
[also build test WARNING on next-20220812]
[cannot apply to arm-perf/for-next/perf v5.19]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Jonathan-Cameron/CXL-3-0-Performance-Monitoring-Unit-support/20220812-231616
base: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 7ebfc85e2cd7b08f518b526173e9a33b56b3913b
config: x86_64-randconfig-a014 (https://download.01.org/0day-ci/archive/20220813/202208130612.shIDJG3a-lkp@intel.com/config)
compiler: clang version 16.0.0 (https://github.com/llvm/llvm-project 5f1c7e2cc5a3c07cbc2412e851a7283c1841f520)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/4776483ba3a4979cc318906623d23fc1e02148a7
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Jonathan-Cameron/CXL-3-0-Performance-Monitoring-Unit-support/20220812-231616
git checkout 4776483ba3a4979cc318906623d23fc1e02148a7
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/cxl/
If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
>> drivers/cxl/cpmu.c:168:12: warning: address of array 'info->conf_counter_bm' will always evaluate to 'true' [-Wpointer-bool-conversion]
if (info->conf_counter_bm) {
~~ ~~~~~~^~~~~~~~~~~~~~~
1 warning generated.
vim +168 drivers/cxl/cpmu.c
91
92 /*
93 * All CPMU counters are discoverable via the Event Capabilities Registers.
94 * Each Event Capability register contains a a VID / GroupID.
95 * A counter may then count any combination (by summing) of events in
96 * that group which are in the Supported Events Bitmask.
97 * However, there are some complexities to the scheme.
98 * - Fixed function counters refer to an Event Capabilities register.
99 * That event capability register is not then used for Configurable
100 * counters.
101 * TODO: Support summed events.
102 */
103 static int cpmu_parse_caps(struct device *dev, struct cpmu_info *info)
104 {
105 DECLARE_BITMAP(fixed_counter_event_cap_bm, 32) = {0};
106 void __iomem *base = info->base;
107 u64 val, eval;
108 int i;
109
110 val = readq(base + CPMU_CAP_REG);
111 info->freeze_for_enable = FIELD_GET(CPMU_CAP_WRITEABLE_WHEN_FROZEN, val) &
112 FIELD_GET(CPMU_CAP_FREEZE, val);
113 if (!info->freeze_for_enable) {
114 dev_err(dev, "Driver does not support CPMUs that do not support freeze for enable\n");
115 return -ENODEV;
116 }
117
118 info->num_counters = FIELD_GET(CPMU_CAP_NUM_COUNTERS_MSK, val) + 1;
119 info->counter_width = FIELD_GET(CPMU_CAP_COUNTER_WIDTH_MSK, val);
120 info->num_event_capabilities = FIELD_GET(CPMU_CAP_NUM_EVN_CAP_REG_SUP_MSK, val) + 1;
121
122 info->filter_hdm = FIELD_GET(CPMU_CAP_FILTERS_SUP_MSK, val);
123 if (FIELD_GET(CPMU_CAP_INT, val))
124 info->irq = FIELD_GET(CPMU_CAP_MSI_N_MSK, val);
125 else
126 info->irq = -1;
127
128 /* First handle fixed function counters; note if configurable counters found */
129 for (i = 0; i < info->num_counters; i++) {
130 struct cpmu_event *cpmu_ev;
131 u32 events_msk;
132 u8 group_idx;
133
134 val = readq(base + CPMU_COUNTER_CFG_REG(i));
135
136 if (FIELD_GET(CPMU_COUNTER_CFG_TYPE_MSK, val) ==
137 CPMU_COUNTER_CFG_TYPE_CONFIGURABLE) {
138 set_bit(i, info->conf_counter_bm);
139 }
140
141 if (FIELD_GET(CPMU_COUNTER_CFG_TYPE_MSK, val) !=
142 CPMU_COUNTER_CFG_TYPE_FIXED_FUN)
143 continue;
144
145 /* In this case we know which fields are const */
146 group_idx = FIELD_GET(CPMU_COUNTER_CFG_EVENT_GRP_ID_IDX_MSK, val);
147 events_msk = FIELD_GET(CPMU_COUNTER_CFG_EVENTS_MSK, val);
148 eval = readq(base + CPMU_EVENT_CAP_REG(group_idx));
149 cpmu_ev = devm_kzalloc(dev, sizeof(*cpmu_ev), GFP_KERNEL);
150 if (!cpmu_ev)
151 return -ENOMEM;
152
153 cpmu_ev->vid = FIELD_GET(CPMU_EVENT_CAP_VENDOR_ID_MSK, eval);
154 cpmu_ev->gid = FIELD_GET(CPMU_EVENT_CAP_GROUP_ID_MSK, eval);
155 /* For a fixed purpose counter use the events mask from the counter CFG */
156 cpmu_ev->msk = events_msk;
157 cpmu_ev->configurable = false;
158 cpmu_ev->counter_idx = i;
159 /* This list add is never unwound as all entries deleted on remove */
160 list_add(&cpmu_ev->node, &info->cpmu_events);
161 /*
162 * Configurable counters must not use an Event Capability registers that
163 * is in use for a Fixed counter
164 */
165 set_bit(group_idx, fixed_counter_event_cap_bm);
166 }
167
> 168 if (info->conf_counter_bm) {
169 struct cpmu_event *cpmu_ev;
170 int j;
171 /* Walk event capabilities unused by fixed counters */
172 for_each_clear_bit(j, fixed_counter_event_cap_bm,
173 info->num_event_capabilities) {
174 cpmu_ev = devm_kzalloc(dev, sizeof(*cpmu_ev), GFP_KERNEL);
175 if (!cpmu_ev)
176 return -ENOMEM;
177
178 eval = readq(base + CPMU_EVENT_CAP_REG(j));
179 cpmu_ev->vid = FIELD_GET(CPMU_EVENT_CAP_VENDOR_ID_MSK, eval);
180 cpmu_ev->gid = FIELD_GET(CPMU_EVENT_CAP_GROUP_ID_MSK, eval);
181 cpmu_ev->msk = FIELD_GET(CPMU_EVENT_CAP_SUPPORTED_EVENTS_MSK, eval);
182 cpmu_ev->event_idx = j;
183 cpmu_ev->configurable = true;
184 list_add(&cpmu_ev->node, &info->cpmu_events);
185 }
186 }
187
188 return 0;
189 }
190
--
0-DAY CI Kernel Test Service
https://01.org/lkp
next prev parent reply other threads:[~2022-08-12 22:25 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-12 15:12 [RFC PATCH 0/4] CXL 3.0 Performance Monitoring Unit support Jonathan Cameron
2022-08-12 15:12 ` [RFC PATCH 1/4] cxl: Add function to count regblocks of a given type Jonathan Cameron
2022-08-12 15:12 ` [RFC PATCH 2/4] cxl/pci: Find and register CXL PMU devices Jonathan Cameron
2022-08-12 23:46 ` kernel test robot
2022-08-12 23:46 ` kernel test robot
2022-08-22 17:09 ` Jonathan Cameron
2022-08-12 15:12 ` [RFC PATCH 3/4] cxl: CXL Performance Monitoring Unit driver Jonathan Cameron
2022-08-12 22:24 ` kernel test robot [this message]
2022-08-12 15:12 ` [RFC PATCH 4/4] docs: perf: Minimal introduction the the CXL PMU device and driver Jonathan Cameron
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