From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from wout1-smtp.messagingengine.com (wout1-smtp.messagingengine.com [64.147.123.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C58FA10F5 for ; Mon, 15 Aug 2022 05:08:25 +0000 (UTC) Received: from compute3.internal (compute3.nyi.internal [10.202.2.43]) by mailout.west.internal (Postfix) with ESMTP id 2F79232004AE; Mon, 15 Aug 2022 01:08:24 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute3.internal (MEProxy); Mon, 15 Aug 2022 01:08:25 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= cc:cc:content-transfer-encoding:date:date:from:from:in-reply-to :in-reply-to:message-id:mime-version:references:reply-to:sender :subject:subject:to:to; s=fm2; t=1660540103; x=1660626503; bh=29 uAAq1TVY/O7ZEUaRe+3LcWY61wpaNsGqYURHUMEAQ=; b=Lv40otdXtr3OwindnT WjgvPehS8V6WPGFcblD/hR1waOQkqGMjINtWzTvfMc9n79ZAG2e8+RN0+L3rgPTj l/7hKUTjvkzNtdB1XFtc1eUgKTTecpVco3fZ/RYsB1P5m88BRDNxPoFuzqim+3D7 pf0eLDvwd5x9OC3PFPOHjYVR7XLyP69P3HHEUKgxAQwXp493L7cfUqqEl21gN9qx zp0BT269U1qhmj/3s9Pc6HhJC0ONNyj0QvYpyGkLLuQRQt2pwslDX7KgfmSWflhK pKmRPqyoaO3k//oYYrXO0ZW5zMRF4NM8Wdpe+QTj9VRW3ImjFnZBlirb7zSkFM7Y swtQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding:date:date :feedback-id:feedback-id:from:from:in-reply-to:in-reply-to :message-id:mime-version:references:reply-to:sender:subject :subject:to:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm1; t=1660540103; x=1660626503; bh=29uAAq1TVY/O7 ZEUaRe+3LcWY61wpaNsGqYURHUMEAQ=; b=QE0kSkO9TDbjd71LqM6FjE1EYAG82 eyJNBrE6n0W3mOl1qwtdGRa+GsK6dreQ0ydKJNijL8TS4mSkA+d8KCQ/Tqe9FDnU a1K/Bs0LMG9BbcuJDFMygPaMjk+btMra8wcQKkLLKP5lHe5GZY7TVOb9GAlvvVRr 9YnKA/HP+BkVKXeMGlRgSPf99I0qEXXOlRN+efuuTy/+ctdx+kMEmP8U+ibxlliP tECM8hvYyG5l8iWonuWSWgMlsNa99Upe4oMWndA/26eAXc8qtmDyjIk4gQHN6IuV 13+wHLL6y10Y5bUxz3EI1L9ttQGLft5g30VPBetqS44H3Taj4DLyIiqaQ== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvfedrvdehuddgleehucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvvefufffkofgjfhgggfestdekredtredttdenucfhrhhomhepufgrmhhu vghlucfjohhllhgrnhguuceoshgrmhhuvghlsehshhholhhlrghnugdrohhrgheqnecugg ftrfgrthhtvghrnhepudekteeuudehtdelteevgfduvddvjefhfedulefgudevgeeghefg udefiedtveetnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilhhfrh homhepshgrmhhuvghlsehshhholhhlrghnugdrohhrgh X-ME-Proxy: Feedback-ID: i0ad843c9:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Mon, 15 Aug 2022 01:08:22 -0400 (EDT) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , linux-sunxi@lists.linux.dev, Palmer Dabbelt , Paul Walmsley , Albert Ou , linux-riscv@lists.infradead.org Cc: Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Samuel Holland Subject: [PATCH 02/12] dt-bindings: riscv: Add T-HEAD C906 and C910 compatibles Date: Mon, 15 Aug 2022 00:08:05 -0500 Message-Id: <20220815050815.22340-3-samuel@sholland.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220815050815.22340-1-samuel@sholland.org> References: <20220815050815.22340-1-samuel@sholland.org> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The C906 and C910 are RISC-V CPU cores from T-HEAD Semiconductor. Notably, the C906 core is used in the Allwinner D1 SoC. Signed-off-by: Samuel Holland --- Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 873dd12f6e89..ce2161d9115a 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -38,6 +38,8 @@ properties: - sifive,u5 - sifive,u7 - canaan,k210 + - thead,c906 + - thead,c910 - const: riscv - items: - enum: -- 2.35.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C8A16C25B0D for ; Mon, 15 Aug 2022 05:08:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; 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Mon, 15 Aug 2022 01:08:22 -0400 (EDT) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , linux-sunxi@lists.linux.dev, Palmer Dabbelt , Paul Walmsley , Albert Ou , linux-riscv@lists.infradead.org Cc: Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Samuel Holland Subject: [PATCH 02/12] dt-bindings: riscv: Add T-HEAD C906 and C910 compatibles Date: Mon, 15 Aug 2022 00:08:05 -0500 Message-Id: <20220815050815.22340-3-samuel@sholland.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220815050815.22340-1-samuel@sholland.org> References: <20220815050815.22340-1-samuel@sholland.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220814_220826_031131_4FC64B71 X-CRM114-Status: UNSURE ( 8.18 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The C906 and C910 are RISC-V CPU cores from T-HEAD Semiconductor. Notably, the C906 core is used in the Allwinner D1 SoC. Signed-off-by: Samuel Holland --- Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 873dd12f6e89..ce2161d9115a 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -38,6 +38,8 @@ properties: - sifive,u5 - sifive,u7 - canaan,k210 + - thead,c906 + - thead,c910 - const: riscv - items: - enum: -- 2.35.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv