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DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?mNN+u/w5Lk3QbqpWmuTSLXuIs+pAKCZ72adesrgApIc/kVtPUpmyB3mB/4DW?= =?us-ascii?Q?AAglWVNTl7gUkLEUr3ECbqO83nT6GCxksgPRjEwtzn4VqjnQvdvJ2gxIBljN?= =?us-ascii?Q?zGa52YJRVa5k3+zOXu9pl5aKiQ1egDrPZKefq8/uzFj8N4wXKubBpVVDCWwr?= =?us-ascii?Q?AE185ZRaN5eogveYwstB+revUwyOgMCja26xJ42ygq0vnCCF+GOD316ZPh23?= =?us-ascii?Q?bTTWTHA0NixZqrY/QJFI8MG+4XUZRqVDRUq4VwzQ6Yb6zd2vyppwu5y9lyTP?= =?us-ascii?Q?KTDmrVYS1MogmM5TKW9xKWeKcV0PYI7y4jP2VMh4rBvTK5/e4WcYXmiGr/5T?= =?us-ascii?Q?+Byx5lvmQunDyoI8pKf3QZ1Ysi2Yz15IhgKDceQN1rSsa2kHJcNtheonHM8V?= =?us-ascii?Q?9q8mSkK53m9xhFNjC8QVq3kV6oVdJ4zhT1b8+VOlm0MzKvGL7bGqYcY6w9ta?= =?us-ascii?Q?1qezWIa9crTkgFkklqmn1KI6ZaqBKW0rwZ9yIid6zo3VQlFU0w9sgLgTPS2U?= =?us-ascii?Q?qUbNdvWQylIMaE/RCGvd6OR9Sa1snqhO6PEi68zhQwN693ayOxGhgPxZ2kDb?= =?us-ascii?Q?qvH2qlEmdYw4VD/ubUG726ZZaRMLkHduQp5LE/KEHmDtOE36tJvnig985NNg?= =?us-ascii?Q?UGn15OIC1aEXwtudLCxzzYTC9jz27FHNpexGDzpwEhGWZDVWr0+pQ7O36P7w?= =?us-ascii?Q?3aI54/cqHcidD+WaXF3v9S+lv7AuJQIZMvXmuD5k3e5oeAsHN5OlnKImhLeO?= =?us-ascii?Q?lW//DZAOyM76rD4X/4/e4CY0cvhvF/r0+Yi+5zxrY+p5iqV15o25y1sWQq5D?= =?us-ascii?Q?BILhAIOMKGxy5JWtwJ9P+6/+CX4K0trijV7kLCamFg8Bbd0a9Cjq9WdkzfE3?= =?us-ascii?Q?YF623nw43qJAFJnCLOZD4p5TP9jbHacFeJHnF3thATgYvNAdWZWrnC5f+nXm?= =?us-ascii?Q?7AXCTgD0n9VORCplIjHNKh5m5yYDxnpufBKJdAWioOfk0zDgL6KT8pS2qhPh?= =?us-ascii?Q?RekdX/GTyvGM2fsO1fBZP5XQqXCqgXGPhAqJp8SW63wKRjcWnfmyY3/aMwuK?= =?us-ascii?Q?cf4t1OMVR18YNTuW8Tt2WlEI8VmoX/M7wqfpJClZQeLV9Pu59Sfy0M91U1JO?= =?us-ascii?Q?pcdwKBWKrFNoy8DeXA5XMIgIhvV7DcX6eyaLs/Fon3C80LGuOQgsMIquIn4A?= =?us-ascii?Q?ckoCrYO8CJWNtF9i2i2Abh4CSMP4bt/qbDrWmpovAvzl4i0jpQwUgjhK4BEr?= =?us-ascii?Q?Pd/WTlHasVn8urN+JeZIc2zeuOfabmEx8kbiZOLhupGEBDfIEbhK3tgylbmj?= =?us-ascii?Q?4jDPzwRvaYFB2bN95tWl6Xzkm8tLRt2oU9I8vD+xqg2Mqr/na7I5DLKUoh8+?= =?us-ascii?Q?T6+4IZgr2X72FVj85J90g+lWlY37je2El3gWFg9AroAdn+YYd2XaaQ9MT/kL?= =?us-ascii?Q?bENhaSXAl/0mtgtbweT7GCj9Rtx8ugk9JTEIrXnvQ1tyUf7licBv/LhiqXOb?= =?us-ascii?Q?r1e5gJ72c0dAILWQ3/gUbFt1TuL8NxH4Y0ZmR+tsp3/0C0Um81H1pdv8YGJs?= =?us-ascii?Q?vqEnBAaL6q5v0p1rK1GMzDx3YM2ilra/6dgIkXG0pkTlkaJewk88zFAhx0S5?= =?us-ascii?Q?Dg=3D=3D?= X-MS-Exchange-CrossTenant-Network-Message-Id: 5184b351-6c94-4ad5-1593-08da80074c45 X-MS-Exchange-CrossTenant-AuthSource: CY5PR11MB6139.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Aug 2022 04:16:46.0474 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 8J7F3ZQLo8wUMzv204bNwe263r9DFAlolZFIxo1DNA64VZl7HLVurLLGJHvIjExz9dprm4O+QNM63qcqEB8zTk/TNm7HFo0SGVSA9xfHd5o= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR11MB3623 X-OriginatorOrg: intel.com Subject: Re: [Intel-gfx] [PATCH 13/39] drm/i915: move dpll under display.dpll X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Thu, Aug 11, 2022 at 06:07:24PM +0300, Jani Nikula wrote: >Move display related members under drm_i915_private display sub-struct. > >Signed-off-by: Jani Nikula >--- > drivers/gpu/drm/i915/display/icl_dsi.c | 12 +- > drivers/gpu/drm/i915/display/intel_ddi.c | 24 ++-- > drivers/gpu/drm/i915/display/intel_display.c | 4 +- > .../gpu/drm/i915/display/intel_display_core.h | 21 ++++ > .../drm/i915/display/intel_display_debugfs.c | 8 +- > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 112 +++++++++--------- > .../gpu/drm/i915/display/intel_pch_refclk.c | 2 +- > drivers/gpu/drm/i915/gvt/handlers.c | 4 +- > drivers/gpu/drm/i915/i915_drv.h | 21 ---- > 9 files changed, 104 insertions(+), 104 deletions(-) > >diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c >index 5dcfa7feffa9..49357e4ed3be 100644 >--- a/drivers/gpu/drm/i915/display/icl_dsi.c >+++ b/drivers/gpu/drm/i915/display/icl_dsi.c >@@ -641,13 +641,13 @@ static void gen11_dsi_gate_clocks(struct intel_encoder *encoder) > u32 tmp; > enum phy phy; > >- mutex_lock(&dev_priv->dpll.lock); >+ mutex_lock(&dev_priv->display.dpll.lock); > tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); > for_each_dsi_phy(phy, intel_dsi->phys) > tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); > > intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp); >- mutex_unlock(&dev_priv->dpll.lock); >+ mutex_unlock(&dev_priv->display.dpll.lock); > } > > static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder) >@@ -657,13 +657,13 @@ static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder) > u32 tmp; > enum phy phy; > >- mutex_lock(&dev_priv->dpll.lock); >+ mutex_lock(&dev_priv->display.dpll.lock); > tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); > for_each_dsi_phy(phy, intel_dsi->phys) > tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); > > intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp); >- mutex_unlock(&dev_priv->dpll.lock); >+ mutex_unlock(&dev_priv->display.dpll.lock); > } > > static bool gen11_dsi_is_clock_enabled(struct intel_encoder *encoder) >@@ -693,7 +693,7 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder, > enum phy phy; > u32 val; > >- mutex_lock(&dev_priv->dpll.lock); >+ mutex_lock(&dev_priv->display.dpll.lock); > > val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); > for_each_dsi_phy(phy, intel_dsi->phys) { >@@ -709,7 +709,7 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder, > > intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0); > >- mutex_unlock(&dev_priv->dpll.lock); >+ mutex_unlock(&dev_priv->display.dpll.lock); > } > > static void >diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c >index a4c8493f3ce7..23c8287b0262 100644 >--- a/drivers/gpu/drm/i915/display/intel_ddi.c >+++ b/drivers/gpu/drm/i915/display/intel_ddi.c >@@ -1425,7 +1425,7 @@ hsw_set_signal_levels(struct intel_encoder *encoder, > static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg, > u32 clk_sel_mask, u32 clk_sel, u32 clk_off) > { >- mutex_lock(&i915->dpll.lock); >+ mutex_lock(&i915->display.dpll.lock); > > intel_de_rmw(i915, reg, clk_sel_mask, clk_sel); > >@@ -1435,17 +1435,17 @@ static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg, > */ > intel_de_rmw(i915, reg, clk_off, 0); > >- mutex_unlock(&i915->dpll.lock); >+ mutex_unlock(&i915->display.dpll.lock); > } > > static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg, > u32 clk_off) > { >- mutex_lock(&i915->dpll.lock); >+ mutex_lock(&i915->display.dpll.lock); > > intel_de_rmw(i915, reg, 0, clk_off); > >- mutex_unlock(&i915->dpll.lock); >+ mutex_unlock(&i915->display.dpll.lock); > } > > static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg, >@@ -1720,12 +1720,12 @@ static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, > intel_de_write(i915, DDI_CLK_SEL(port), > icl_pll_to_ddi_clk_sel(encoder, crtc_state)); > >- mutex_lock(&i915->dpll.lock); >+ mutex_lock(&i915->display.dpll.lock); > > intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, > ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0); > >- mutex_unlock(&i915->dpll.lock); >+ mutex_unlock(&i915->display.dpll.lock); > } > > static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder) >@@ -1734,12 +1734,12 @@ static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder) > enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); > enum port port = encoder->port; > >- mutex_lock(&i915->dpll.lock); >+ mutex_lock(&i915->display.dpll.lock); > > intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, > 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); > >- mutex_unlock(&i915->dpll.lock); >+ mutex_unlock(&i915->display.dpll.lock); > > intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); > } >@@ -1824,7 +1824,7 @@ static void skl_ddi_enable_clock(struct intel_encoder *encoder, > if (drm_WARN_ON(&i915->drm, !pll)) > return; > >- mutex_lock(&i915->dpll.lock); >+ mutex_lock(&i915->display.dpll.lock); > > intel_de_rmw(i915, DPLL_CTRL2, > DPLL_CTRL2_DDI_CLK_OFF(port) | >@@ -1832,7 +1832,7 @@ static void skl_ddi_enable_clock(struct intel_encoder *encoder, > DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | > DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); > >- mutex_unlock(&i915->dpll.lock); >+ mutex_unlock(&i915->display.dpll.lock); > } > > static void skl_ddi_disable_clock(struct intel_encoder *encoder) >@@ -1840,12 +1840,12 @@ static void skl_ddi_disable_clock(struct intel_encoder *encoder) > struct drm_i915_private *i915 = to_i915(encoder->base.dev); > enum port port = encoder->port; > >- mutex_lock(&i915->dpll.lock); >+ mutex_lock(&i915->display.dpll.lock); > > intel_de_rmw(i915, DPLL_CTRL2, > 0, DPLL_CTRL2_DDI_CLK_OFF(port)); > >- mutex_unlock(&i915->dpll.lock); >+ mutex_unlock(&i915->display.dpll.lock); > } > > static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) >diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c >index 7db4ac27364d..efc0fa648736 100644 >--- a/drivers/gpu/drm/i915/display/intel_display.c >+++ b/drivers/gpu/drm/i915/display/intel_display.c >@@ -1487,7 +1487,7 @@ static void intel_encoders_update_prepare(struct intel_atomic_state *state) > * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits. > * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook. > */ >- if (i915->dpll.mgr) { >+ if (i915->display.dpll.mgr) { > for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { > if (intel_crtc_needs_modeset(new_crtc_state)) > continue; >@@ -5839,7 +5839,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, > > PIPE_CONF_CHECK_BOOL(double_wide); > >- if (dev_priv->dpll.mgr) { >+ if (dev_priv->display.dpll.mgr) { > PIPE_CONF_CHECK_P(shared_dpll); > > PIPE_CONF_CHECK_X(dpll_hw_state.dpll); >diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h >index 748d2a84e20e..f12ff36fef07 100644 >--- a/drivers/gpu/drm/i915/display/intel_display_core.h >+++ b/drivers/gpu/drm/i915/display/intel_display_core.h >@@ -12,6 +12,7 @@ > > #include "intel_display.h" > #include "intel_dmc.h" >+#include "intel_dpll_mgr.h" > #include "intel_gmbus.h" > > struct drm_i915_private; >@@ -24,6 +25,7 @@ struct intel_color_funcs; > struct intel_crtc; > struct intel_crtc_state; > struct intel_dpll_funcs; >+struct intel_dpll_mgr; if you include intel_dpll_mgr.h you don't need the fwd declaration? Reviewed-by: Lucas De Marchi Lucas De Marchi