From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5D2D2C32772 for ; Tue, 23 Aug 2022 09:11:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:Message-Id:Date:Subject:Cc:To :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=Jp/ft7IJclo43CBi/lAnxcAut5usjq4p6LUkd7eToWk=; b=IlWVwSTI/fvgOe JQSMkCNvpKiCTh8aJf64U1m8VJPQ7Z1TNFnPZv8USDBvu6vrs+CUjeJ2aLpsubzLRpikD2Etypl/A H7H67G7NTF9J/ZTQfJiqh6q2pWfr9pPMQPHP0JR5kYhOKQGt/atlpp1P+nb7HtAvjLLbiIwezbEDo VVdOa6yAW1e0eEgmskN3/9UJNoolw+evBo48SyMbm6Uy5g7as1JfEROMvzNVGpG0iNZhb7AmwSop5 MKdBPneWXTo2CBAZjiHrGraEpaSc9uqq26JY8rg1L1pt67seFOKHVVGWw1XgaHA36epWFizRXIfn0 Y337ufvGXbGBXstH99lQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oQPvT-004KQ6-2B; Tue, 23 Aug 2022 09:10:23 +0000 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oQPvN-004KIo-F9 for linux-arm-kernel@lists.infradead.org; Tue, 23 Aug 2022 09:10:20 +0000 Received: by mail-wr1-x42e.google.com with SMTP id e20so15699831wri.13 for ; Tue, 23 Aug 2022 02:10:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=message-id:date:subject:cc:to:from:from:to:cc; bh=2GEox6su7AoY4+aEAqSxNCHHTvFo9S3YrU+NFgyLh6M=; b=q9GKbI0mC9u3ZVdiR0XwtAj2Sv+LW2oXwXZJGh29tpEE9vE4lBN91EtDicNh2CTdG+ n4eyNcmuhRcY2tkbg/3s24892tRY+K1BRawtSEDJkJDtGeUYd8XiVuzfEDsigrTBPH/j 1bEprKm4GDguie8AVGxCytQWxmPBjItZKB32Q1uBgRQqwdeFqUQZXh+4jVdrnzAgRAo7 aaJ0csNmeTUuvvYiwjsnoO3swsFzGoWstLL6ySqPC8nsyWi192VACuWzvjRYWP4qx/N4 cmCWfeMx/c7MuYuL5dV/tNIp75X0MbRDB4VAFKxLuMjL/KXJQUVtWXJoL6/seswm86Qh pWqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=2GEox6su7AoY4+aEAqSxNCHHTvFo9S3YrU+NFgyLh6M=; b=oJx0SqBy1jQKFDsYEWrXxfRyT8ZdCBxhjQ8QObUl6xzX6EyuLCRy75Lup2hUCGI7z5 4xi9lKUoYxnItzGt7W8T6wMK8s4snbW5qbJF4hr4nINSKADVgxyyJWMB6emsxw5lmfHu 6XShIcxBGdn3ugdYr7bB33OOthKccsaqi1mXJQLEIwSgcLjJiNpATAKXtn98U6Zf3+pc dBIK4irwiM0YxbPD42Qzc1Uf3Pw2T6/UlBTmJlAnGq5+ZjH458tul/yP35WM1CDO+Xd1 iAbyBrcQnRYU+DDVcMls6PpQnKksrJ/3o4WAuEQgE3dvkjvOCm+PAXfs3CUKA+nudfC4 xcuQ== X-Gm-Message-State: ACgBeo34g/TtxijAkLLXY7bHyr0w6GzgQULT77gumiz4JAFgJirm2Lyr eYBdAvzgo8CIYsBLH0JD2Iq14g== X-Google-Smtp-Source: AA6agR7Qo0nSag2xxvg7vayzLIp13TZaGsEXPSOjjQe6WSAi9DLEUM0rn2oxZmdfBNRAqc1H4dZF6Q== X-Received: by 2002:adf:fb0e:0:b0:21a:34a2:5ca9 with SMTP id c14-20020adffb0e000000b0021a34a25ca9mr13092302wrr.472.1661245813218; Tue, 23 Aug 2022 02:10:13 -0700 (PDT) Received: from linaro.org ([2a00:23c5:6809:2201:4553:cf11:6cff:b293]) by smtp.gmail.com with ESMTPSA id w6-20020adfde86000000b002253d162491sm10760721wrl.52.2022.08.23.02.10.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Aug 2022 02:10:12 -0700 (PDT) From: Mike Leach To: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: mathieu.poirier@linaro.org, suzuki.poulose@arm.com, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-perf-users@vger.kernel.org, leo.yan@linaro.org, quic_jinlmao@quicinc.com, Mike Leach Subject: [PATCH v4 00/13] coresight: Add new API to allocate trace source ID values Date: Tue, 23 Aug 2022 10:09:56 +0100 Message-Id: <20220823091009.14121-1-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220823_021017_557377_05295711 X-CRM114-Status: GOOD ( 27.81 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The current method for allocating trace source ID values to sources is to use a fixed algorithm for CPU based sources of (cpu_num * 2 + 0x10). The STM is allocated ID 0x1. This fixed algorithm is used in both the CoreSight driver code, and by perf when writing the trace metadata in the AUXTRACE_INFO record. The method needs replacing as currently:- 1. It is inefficient in using available IDs. 2. Does not scale to larger systems with many cores and the algorithm has no limits so will generate invalid trace IDs for cpu number > 44. Additionally requirements to allocate additional system IDs on some systems have been seen. This patch set introduces an API that allows the allocation of trace IDs in a dynamic manner. Architecturally reserved IDs are never allocated, and the system is limited to allocating only valid IDs. Each of the current trace sources ETM3.x, ETM4.x and STM is updated to use the new API. For the ETMx.x devices IDs are allocated on certain events a) When using sysfs, an ID will be allocated on hardware enable, or a read of sysfs TRCTRACEID register and freed when the sysfs reset is written. b) When using perf, ID is allocated on during setup AUX event, and freed on event free. IDs are communicated using the AUX_OUTPUT_HW_ID packet. The ID allocator is notified when perf sessions start and stop so CPU based IDs are kept constant throughout any perf session. Note: This patchset breaks some backward compatibility for perf record and perf report. The version of the AUXTRACE_INFO has been updated to reflect the fact that the trace source IDs are generated differently. This will mean older versions of perf report cannot decode the newer file. Applies to coresight/next [4d45bc82df66] Tested on DB410c Changes since v3: 1) Fixed aarch32 build error in ETM3.x driver. Reported-by: kernel test robot Changes since v2: 1) Improved backward compatibility: (requested by James) Using the new version of perf on an old kernel will generate a usable file legacy metadata values are set by the new perf and will be used if mew ID packets are not present in the file. Using an older version of perf / simpleperf on an updated kernel may still work. The trace ID allocator has been updated to use the legacy ID values where possible, so generated file and used trace IDs will match up to the point where the legacy algorithm is broken anyway. 2) Various changes to the ID allocator and ID packet format. (suggested by Suzuki) 3) per CPU ID info in allocator now stored as atomic type to allow a passive read without taking the allocator spinlock. perf flow now allocates and releases ID values in setup_aux / free_event. Device enable and event enable use the passive read to set the allocated values. This simplifies the locking mechanisms on the perf run and fixes issues that arose with locking dependencies. Changes since v1: (after feedback & discussion with Mathieu & Suzuki). 1) API has changed. The global trace ID map is managed internally, so it is no longer passed in to the API functions. 2) perf record does not use sysfs to find the trace IDs. These are now output as AUX_OUTPUT_HW_ID events. The drivers, perf record, and perf report have been updated accordingly to generate and handle these events. Mike Leach (13): coresight: trace-id: Add API to dynamically assign Trace ID values coresight: Remove obsolete Trace ID unniqueness checks coresight: stm: Update STM driver to use Trace ID API coresight: etm4x: Update ETM4 driver to use Trace ID API coresight: etm3x: Update ETM3 driver to use Trace ID API coresight: etmX.X: stm: Remove trace_id() callback coresight: perf: traceid: Add perf notifiers for Trace ID perf: cs-etm: Move mapping of Trace ID and cpu into helper function perf: cs-etm: Update record event to use new Trace ID protocol kernel: events: Export perf_report_aux_output_id() perf: cs-etm: Handle PERF_RECORD_AUX_OUTPUT_HW_ID packet coresight: events: PERF_RECORD_AUX_OUTPUT_HW_ID used for Trace ID coresight: trace-id: Add debug & test macros to Trace ID allocation drivers/hwtracing/coresight/Makefile | 2 +- drivers/hwtracing/coresight/coresight-core.c | 49 +-- .../hwtracing/coresight/coresight-etm-perf.c | 23 ++ drivers/hwtracing/coresight/coresight-etm.h | 3 +- .../coresight/coresight-etm3x-core.c | 92 +++-- .../coresight/coresight-etm3x-sysfs.c | 27 +- .../coresight/coresight-etm4x-core.c | 79 ++++- .../coresight/coresight-etm4x-sysfs.c | 27 +- drivers/hwtracing/coresight/coresight-etm4x.h | 3 + drivers/hwtracing/coresight/coresight-stm.c | 49 +-- .../hwtracing/coresight/coresight-trace-id.c | 266 ++++++++++++++ .../hwtracing/coresight/coresight-trace-id.h | 78 +++++ include/linux/coresight-pmu.h | 35 +- include/linux/coresight.h | 3 - kernel/events/core.c | 1 + tools/include/linux/coresight-pmu.h | 48 ++- tools/perf/arch/arm/util/cs-etm.c | 21 +- .../perf/util/cs-etm-decoder/cs-etm-decoder.c | 7 + tools/perf/util/cs-etm.c | 331 +++++++++++++++--- tools/perf/util/cs-etm.h | 14 +- 20 files changed, 933 insertions(+), 225 deletions(-) create mode 100644 drivers/hwtracing/coresight/coresight-trace-id.c create mode 100644 drivers/hwtracing/coresight/coresight-trace-id.h -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2408EC32793 for ; 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Tue, 23 Aug 2022 02:10:12 -0700 (PDT) From: Mike Leach To: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: mathieu.poirier@linaro.org, suzuki.poulose@arm.com, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-perf-users@vger.kernel.org, leo.yan@linaro.org, quic_jinlmao@quicinc.com, Mike Leach Subject: [PATCH v4 00/13] coresight: Add new API to allocate trace source ID values Date: Tue, 23 Aug 2022 10:09:56 +0100 Message-Id: <20220823091009.14121-1-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The current method for allocating trace source ID values to sources is to use a fixed algorithm for CPU based sources of (cpu_num * 2 + 0x10). The STM is allocated ID 0x1. This fixed algorithm is used in both the CoreSight driver code, and by perf when writing the trace metadata in the AUXTRACE_INFO record. The method needs replacing as currently:- 1. It is inefficient in using available IDs. 2. Does not scale to larger systems with many cores and the algorithm has no limits so will generate invalid trace IDs for cpu number > 44. Additionally requirements to allocate additional system IDs on some systems have been seen. This patch set introduces an API that allows the allocation of trace IDs in a dynamic manner. Architecturally reserved IDs are never allocated, and the system is limited to allocating only valid IDs. Each of the current trace sources ETM3.x, ETM4.x and STM is updated to use the new API. For the ETMx.x devices IDs are allocated on certain events a) When using sysfs, an ID will be allocated on hardware enable, or a read of sysfs TRCTRACEID register and freed when the sysfs reset is written. b) When using perf, ID is allocated on during setup AUX event, and freed on event free. IDs are communicated using the AUX_OUTPUT_HW_ID packet. The ID allocator is notified when perf sessions start and stop so CPU based IDs are kept constant throughout any perf session. Note: This patchset breaks some backward compatibility for perf record and perf report. The version of the AUXTRACE_INFO has been updated to reflect the fact that the trace source IDs are generated differently. This will mean older versions of perf report cannot decode the newer file. Applies to coresight/next [4d45bc82df66] Tested on DB410c Changes since v3: 1) Fixed aarch32 build error in ETM3.x driver. Reported-by: kernel test robot Changes since v2: 1) Improved backward compatibility: (requested by James) Using the new version of perf on an old kernel will generate a usable file legacy metadata values are set by the new perf and will be used if mew ID packets are not present in the file. Using an older version of perf / simpleperf on an updated kernel may still work. The trace ID allocator has been updated to use the legacy ID values where possible, so generated file and used trace IDs will match up to the point where the legacy algorithm is broken anyway. 2) Various changes to the ID allocator and ID packet format. (suggested by Suzuki) 3) per CPU ID info in allocator now stored as atomic type to allow a passive read without taking the allocator spinlock. perf flow now allocates and releases ID values in setup_aux / free_event. Device enable and event enable use the passive read to set the allocated values. This simplifies the locking mechanisms on the perf run and fixes issues that arose with locking dependencies. Changes since v1: (after feedback & discussion with Mathieu & Suzuki). 1) API has changed. The global trace ID map is managed internally, so it is no longer passed in to the API functions. 2) perf record does not use sysfs to find the trace IDs. These are now output as AUX_OUTPUT_HW_ID events. The drivers, perf record, and perf report have been updated accordingly to generate and handle these events. Mike Leach (13): coresight: trace-id: Add API to dynamically assign Trace ID values coresight: Remove obsolete Trace ID unniqueness checks coresight: stm: Update STM driver to use Trace ID API coresight: etm4x: Update ETM4 driver to use Trace ID API coresight: etm3x: Update ETM3 driver to use Trace ID API coresight: etmX.X: stm: Remove trace_id() callback coresight: perf: traceid: Add perf notifiers for Trace ID perf: cs-etm: Move mapping of Trace ID and cpu into helper function perf: cs-etm: Update record event to use new Trace ID protocol kernel: events: Export perf_report_aux_output_id() perf: cs-etm: Handle PERF_RECORD_AUX_OUTPUT_HW_ID packet coresight: events: PERF_RECORD_AUX_OUTPUT_HW_ID used for Trace ID coresight: trace-id: Add debug & test macros to Trace ID allocation drivers/hwtracing/coresight/Makefile | 2 +- drivers/hwtracing/coresight/coresight-core.c | 49 +-- .../hwtracing/coresight/coresight-etm-perf.c | 23 ++ drivers/hwtracing/coresight/coresight-etm.h | 3 +- .../coresight/coresight-etm3x-core.c | 92 +++-- .../coresight/coresight-etm3x-sysfs.c | 27 +- .../coresight/coresight-etm4x-core.c | 79 ++++- .../coresight/coresight-etm4x-sysfs.c | 27 +- drivers/hwtracing/coresight/coresight-etm4x.h | 3 + drivers/hwtracing/coresight/coresight-stm.c | 49 +-- .../hwtracing/coresight/coresight-trace-id.c | 266 ++++++++++++++ .../hwtracing/coresight/coresight-trace-id.h | 78 +++++ include/linux/coresight-pmu.h | 35 +- include/linux/coresight.h | 3 - kernel/events/core.c | 1 + tools/include/linux/coresight-pmu.h | 48 ++- tools/perf/arch/arm/util/cs-etm.c | 21 +- .../perf/util/cs-etm-decoder/cs-etm-decoder.c | 7 + tools/perf/util/cs-etm.c | 331 +++++++++++++++--- tools/perf/util/cs-etm.h | 14 +- 20 files changed, 933 insertions(+), 225 deletions(-) create mode 100644 drivers/hwtracing/coresight/coresight-trace-id.c create mode 100644 drivers/hwtracing/coresight/coresight-trace-id.h -- 2.17.1