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From: Thomas Petazzoni via buildroot <buildroot@buildroot.org>
To: Bram Vlerick <bram.vlerick@openpixelsystems.org>
Cc: buildroot@buildroot.org
Subject: Re: [Buildroot] [PATCH 1/2] board/freescale/common/imx: align u-boot-spl to 4 bytes
Date: Tue, 23 Aug 2022 23:30:12 +0200	[thread overview]
Message-ID: <20220823233012.513e0bf8@windsurf> (raw)
In-Reply-To: <20220816120718.3021545-1-bram.vlerick@openpixelsystems.org>

Hello Bram,

On Tue, 16 Aug 2022 14:07:17 +0200
Bram Vlerick <bram.vlerick@openpixelsystems.org> wrote:

> When enable DM for SPL binary, the DTB part of SPL may not 4 bytes aligned.
> If u-boot-spl is not aligned, the offset of the DDR firmware is not 4
> byte aligned when u-boot-spl-ddr.bin is created. This causes the ddr
> firmware to not be loaded correctly at boot.
> 
> See imx-mkimage commit bba038d893046b44683182dba540f104dab80fe7 for
> implementation in imx-mkimage.
> 
> Signed-off-by: Bram Vlerick <bram.vlerick@openpixelsystems.org>
> ---
>  .../freescale/common/imx/imx8-bootloader-prepare.sh  | 12 ++++++++----
>  1 file changed, 8 insertions(+), 4 deletions(-)

Applied to master, thanks. Even though your patch was marked PATCH 1/2,
there was no PATCH 2/2 posted on the list. Was this a mistake?

Thanks!

Thomas
-- 
Thomas Petazzoni, CTO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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  reply	other threads:[~2022-08-23 21:30 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-16 12:07 [Buildroot] [PATCH 1/2] board/freescale/common/imx: align u-boot-spl to 4 bytes Bram Vlerick
2022-08-23 21:30 ` Thomas Petazzoni via buildroot [this message]
2022-08-24  7:38   ` Bram Vlerick
2022-09-17 12:32 ` Peter Korsgaard

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