From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BA3DEECAAD4 for ; Sun, 4 Sep 2022 09:41:57 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 75938826AD; Sun, 4 Sep 2022 11:41:55 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="R9EFh9lH"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 0B2C58005B; Sun, 4 Sep 2022 11:41:53 +0200 (CEST) Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 5736583FA1 for ; Sun, 4 Sep 2022 11:41:50 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id D10BEB80C0A; Sun, 4 Sep 2022 09:41:49 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 58913C433C1; Sun, 4 Sep 2022 09:41:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1662284508; bh=7WXvjMUHTXOnx7jbBfL/Hyss2Wor++LjNyACJWNWs+g=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=R9EFh9lHDRqFn8H8k++YXyw0ualzT/Zdde1gZGYiKigStZkJCx5YVFAChznz254p8 ms+ctKMIysMx5HQRlRvIdDlh2JlZZpqUNcy4kIxDdP/pRWMyECKU16j9juG3x06bsl D/p3lNC1pkH9l2Akn9LTCUDGuQahDALfi8uG6VDc/wR/KSaaXZwHEAscEFeyGWZ0zM EGMSNomw2mL3Sf9arghZ01qSH3zBOWLNJRNU7SevBhZI6l2jq/MecGrGstY+a+IbPD 1R4a5/4FvqSet8xw33XzeOVGgx93ymD1zylFdGJibVoBKiWl4W91rETjjohjy9EkVf o3q/3F0RZCbHA== Received: by pali.im (Postfix) id 765167F5; Sun, 4 Sep 2022 11:41:45 +0200 (CEST) Date: Sun, 4 Sep 2022 11:41:45 +0200 From: Pali =?utf-8?B?Um9ow6Fy?= To: Tony Dinh Cc: Stefan Roese , U-Boot Mailing List , Michael Walle , Simon Glass Subject: Re: [PATCH v2 3/8] timer: orion-timer: Add timer_get_boot_us() for BOOTSTAGE support Message-ID: <20220904094145.jbdyqdrx6l3dkqis@pali> References: <20220902062554.1197435-1-sr@denx.de> <20220902062554.1197435-4-sr@denx.de> <3e1fdcaf-2d9d-bcfb-3067-d8c723af52cb@denx.de> <20220904010819.5npwywx3znynglzf@pali> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: NeoMutt/20180716 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean On Saturday 03 September 2022 19:36:03 Tony Dinh wrote: > Hi Pali, > > On Sat, Sep 3, 2022 at 6:08 PM Pali Rohár wrote: > > > > On Saturday 03 September 2022 17:38:01 Tony Dinh wrote: > > > Hi Pali, > > > > > > Is there a way to get the CPU frequency from the board upon start up? > > > > > > Thanks, > > > Tony > > > > Hello! Each SoC has either fixed CPU frequency or has some bits in SAR > > register which say on which frequency is CPU running. SAR bits are SoC > > specific and are documented either in Functional Specifications or in > > Hardware Specifications (both documents are available for free all > > 32-bit Marvell SoCs except 375 and 39x). > > Thanks for the recap. I do remember you posted a patch for that detection. > https://lists.denx.de/pipermail/u-boot/2022-August/492034.html > > Just want to make sure that the SAR register is the only way we can > detect it in u-boot. The Kirkwood 6192 SoC on this Pogo V4 board can > run at 200 Mhz and 800 Mhz with frequency scaling in Linux. > > Thanks, > Tony Well, All those SoCs have more clocks which are used for different peripherals. TCLK is something like base block and CPU is connected to different clock. Settings for it CPU clock is also in SAR register (different bits). And then there can be something like CPU scaling and cpufreq driver with configuration via different registers which can modify divisor of the main CPU clock. Which effectively can lower CPU speed. This cpufreq part is not implemented in U-Boot and IIRC CPU clock divisor should be at 1 = full CPU speed.