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However, the DRM device isn't freed as long as the last user didn't close it, hence userspace can still call into the driver. Therefore protect the critical sections which are accessing those resources with drm_dev_enter() and drm_dev_exit(). Signed-off-by: Danilo Krummrich --- drivers/gpu/drm/arm/hdlcd_crtc.c | 49 ++++++++++++++++++++++++++++++-- 1 file changed, 47 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/arm/hdlcd_crtc.c b/drivers/gpu/drm/arm/hdlcd_crtc.c index 17d3ccf12245..bfc42d4a53c2 100644 --- a/drivers/gpu/drm/arm/hdlcd_crtc.c +++ b/drivers/gpu/drm/arm/hdlcd_crtc.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -39,27 +40,47 @@ static void hdlcd_crtc_cleanup(struct drm_crtc *crtc) { struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); + int idx; + + if (!drm_dev_enter(crtc->dev, &idx)) + return; /* stop the controller on cleanup */ hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0); + + drm_dev_exit(idx); } static int hdlcd_crtc_enable_vblank(struct drm_crtc *crtc) { struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); - unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK); + unsigned int mask; + int idx; + if (!drm_dev_enter(crtc->dev, &idx)) + return -ENODEV; + + mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK); hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask | HDLCD_INTERRUPT_VSYNC); + drm_dev_exit(idx); + return 0; } static void hdlcd_crtc_disable_vblank(struct drm_crtc *crtc) { struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); - unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK); + unsigned int mask; + int idx; + if (!drm_dev_enter(crtc->dev, &idx)) + return; + + mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK); hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask & ~HDLCD_INTERRUPT_VSYNC); + + drm_dev_exit(idx); } static const struct drm_crtc_funcs hdlcd_crtc_funcs = { @@ -170,21 +191,33 @@ static void hdlcd_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *state) { struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); + int idx; + + if (!drm_dev_enter(crtc->dev, &idx)) + return; clk_prepare_enable(hdlcd->clk); hdlcd_crtc_mode_set_nofb(crtc); hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 1); drm_crtc_vblank_on(crtc); + + drm_dev_exit(idx); } static void hdlcd_crtc_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_state *state) { struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); + int idx; + + if (!drm_dev_enter(crtc->dev, &idx)) + return; drm_crtc_vblank_off(crtc); hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0); clk_disable_unprepare(hdlcd->clk); + + drm_dev_exit(idx); } static enum drm_mode_status hdlcd_crtc_mode_valid(struct drm_crtc *crtc, @@ -192,6 +225,10 @@ static enum drm_mode_status hdlcd_crtc_mode_valid(struct drm_crtc *crtc, { struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); long rate, clk_rate = mode->clock * 1000; + int idx; + + if (!drm_dev_enter(crtc->dev, &idx)) + return MODE_NOCLOCK; rate = clk_round_rate(hdlcd->clk, clk_rate); /* 0.1% seems a close enough tolerance for the TDA19988 on Juno */ @@ -200,6 +237,8 @@ static enum drm_mode_status hdlcd_crtc_mode_valid(struct drm_crtc *crtc, return MODE_NOCLOCK; } + drm_dev_exit(idx); + return MODE_OK; } @@ -267,6 +306,10 @@ static void hdlcd_plane_atomic_update(struct drm_plane *plane, struct hdlcd_drm_private *hdlcd; u32 dest_h; dma_addr_t scanout_start; + int idx; + + if (!drm_dev_enter(plane->dev, &idx)) + return; if (!fb) return; @@ -279,6 +322,8 @@ static void hdlcd_plane_atomic_update(struct drm_plane *plane, hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_PITCH, fb->pitches[0]); hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_COUNT, dest_h - 1); hdlcd_write(hdlcd, HDLCD_REG_FB_BASE, scanout_start); + + drm_dev_exit(idx); } static const struct drm_plane_helper_funcs hdlcd_plane_helper_funcs = { -- 2.37.2 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0964ECAAD3 for ; Mon, 5 Sep 2022 15:29:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238971AbiIEP3v (ORCPT ); Mon, 5 Sep 2022 11:29:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35650 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239179AbiIEP2t (ORCPT ); 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Mon, 05 Sep 2022 08:27:43 -0700 (PDT) Received: from pollux.redhat.com ([2a02:810d:4b40:2ee8:642:1aff:fe31:a15c]) by smtp.gmail.com with ESMTPSA id t19-20020a1709067c1300b00730b61d8a5esm5206061ejo.61.2022.09.05.08.27.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Sep 2022 08:27:43 -0700 (PDT) From: Danilo Krummrich To: daniel@ffwll.ch, airlied@linux.ie, tzimmermann@suse.de, mripard@kernel.org, liviu.dudau@arm.com, brian.starkey@arm.com Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Danilo Krummrich Subject: [PATCH RESEND drm-misc-next 6/7] drm/arm/hdlcd: crtc: protect device resources after removal Date: Mon, 5 Sep 2022 17:27:18 +0200 Message-Id: <20220905152719.128539-7-dakr@redhat.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220905152719.128539-1-dakr@redhat.com> References: <20220905152719.128539-1-dakr@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org (Hardware) resources which are bound to the driver and device lifecycle must not be accessed after the device and driver are unbound. However, the DRM device isn't freed as long as the last user didn't close it, hence userspace can still call into the driver. Therefore protect the critical sections which are accessing those resources with drm_dev_enter() and drm_dev_exit(). Signed-off-by: Danilo Krummrich --- drivers/gpu/drm/arm/hdlcd_crtc.c | 49 ++++++++++++++++++++++++++++++-- 1 file changed, 47 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/arm/hdlcd_crtc.c b/drivers/gpu/drm/arm/hdlcd_crtc.c index 17d3ccf12245..bfc42d4a53c2 100644 --- a/drivers/gpu/drm/arm/hdlcd_crtc.c +++ b/drivers/gpu/drm/arm/hdlcd_crtc.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -39,27 +40,47 @@ static void hdlcd_crtc_cleanup(struct drm_crtc *crtc) { struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); + int idx; + + if (!drm_dev_enter(crtc->dev, &idx)) + return; /* stop the controller on cleanup */ hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0); + + drm_dev_exit(idx); } static int hdlcd_crtc_enable_vblank(struct drm_crtc *crtc) { struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); - unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK); + unsigned int mask; + int idx; + if (!drm_dev_enter(crtc->dev, &idx)) + return -ENODEV; + + mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK); hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask | HDLCD_INTERRUPT_VSYNC); + drm_dev_exit(idx); + return 0; } static void hdlcd_crtc_disable_vblank(struct drm_crtc *crtc) { struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); - unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK); + unsigned int mask; + int idx; + if (!drm_dev_enter(crtc->dev, &idx)) + return; + + mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK); hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask & ~HDLCD_INTERRUPT_VSYNC); + + drm_dev_exit(idx); } static const struct drm_crtc_funcs hdlcd_crtc_funcs = { @@ -170,21 +191,33 @@ static void hdlcd_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *state) { struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); + int idx; + + if (!drm_dev_enter(crtc->dev, &idx)) + return; clk_prepare_enable(hdlcd->clk); hdlcd_crtc_mode_set_nofb(crtc); hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 1); drm_crtc_vblank_on(crtc); + + drm_dev_exit(idx); } static void hdlcd_crtc_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_state *state) { struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); + int idx; + + if (!drm_dev_enter(crtc->dev, &idx)) + return; drm_crtc_vblank_off(crtc); hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0); clk_disable_unprepare(hdlcd->clk); + + drm_dev_exit(idx); } static enum drm_mode_status hdlcd_crtc_mode_valid(struct drm_crtc *crtc, @@ -192,6 +225,10 @@ static enum drm_mode_status hdlcd_crtc_mode_valid(struct drm_crtc *crtc, { struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); long rate, clk_rate = mode->clock * 1000; + int idx; + + if (!drm_dev_enter(crtc->dev, &idx)) + return MODE_NOCLOCK; rate = clk_round_rate(hdlcd->clk, clk_rate); /* 0.1% seems a close enough tolerance for the TDA19988 on Juno */ @@ -200,6 +237,8 @@ static enum drm_mode_status hdlcd_crtc_mode_valid(struct drm_crtc *crtc, return MODE_NOCLOCK; } + drm_dev_exit(idx); + return MODE_OK; } @@ -267,6 +306,10 @@ static void hdlcd_plane_atomic_update(struct drm_plane *plane, struct hdlcd_drm_private *hdlcd; u32 dest_h; dma_addr_t scanout_start; + int idx; + + if (!drm_dev_enter(plane->dev, &idx)) + return; if (!fb) return; @@ -279,6 +322,8 @@ static void hdlcd_plane_atomic_update(struct drm_plane *plane, hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_PITCH, fb->pitches[0]); hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_COUNT, dest_h - 1); hdlcd_write(hdlcd, HDLCD_REG_FB_BASE, scanout_start); + + drm_dev_exit(idx); } static const struct drm_plane_helper_funcs hdlcd_plane_helper_funcs = { -- 2.37.2