From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 450B0C38145 for ; Tue, 6 Sep 2022 19:04:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229823AbiIFTEz (ORCPT ); Tue, 6 Sep 2022 15:04:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51392 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229754AbiIFTEa (ORCPT ); Tue, 6 Sep 2022 15:04:30 -0400 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 663516159; Tue, 6 Sep 2022 12:04:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1662491065; x=1694027065; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CqpjE8AeYqVUESQDZItbLGhRNWtI1PM4eAHT7QbqAhA=; b=R2nUuZmmB13/hO6Pl61gOht7+EJIbOgiLY9y8CmkJIo22NjocgIDVCh+ fIgcaaCyAbOAmFEDCgJrcYWIoe2IWe6cpWWXB2h5x4kNxyJn0Xs9OaafY D1M3mcM2sujJ5YxhfNL7re8290WhGrltsK8EcFKhb47zfY9DDZ6Kw1mum ichDrXWtFEet+0zGjGdMGrFDb7zP+5+6oOdTI43iNy0Z11ofif4PkwHjl 4ef82iYoHlePodCQuWiryT+E5Ow3h9/+E+kE0yKaf5VwyKJCJRWeWUf7r d/yzcqUhOy/APl474wT9FrNkrl1rDnmrTnRz858MjBH2NNTdM4Wm/D46f A==; X-IronPort-AV: E=McAfee;i="6500,9779,10462"; a="283677338" X-IronPort-AV: E=Sophos;i="5.93,294,1654585200"; d="scan'208";a="283677338" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Sep 2022 12:04:18 -0700 X-IronPort-AV: E=Sophos;i="5.93,294,1654585200"; d="scan'208";a="789782548" Received: from rhweight-wrk1.ra.intel.com ([137.102.106.43]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Sep 2022 12:04:18 -0700 From: matthew.gerlach@linux.intel.com To: hao.wu@intel.com, yilun.xu@intel.com, russell.h.weight@intel.com, basheer.ahmed.muddebihal@intel.com, trix@redhat.com, mdf@kernel.org, linux-fpga@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, tianfei.zhang@intel.com, corbet@lwn.net, gregkh@linuxfoundation.org, linux-serial@vger.kernel.org, jirislaby@kernel.org, geert+renesas@glider.be, andriy.shevchenko@linux.intel.com, niklas.soderlund+renesas@ragnatech.se, phil.edworthy@renesas.com, macro@orcam.me.uk, johan@kernel.org, lukas@wunner.de Cc: Basheer Ahmed Muddebihal , Matthew Gerlach Subject: [PATCH v1 3/5] fpga: dfl: Add DFHv1 Register Definitions Date: Tue, 6 Sep 2022 12:04:24 -0700 Message-Id: <20220906190426.3139760-4-matthew.gerlach@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220906190426.3139760-1-matthew.gerlach@linux.intel.com> References: <20220906190426.3139760-1-matthew.gerlach@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Basheer Ahmed Muddebihal This patch adds the definitions for DFHv1 header and related register bitfields. Signed-off-by: Basheer Ahmed Muddebihal Signed-off-by: Matthew Gerlach --- include/linux/dfl.h | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/include/linux/dfl.h b/include/linux/dfl.h index b5accdcfa368..61bcf20c1bc8 100644 --- a/include/linux/dfl.h +++ b/include/linux/dfl.h @@ -23,6 +23,16 @@ #define GUID_H 0x10 #define NEXT_AFU 0x18 +/* + * DFHv1 Register Offset definitons + * In DHFv1, DFH + GUID + CSR_START + CSR_SIZE_GROUP + PARAM_HDR + PARAM_DATA + * as common header registers + */ +#define DFHv1_CSR_ADDR 0x18 /* CSR Register start address */ +#define DFHv1_CSR_SIZE_GRP 0x20 /* Size of Reg Block and Group/tag */ +#define DFHv1_PARAM_HDR 0x28 /* Optional First Param header */ +#define DFHv1_PARAM_DATA 0x8 /* Offset of Param data from Param header */ + #define DFH_SIZE 0x8 /* Device Feature Header Register Bitfield */ @@ -30,8 +40,35 @@ #define DFH_REVISION GENMASK_ULL(15, 12) /* Feature revision */ #define DFH_NEXT_HDR_OFST GENMASK_ULL(39, 16) /* Offset to next DFH */ #define DFH_EOL BIT_ULL(40) /* End of list */ +#define DFH_VERSION GENMASK_ULL(59, 52) /* DFH version */ #define DFH_TYPE GENMASK_ULL(63, 60) /* Feature type */ +/* + * CSR Rel Bit, 1'b0 = relative (offset from feature DFH start), + * 1'b1 = absolute (ARM or other non-PCIe use) + */ +#define DFHv1_CSR_ADDR_REL BIT_ULL(0) + +/* + * CSR Header Register Bit Definitions + */ +#define DFHv1_CSR_ADDR_MASK GENMASK_ULL(63, 1) /* 63:1 of CSR address */ + +/* + * CSR SIZE Goup Register Bit Definitions + */ +#define DFHv1_CSR_SIZE_GRP_INSTANCE_ID GENMASK_ULL(15, 0) /* Enumeration instantiated IP */ +#define DFHv1_CSR_SIZE_GRP_GROUPING_ID GENMASK_ULL(30, 16) /* Group Features/interfaces */ +#define DFHv1_CSR_SIZE_GRP_HAS_PARAMS BIT_ULL(31) /* Presence of Parameters */ +#define DFHv1_CSR_SIZE_GRP_SIZE GENMASK_ULL(63, 32) /* Size of CSR Block in bytes */ + +/* + * PARAM Header Register Bit Definitions + */ +#define DFHv1_PARAM_HDR_ID GENMASK_ULL(15, 0) /* Id of this Param */ +#define DFHv1_PARAM_HDR_VERSION GENMASK_ULL(31, 16) /* Version Param */ +#define DFHv1_PARAM_HDR_NEXT_OFFSET GENMASK_ULL(63, 32) /* Offset of next Param */ + /** * enum dfl_id_type - define the DFL FIU types */ -- 2.25.1