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From: Wayne Lin <Wayne.Lin@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: stylon.wang@amd.com, Sunpeng.Li@amd.com, Harry.Wentland@amd.com,
	qingqing.zhuo@amd.com, Rodrigo.Siqueira@amd.com,
	roman.li@amd.com,
	Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>,
	solomon.chiu@amd.com, Aurabindo.Pillai@amd.com,
	wayne.lin@amd.com, Bhawanpreet.Lakha@amd.com,
	Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>,
	agustin.gutierrez@amd.com, pavle.kotarac@amd.com
Subject: [PATCH V3 29/47] drm/amd/display: Display distortion after hotplug 5K tiled display
Date: Wed, 14 Sep 2022 13:10:28 +0800	[thread overview]
Message-ID: <20220914051046.1131186-30-Wayne.Lin@amd.com> (raw)
In-Reply-To: <20220914051046.1131186-1-Wayne.Lin@amd.com>

From: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>

[Why]
During hot plug of specific 5K tiled display, sometimes both the tiles
are not synchronized resulting in distortion. The reason is that otgs of
both the tiles goes out of sync when otg workaround (dcnxxx_disable_otg_wa)
is applied for bandwidth optimization. The otg workaround reenables otg
but otg synchronization context is not reset and hence dc_trigger_sync()
does not resynchronize otg again.

[How]
Implement reset_sync_context_for_pipe() to reset the otg synchronization
context for the disabled pipe and its slave pipes when otg workaround is
applied.

Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>
---
 .../display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c    | 11 ++++++-----
 .../display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c  | 11 ++++++-----
 .../display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c  | 11 ++++++-----
 .../display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c  | 11 ++++++-----
 .../gpu/drm/amd/display/dc/core/dc_resource.c   | 17 +++++++++++++++++
 drivers/gpu/drm/amd/display/dc/inc/resource.h   |  4 ++++
 6 files changed, 45 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
index d43258e3cd4f..c1eaf571407a 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
@@ -104,7 +104,7 @@ static int dcn31_get_active_display_cnt_wa(
 	return display_count;
 }
 
-static void dcn31_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable)
+static void dcn31_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)
 {
 	struct dc *dc = clk_mgr_base->ctx->dc;
 	int i;
@@ -115,9 +115,10 @@ static void dcn31_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable)
 		if (pipe->top_pipe || pipe->prev_odm_pipe)
 			continue;
 		if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))) {
-			if (disable)
+			if (disable) {
 				pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);
-			else
+				reset_sync_context_for_pipe(dc, context, i);
+			} else
 				pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
 		}
 	}
@@ -216,11 +217,11 @@ void dcn31_update_clocks(struct clk_mgr *clk_mgr_base,
 	}
 
 	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
-		dcn31_disable_otg_wa(clk_mgr_base, true);
+		dcn31_disable_otg_wa(clk_mgr_base, context, true);
 
 		clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
 		dcn31_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
-		dcn31_disable_otg_wa(clk_mgr_base, false);
+		dcn31_disable_otg_wa(clk_mgr_base, context, false);
 
 		update_dispclk = true;
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
index cd86aa912e3c..fd4b79746f4b 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
@@ -126,7 +126,7 @@ static int dcn314_get_active_display_cnt_wa(
 	return display_count;
 }
 
-static void dcn314_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable)
+static void dcn314_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)
 {
 	struct dc *dc = clk_mgr_base->ctx->dc;
 	int i;
@@ -138,9 +138,10 @@ static void dcn314_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable)
 			continue;
 		if (pipe->stream && (pipe->stream->dpms_off || pipe->plane_state == NULL ||
 				     dc_is_virtual_signal(pipe->stream->signal))) {
-			if (disable)
+			if (disable) {
 				pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);
-			else
+				reset_sync_context_for_pipe(dc, context, i);
+			} else
 				pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
 		}
 	}
@@ -240,11 +241,11 @@ void dcn314_update_clocks(struct clk_mgr *clk_mgr_base,
 	}
 
 	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
-		dcn314_disable_otg_wa(clk_mgr_base, true);
+		dcn314_disable_otg_wa(clk_mgr_base, context, true);
 
 		clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
 		dcn314_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
-		dcn314_disable_otg_wa(clk_mgr_base, false);
+		dcn314_disable_otg_wa(clk_mgr_base, context, false);
 
 		update_dispclk = true;
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
index dd6abfba9253..7f481ab252d0 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
@@ -84,7 +84,7 @@ static int dcn315_get_active_display_cnt_wa(
 	return display_count;
 }
 
-static void dcn315_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable)
+static void dcn315_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)
 {
 	struct dc *dc = clk_mgr_base->ctx->dc;
 	int i;
@@ -96,9 +96,10 @@ static void dcn315_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable)
 			continue;
 		if (pipe->stream && (pipe->stream->dpms_off || pipe->plane_state == NULL ||
 				     dc_is_virtual_signal(pipe->stream->signal))) {
-			if (disable)
+			if (disable) {
 				pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);
-			else
+				reset_sync_context_for_pipe(dc, context, i);
+			} else
 				pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
 		}
 	}
@@ -180,12 +181,12 @@ static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base,
 	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
 		/* No need to apply the w/a if we haven't taken over from bios yet */
 		if (clk_mgr_base->clks.dispclk_khz)
-			dcn315_disable_otg_wa(clk_mgr_base, true);
+			dcn315_disable_otg_wa(clk_mgr_base, context, true);
 
 		clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
 		dcn315_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
 		if (clk_mgr_base->clks.dispclk_khz)
-			dcn315_disable_otg_wa(clk_mgr_base, false);
+			dcn315_disable_otg_wa(clk_mgr_base, context, false);
 
 		update_dispclk = true;
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
index 0cd3d2eb7ac7..187f5b27fdc8 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
@@ -112,7 +112,7 @@ static int dcn316_get_active_display_cnt_wa(
 	return display_count;
 }
 
-static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable)
+static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)
 {
 	struct dc *dc = clk_mgr_base->ctx->dc;
 	int i;
@@ -124,9 +124,10 @@ static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable)
 			continue;
 		if (pipe->stream && (pipe->stream->dpms_off || pipe->plane_state == NULL ||
 				     dc_is_virtual_signal(pipe->stream->signal))) {
-			if (disable)
+			if (disable) {
 				pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);
-			else
+				reset_sync_context_for_pipe(dc, context, i);
+			} else
 				pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
 		}
 	}
@@ -221,11 +222,11 @@ static void dcn316_update_clocks(struct clk_mgr *clk_mgr_base,
 	}
 
 	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
-		dcn316_disable_otg_wa(clk_mgr_base, true);
+		dcn316_disable_otg_wa(clk_mgr_base, context, true);
 
 		clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
 		dcn316_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
-		dcn316_disable_otg_wa(clk_mgr_base, false);
+		dcn316_disable_otg_wa(clk_mgr_base, context, false);
 
 		update_dispclk = true;
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 5bedee56acd4..8ee0d946bb2f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -3581,6 +3581,23 @@ void check_syncd_pipes_for_disabled_master_pipe(struct dc *dc,
 	}
 }
 
+void reset_sync_context_for_pipe(const struct dc *dc,
+	struct dc_state *context,
+	uint8_t pipe_idx)
+{
+	int i;
+	struct pipe_ctx *pipe_ctx_reset;
+
+	/* reset the otg sync context for the pipe and its slave pipes if any */
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		pipe_ctx_reset = &context->res_ctx.pipe_ctx[i];
+
+		if (((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx_reset) == pipe_idx) &&
+			IS_PIPE_SYNCD_VALID(pipe_ctx_reset)) || (i == pipe_idx))
+			SET_PIPE_SYNCD_TO_PIPE(pipe_ctx_reset, i);
+	}
+}
+
 uint8_t resource_transmitter_to_phy_idx(const struct dc *dc, enum transmitter transmitter)
 {
 	/* TODO - get transmitter to phy idx mapping from DMUB */
diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h
index a58f80ac94ba..c37d1141febe 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/resource.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h
@@ -219,6 +219,10 @@ void check_syncd_pipes_for_disabled_master_pipe(struct dc *dc,
 	struct dc_state *context,
 	uint8_t disabled_master_pipe_idx);
 
+void reset_sync_context_for_pipe(const struct dc *dc,
+	struct dc_state *context,
+	uint8_t pipe_idx);
+
 uint8_t resource_transmitter_to_phy_idx(const struct dc *dc, enum transmitter transmitter);
 
 const struct link_hwss *get_link_hwss(const struct dc_link *link,
-- 
2.37.3


  parent reply	other threads:[~2022-09-14  5:16 UTC|newest]

Thread overview: 59+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-14  5:09 [PATCH V3 00/47] DC Patches September 14, 2022 Wayne Lin
2022-09-14  5:10 ` [PATCH V3 01/47] drm/amd/display: Port DCN30 420 logic to DCN32 Wayne Lin
2022-09-14  5:10 ` [PATCH V3 02/47] drm/amd/display: Remove some unused definitions from DCN32/321 Wayne Lin
2022-09-14  5:10 ` [PATCH V3 03/47] drm/amd/display: Fix pipe split prediction Wayne Lin
2022-09-14  5:10 ` [PATCH V3 04/47] drm/amd/display: add debug option for dramclk_change_latency in apu Wayne Lin
2022-09-14  5:10 ` [PATCH V3 05/47] drm/amd/display: Various logs added Wayne Lin
2022-09-14  5:10 ` [PATCH V3 06/47] drm/amd/display: Only consider pixle rate div policy for DCN32+ Wayne Lin
2022-09-14  5:10 ` [PATCH V3 07/47] drm/amd/display: Fix double cursor on non-video RGB MPO Wayne Lin
2022-09-14  5:10 ` [PATCH V3 08/47] drm/amd/display: fix dcn315 memory channel count and width read Wayne Lin
2022-09-14  5:10 ` [PATCH V3 09/47] drm/amd/display: Assume an LTTPR is always present on fixed_vs links Wayne Lin
2022-09-14  5:10 ` [PATCH V3 10/47] drm/amd/display: rework recent update PHY state commit Wayne Lin
2022-09-14  5:10 ` [PATCH V3 11/47] drm/amd/display: support proper mst payload removal when link is not in mst mode in dc Wayne Lin
2022-09-14  5:10 ` [PATCH V3 12/47] drm/amd/display: For ODM seamless transition require AUTO mode Wayne Lin
2022-09-14  5:10 ` [PATCH V3 13/47] drm/amd/display: Add debug option for allocating extra way for cursor Wayne Lin
2022-09-14  5:10 ` [PATCH V3 14/47] drm/amd/display: SubVP pipe split case Wayne Lin
2022-09-14  5:10 ` [PATCH V3 15/47] drm/amd/display: Disable SubVP on driver disable Wayne Lin
2022-09-14  5:10 ` [PATCH V3 16/47] drm/amd/display: Fix SubVP way calculation Wayne Lin
2022-09-14  5:10 ` [PATCH V3 17/47] drm/amd/display: [FW Promotion] Release 0.0.134.0 Wayne Lin
2022-09-14  5:10 ` [PATCH V3 18/47] drm/amd/display: 3.2.203 Wayne Lin
2022-09-14  5:10 ` [PATCH V3 19/47] drm/amd/display: Refactor edp panel power sequencer(PPS) codes Wayne Lin
2022-09-14  5:10 ` [PATCH V3 20/47] drm/amd/display: update gamut remap if plane has changed Wayne Lin
2022-09-14  5:10 ` [PATCH V3 21/47] drm/amd/display: skip audio setup when audio stream is enabled Wayne Lin
2022-09-14  5:10 ` [PATCH V3 22/47] drm/amd/display: Uncomment SubVP pipe split assignment in driver Wayne Lin
2022-09-14  5:10 ` [PATCH V3 23/47] drm/amd/display: Fix urgent latency override for DCN32/DCN321 Wayne Lin
2022-09-14  5:10 ` [PATCH V3 24/47] drm/amd/display: correct hostvm flag Wayne Lin
2022-09-14  5:10 ` [PATCH V3 25/47] drm/amd/display: Added new DCN301 Asic Id Wayne Lin
2022-09-14  5:10 ` [PATCH V3 26/47] drm/amd/display: Removing 2 phys Wayne Lin
2022-09-14  5:10 ` [PATCH V3 27/47] drm/amd/display: Expose few dchubbub functions Wayne Lin
2022-09-14  5:10 ` [PATCH V3 28/47] drm/amd/display: Update dummy P-state search to use DCN32 DML Wayne Lin
2022-09-14  5:10 ` Wayne Lin [this message]
2022-09-14  5:10 ` [PATCH V3 30/47] drm/amd/display: Fix DP MST timeslot issue when fallback happened Wayne Lin
2022-09-14  5:10 ` [PATCH V3 31/47] drm/amd/display: Don't allocate DET for phantom pipes Wayne Lin
2022-09-14  5:10 ` [PATCH V3 32/47] drm/amd/display: Ignore k1/k2 values for virtual signal Wayne Lin
2022-09-14  5:10 ` [PATCH V3 33/47] drm/amd/display: increase dcn315 pstate change latency Wayne Lin
2022-09-14  5:10 ` [PATCH V3 34/47] drm/amd/display: do not compare integers of different widths Wayne Lin
2022-09-14  5:10 ` [PATCH V3 35/47] drm/amd/display: Assume connectors are on single slot Wayne Lin
2022-09-14  5:10 ` [PATCH V3 36/47] drm/amd/display: Enable committing subvp config Wayne Lin
2022-09-14  5:10 ` [PATCH V3 37/47] drm/amd/display: Add shift and mask for ICH_RESET_AT_END_OF_LINE Wayne Lin
2022-09-14  5:10 ` [PATCH V3 38/47] drm/amd/display: Disable OTG WA for the plane_state NULL case on DCN314 Wayne Lin
2022-09-14  5:10 ` [PATCH V3 39/47] drm/amd/display: Modify DML to adjust Vstartup Position Wayne Lin
2022-09-14  5:10 ` [PATCH V3 40/47] drm/amd/display: Revise Sink device string ID Wayne Lin
2022-09-14  5:10 ` [PATCH V3 41/47] drm/amd/display: log vertical interrupt 1 for debug Wayne Lin
2022-09-14  5:10 ` [PATCH V3 42/47] drm/amd/display: Do second pass through DML for DET calculation Wayne Lin
2022-09-14  5:10 ` [PATCH V3 43/47] drm/amd/display: update dccg based on HW delta Wayne Lin
2022-09-14  5:10 ` [PATCH V3 44/47] drm/amd/display: solve regression in update phy state refactor Wayne Lin
2022-09-14  5:10 ` [PATCH V3 45/47] drm/amd/display: correct num_dsc based on HW cap Wayne Lin
2022-09-14  5:10 ` [PATCH V3 46/47] drm/amd/display: Fix failures of disabling primary plans Wayne Lin
2022-09-14 13:31   ` Michel Dänzer
2022-09-14 13:40     ` Michel Dänzer
2022-09-14 16:30       ` Alex Hung
2022-09-14 16:55         ` Michel Dänzer
2022-09-14 16:55           ` Michel Dänzer
2022-09-14 20:08           ` Alex Hung
2022-09-14 20:08             ` Alex Hung
2022-09-15  8:55             ` Michel Dänzer
2022-09-15  8:55               ` Michel Dänzer
2022-09-15 20:44               ` Rodrigo Siqueira Jordao
2022-09-16  9:12                 ` Michel Dänzer
2022-09-14  5:10 ` [PATCH V3 47/47] drm/amd/display: 3.2.204 Wayne Lin

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