From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D2CDEC54EE9 for ; Fri, 16 Sep 2022 04:54:53 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 81BD784B9D; Fri, 16 Sep 2022 06:54:51 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="i/pcQJMn"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id BA71284BA4; Fri, 16 Sep 2022 06:54:49 +0200 (CEST) Received: from mail-pf1-x42c.google.com (mail-pf1-x42c.google.com [IPv6:2607:f8b0:4864:20::42c]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id E1ED184BA3 for ; Fri, 16 Sep 2022 06:54:46 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=judge.packham@gmail.com Received: by mail-pf1-x42c.google.com with SMTP id 9so9023277pfz.12 for ; Thu, 15 Sep 2022 21:54:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=ddfalIgmmaVyldD0SsMA0SUkFzI09zQNVlHYiv9/9CI=; b=i/pcQJMnIhBpJmG+c2AsGLskhqeWcwVZE+l/M73RRQht3uUf9hjhfEThek+7Ge3gaW Z/Ojrg5Z93mr6S6xQwH0Q93d2FamGQCDK3lzC902iXGHaYmURAdh3Kiti+a9hTe3fUlT t+Af948xsjbZ+lf1DoTaJHBm/XTlMF0EoTq7qiNUYW8JKnBtRRS69WxDMIBGL6TT4XbT sBawNqC21nqvbDT0U6+8kcHq+BnvgqXnjWW+RnxJuxm8IdV9SCXnf28uOQ361oR2CISF P42mf93dKCkaSXhR45d/4WcuoJOggOeKeXtFQp4T/Cie4PrhDH9AYS88Ubw/+Hubr4Ip M8hw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=ddfalIgmmaVyldD0SsMA0SUkFzI09zQNVlHYiv9/9CI=; b=qr5YWUs7FXW/79vDdCBVN6MgsnneRk9ewJHT4ld4uS0ZHdsko5kqQp51KfCuu4Z2Lr WJAnoVtA69Y0N0WqHx3wJNY5YCaT4nTCcWLKRox5eXr0CtN9QYUuY+9mO409VVT/gWzq gOvwIdApyDxhHdgZDxLUUAkTBkK+7rztcVWdZ6z7jj4kSTfEQyMswPcl12MIDd+5AYe5 al4Rz4W4CY0oX6O81izQtJaY1n4ZlMV/3b9qb+tGGYGoslAAmz8pCTuFk1pnBIMl9VSU TjoMLcaaZarZYjWtBIDkb552/AeHobvwtEAMSt41ltY5510kIg7b/dKpY6/MiO466g29 J3TA== X-Gm-Message-State: ACrzQf1WshtYW3e5M7Z6O//Vp6mz6g/JiIEE8PLEqXH7zxgmO4iloOZl vfA7L/F46KrC9bB8U1XxPUg= X-Google-Smtp-Source: AMsMyM44EiiCLmr7ilZQW2fNSeNPGCnMxmPHwDglZHMwbVXmj8XDGhBNL0vDX2l/8dRpLJOv8C+MjQ== X-Received: by 2002:a05:6a00:26d1:b0:53e:1d86:bead with SMTP id p17-20020a056a0026d100b0053e1d86beadmr3560577pfw.26.1663304085018; Thu, 15 Sep 2022 21:54:45 -0700 (PDT) Received: from chrisp-dl.atlnz.lc ([2001:df5:b000:22:1d7c:c94b:55d3:ab82]) by smtp.gmail.com with ESMTPSA id e7-20020a17090301c700b001782398648dsm12340346plh.8.2022.09.15.21.54.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Sep 2022 21:54:44 -0700 (PDT) From: Chris Packham To: Stefan Roese Cc: Elad Nachman , Vadym Kochan , Chris Packham , Joe Hershberger , Ramon Fried , u-boot@lists.denx.de Subject: [PATCH 1/7] net: mvneta: Add support for AlleyCat5 Date: Fri, 16 Sep 2022 16:54:17 +1200 Message-Id: <20220916045423.3635985-2-judge.packham@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220916045423.3635985-1-judge.packham@gmail.com> References: <20220916045423.3635985-1-judge.packham@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Add support for the AlleyCat5 SoC. This lacks the mbus from the other users of the mvneta.c driver so a new compatible string is needed to allow for a different window configuration. Signed-off-by: Chris Packham --- drivers/net/Kconfig | 2 +- drivers/net/mvneta.c | 66 ++++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 64 insertions(+), 4 deletions(-) diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 6bbbadc5ee..8df3dce6df 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -448,7 +448,7 @@ config MVGBE config MVNETA bool "Marvell Armada XP/385/3700 network interface support" - depends on ARMADA_XP || ARMADA_38X || ARMADA_3700 + depends on ARMADA_XP || ARMADA_38X || ARMADA_3700 || ALLEYCAT_5 select PHYLIB select DM_MDIO help diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c index d2c42c4396..07919d6d35 100644 --- a/drivers/net/mvneta.c +++ b/drivers/net/mvneta.c @@ -91,6 +91,8 @@ DECLARE_GLOBAL_DATA_PTR; #define MVNETA_WIN_SIZE_MASK (0xffff0000) #define MVNETA_BASE_ADDR_ENABLE 0x2290 #define MVNETA_BASE_ADDR_ENABLE_BIT 0x1 +#define MVNETA_AC5_CNM_DDR_TARGET 0x2 +#define MVNETA_AC5_CNM_DDR_ATTR 0xb #define MVNETA_PORT_ACCESS_PROTECT 0x2294 #define MVNETA_PORT_ACCESS_PROTECT_WIN0_RW 0x3 #define MVNETA_PORT_CONFIG 0x2400 @@ -282,6 +284,8 @@ struct mvneta_port { struct gpio_desc phy_reset_gpio; struct gpio_desc sfp_tx_disable_gpio; #endif + + uintptr_t dma_base; /* base address for DMA address decoding */ }; /* The mvneta_tx_desc and mvneta_rx_desc structures describe the @@ -513,10 +517,19 @@ static void mvneta_rxq_desc_num_update(struct mvneta_port *pp, static struct mvneta_rx_desc * mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq) { + struct mvneta_rx_desc *curr; int rx_desc = rxq->next_desc_to_proc; + /* validate RX descriptor */ + curr = rxq->descs + rx_desc; + if (curr->data_size == 0) { + /* do it to read real descriptor next time */ + DSB; + return NULL; + } + rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc); - return rxq->descs + rx_desc; + return curr; } /* Tx descriptors helper methods */ @@ -1343,6 +1356,29 @@ static void mvneta_conf_mbus_windows(struct mvneta_port *pp) mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); } +static void mvneta_conf_ac5_cnm_xbar_windows(struct mvneta_port *pp) +{ + int i; + + /* Clear all windows */ + for (i = 0; i < 6; i++) { + mvreg_write(pp, MVNETA_WIN_BASE(i), 0); + mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); + + if (i < 4) + mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); + } + + /* + * Setup window #0 base 0x0 to target XBAR port 2 (AMB2), attribute 0xb, size 4GB + * AMB2 address decoder remaps 0x0 to DDR 64 bit base address + */ + mvreg_write(pp, MVNETA_WIN_BASE(0), + (MVNETA_AC5_CNM_DDR_ATTR << 8) | MVNETA_AC5_CNM_DDR_TARGET); + mvreg_write(pp, MVNETA_WIN_SIZE(0), 0xffff0000); + mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, 0x3e); +} + /* Power up the port */ static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode) { @@ -1508,11 +1544,15 @@ static int mvneta_recv(struct udevice *dev, int flags, uchar **packetp) */ rx_desc = mvneta_rxq_next_desc_get(rxq); + if (!rx_desc) + return 0; + rx_status = rx_desc->status; if (!mvneta_rxq_desc_is_first_last(rx_status) || (rx_status & MVNETA_RXD_ERR_SUMMARY)) { mvneta_rx_error(pp, rx_desc); - /* leave the descriptor untouched */ + /* invalidate the descriptor */ + rx_desc->data_size = 0; return -EIO; } @@ -1525,13 +1565,15 @@ static int mvneta_recv(struct udevice *dev, int flags, uchar **packetp) * No cache invalidation needed here, since the rx_buffer's are * located in a uncached memory region */ - *packetp = data; + *packetp = data + pp->dma_base; /* * Only mark one descriptor as free * since only one was processed */ mvneta_rxq_desc_num_update(pp, rxq, 1, 1); + /* invalidate the descriptor */ + rx_desc->data_size = 0; } return rx_bytes; @@ -1544,6 +1586,11 @@ static int mvneta_probe(struct udevice *dev) struct ofnode_phandle_args sfp_args; #endif void *bd_space; + void *blob = (void *)gd->fdt_blob; + int node = dev_of_offset(dev); + const int *cell; + int len; + /* * Allocate buffer area for descs and rx_buffers. This is only @@ -1577,9 +1624,21 @@ static int mvneta_probe(struct udevice *dev) /* Configure MBUS address windows */ if (device_is_compatible(dev, "marvell,armada-3700-neta")) mvneta_bypass_mbus_windows(pp); + else if (device_is_compatible(dev, "marvell,armada-ac5-neta")) + mvneta_conf_ac5_cnm_xbar_windows(pp); else mvneta_conf_mbus_windows(pp); + /* fetch dma ranges property */ + cell = fdt_getprop(blob, node, "dma-ranges", &len); + if (cell && len >= 4 * sizeof(int)) { + /* RAZA - TODO do that in loop by address-cells size */ + pp->dma_base = fdt32_to_cpu(cell[1]); + pp->dma_base = (pp->dma_base << 32) | fdt32_to_cpu(cell[2]); + } else { + pp->dma_base = 0; + } + #if CONFIG_IS_ENABLED(DM_GPIO) if (!dev_read_phandle_with_args(dev, "sfp", NULL, 0, 0, &sfp_args) && ofnode_is_enabled(sfp_args.node)) @@ -1620,6 +1679,7 @@ static const struct eth_ops mvneta_ops = { static const struct udevice_id mvneta_ids[] = { { .compatible = "marvell,armada-370-neta" }, + { .compatible = "marvell,armada-ac5-neta" }, { .compatible = "marvell,armada-xp-neta" }, { .compatible = "marvell,armada-3700-neta" }, { } -- 2.37.3