* [Intel-gfx] [PATCH 1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup
@ 2022-09-16 8:31 Animesh Manna
2022-09-16 8:31 ` [Intel-gfx] [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario Animesh Manna
` (2 more replies)
0 siblings, 3 replies; 17+ messages in thread
From: Animesh Manna @ 2022-09-16 8:31 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
Simplified pps_get_register() which use get_pps_idx() hook to derive the
pps instance and get_pps_idx() will be initialized at pps_init().
v1: Initial version. Got r-b from Jani.
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
.../gpu/drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_pps.c | 15 ++++++++++-----
2 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 0da9b208d56e..b78b29951241 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1693,6 +1693,7 @@ struct intel_dp {
u8 (*preemph_max)(struct intel_dp *intel_dp);
u8 (*voltage_max)(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state);
+ int (*get_pps_idx)(struct intel_dp *intel_dp);
/* Displayport compliance testing */
struct intel_dp_compliance compliance;
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index 21944f5bf3a8..b972fa6ec00d 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -364,12 +364,10 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp,
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
int pps_idx = 0;
- memset(regs, 0, sizeof(*regs));
+ if (intel_dp->get_pps_idx)
+ pps_idx = intel_dp->get_pps_idx(intel_dp);
- if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
- pps_idx = bxt_power_sequencer_idx(intel_dp);
- else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- pps_idx = vlv_power_sequencer_pipe(intel_dp);
+ memset(regs, 0, sizeof(*regs));
regs->pp_ctrl = PP_CONTROL(pps_idx);
regs->pp_stat = PP_STATUS(pps_idx);
@@ -1432,6 +1430,13 @@ void intel_pps_init(struct intel_dp *intel_dp)
intel_dp->pps.initializing = true;
INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work);
+ if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
+ intel_dp->get_pps_idx = bxt_power_sequencer_idx;
+ else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
+ intel_dp->get_pps_idx = vlv_power_sequencer_pipe;
+ else
+ intel_dp->get_pps_idx = NULL;
+
pps_init_timestamps(intel_dp);
with_intel_pps_lock(intel_dp, wakeref) {
--
2.29.0
^ permalink raw reply related [flat|nested] 17+ messages in thread* [Intel-gfx] [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario 2022-09-16 8:31 [Intel-gfx] [PATCH 1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup Animesh Manna @ 2022-09-16 8:31 ` Animesh Manna 2022-09-16 8:58 ` Ville Syrjälä 2022-09-16 10:16 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup Patchwork 2022-09-16 14:29 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 2 siblings, 1 reply; 17+ messages in thread From: Animesh Manna @ 2022-09-16 8:31 UTC (permalink / raw) To: intel-gfx; +Cc: Jani Nikula From display gen12 onwards to support dual EDP two instances of pps added. Currently backlight controller and pps instance can be mapped together for a specific panel. Extended support for gen12 for dual EDP usage. v1: Iniital revision v2: Called intel_bios_panel_init w/o PNPID before intel_pps_init. [Jani] Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> --- drivers/gpu/drm/i915/display/intel_bios.c | 7 ------- drivers/gpu/drm/i915/display/intel_bios.h | 7 +++++++ drivers/gpu/drm/i915/display/intel_dp.c | 9 ++++++--- drivers/gpu/drm/i915/display/intel_pps.c | 2 +- 4 files changed, 14 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 28bdb936cd1f..5fd4c09dfa96 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -706,13 +706,6 @@ static int fallback_get_panel_type(struct drm_i915_private *i915, return 0; } -enum panel_type { - PANEL_TYPE_OPREGION, - PANEL_TYPE_VBT, - PANEL_TYPE_PNPID, - PANEL_TYPE_FALLBACK, -}; - static int get_panel_type(struct drm_i915_private *i915, const struct intel_bios_encoder_data *devdata, const struct edid *edid) diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h index e375405a7828..da01b13260ae 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.h +++ b/drivers/gpu/drm/i915/display/intel_bios.h @@ -231,6 +231,13 @@ struct mipi_pps_data { u16 panel_power_cycle_delay; } __packed; +enum panel_type { + PANEL_TYPE_OPREGION, + PANEL_TYPE_VBT, + PANEL_TYPE_PNPID, + PANEL_TYPE_FALLBACK, +}; + void intel_bios_init(struct drm_i915_private *dev_priv); void intel_bios_init_panel(struct drm_i915_private *dev_priv, struct intel_panel *panel, diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index c19e99ee06b6..6f7afa75ec4d 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5222,6 +5222,9 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, return false; } + intel_bios_init_panel(dev_priv, &intel_connector->panel, + encoder->devdata, NULL); + intel_pps_init(intel_dp); /* Cache DPCD and EDID for edp. */ @@ -5255,9 +5258,9 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, edid = ERR_PTR(-ENOENT); } intel_connector->edid = edid; - - intel_bios_init_panel(dev_priv, &intel_connector->panel, - encoder->devdata, IS_ERR(edid) ? NULL : edid); + if (intel_connector->panel.vbt.panel_type == PANEL_TYPE_FALLBACK) + intel_bios_init_panel(dev_priv, &intel_connector->panel, + encoder->devdata, IS_ERR(edid) ? NULL : edid); intel_panel_add_edid_fixed_modes(intel_connector, intel_connector->panel.vbt.drrs_type != DRRS_TYPE_NONE, diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c index b972fa6ec00d..4b8413382c5d 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -1430,7 +1430,7 @@ void intel_pps_init(struct intel_dp *intel_dp) intel_dp->pps.initializing = true; INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work); - if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) + if (IS_GEMINILAKE(i915) || IS_BROXTON(i915) || DISPLAY_VER(i915) >= 12) intel_dp->get_pps_idx = bxt_power_sequencer_idx; else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) intel_dp->get_pps_idx = vlv_power_sequencer_pipe; -- 2.29.0 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario 2022-09-16 8:31 ` [Intel-gfx] [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario Animesh Manna @ 2022-09-16 8:58 ` Ville Syrjälä 2022-09-16 11:02 ` Manna, Animesh 0 siblings, 1 reply; 17+ messages in thread From: Ville Syrjälä @ 2022-09-16 8:58 UTC (permalink / raw) To: Animesh Manna; +Cc: Jani Nikula, intel-gfx On Fri, Sep 16, 2022 at 02:01:02PM +0530, Animesh Manna wrote: > >From display gen12 onwards to support dual EDP two instances of pps added. > Currently backlight controller and pps instance can be mapped together > for a specific panel. Extended support for gen12 for dual EDP usage. > > v1: Iniital revision > v2: Called intel_bios_panel_init w/o PNPID before intel_pps_init. [Jani] > > Cc: Jani Nikula <jani.nikula@intel.com> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Cc: Uma Shankar <uma.shankar@intel.com> > Signed-off-by: Animesh Manna <animesh.manna@intel.com> > --- > drivers/gpu/drm/i915/display/intel_bios.c | 7 ------- > drivers/gpu/drm/i915/display/intel_bios.h | 7 +++++++ > drivers/gpu/drm/i915/display/intel_dp.c | 9 ++++++--- > drivers/gpu/drm/i915/display/intel_pps.c | 2 +- > 4 files changed, 14 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c > index 28bdb936cd1f..5fd4c09dfa96 100644 > --- a/drivers/gpu/drm/i915/display/intel_bios.c > +++ b/drivers/gpu/drm/i915/display/intel_bios.c > @@ -706,13 +706,6 @@ static int fallback_get_panel_type(struct drm_i915_private *i915, > return 0; > } > > -enum panel_type { > - PANEL_TYPE_OPREGION, > - PANEL_TYPE_VBT, > - PANEL_TYPE_PNPID, > - PANEL_TYPE_FALLBACK, > -}; > - > static int get_panel_type(struct drm_i915_private *i915, > const struct intel_bios_encoder_data *devdata, > const struct edid *edid) > diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h > index e375405a7828..da01b13260ae 100644 > --- a/drivers/gpu/drm/i915/display/intel_bios.h > +++ b/drivers/gpu/drm/i915/display/intel_bios.h > @@ -231,6 +231,13 @@ struct mipi_pps_data { > u16 panel_power_cycle_delay; > } __packed; > > +enum panel_type { > + PANEL_TYPE_OPREGION, > + PANEL_TYPE_VBT, > + PANEL_TYPE_PNPID, > + PANEL_TYPE_FALLBACK, > +}; > + > void intel_bios_init(struct drm_i915_private *dev_priv); > void intel_bios_init_panel(struct drm_i915_private *dev_priv, > struct intel_panel *panel, > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index c19e99ee06b6..6f7afa75ec4d 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -5222,6 +5222,9 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, > return false; > } > > + intel_bios_init_panel(dev_priv, &intel_connector->panel, > + encoder->devdata, NULL); We don't want to go for the fallback type here if we the VBT wants us to use pnpid. Maybe we should just remove the fallback type entirely? Or perhaps only use it if the VBT panel type is entirely invalid? > + > intel_pps_init(intel_dp); > > /* Cache DPCD and EDID for edp. */ > @@ -5255,9 +5258,9 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, > edid = ERR_PTR(-ENOENT); > } > intel_connector->edid = edid; > - > - intel_bios_init_panel(dev_priv, &intel_connector->panel, > - encoder->devdata, IS_ERR(edid) ? NULL : edid); > + if (intel_connector->panel.vbt.panel_type == PANEL_TYPE_FALLBACK) > + intel_bios_init_panel(dev_priv, &intel_connector->panel, > + encoder->devdata, IS_ERR(edid) ? NULL : edid); > > intel_panel_add_edid_fixed_modes(intel_connector, > intel_connector->panel.vbt.drrs_type != DRRS_TYPE_NONE, > diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c > index b972fa6ec00d..4b8413382c5d 100644 > --- a/drivers/gpu/drm/i915/display/intel_pps.c > +++ b/drivers/gpu/drm/i915/display/intel_pps.c > @@ -1430,7 +1430,7 @@ void intel_pps_init(struct intel_dp *intel_dp) > intel_dp->pps.initializing = true; > INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work); > > - if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) > + if (IS_GEMINILAKE(i915) || IS_BROXTON(i915) || DISPLAY_VER(i915) >= 12) > intel_dp->get_pps_idx = bxt_power_sequencer_idx; > else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) > intel_dp->get_pps_idx = vlv_power_sequencer_pipe; > -- > 2.29.0 -- Ville Syrjälä Intel ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario 2022-09-16 8:58 ` Ville Syrjälä @ 2022-09-16 11:02 ` Manna, Animesh 2022-09-16 11:29 ` Jani Nikula 0 siblings, 1 reply; 17+ messages in thread From: Manna, Animesh @ 2022-09-16 11:02 UTC (permalink / raw) To: Ville Syrjälä; +Cc: Nikula, Jani, intel-gfx > -----Original Message----- > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > Sent: Friday, September 16, 2022 2:28 PM > To: Manna, Animesh <animesh.manna@intel.com> > Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani <jani.nikula@intel.com>; > Shankar, Uma <uma.shankar@intel.com> > Subject: Re: [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario > > On Fri, Sep 16, 2022 at 02:01:02PM +0530, Animesh Manna wrote: > > >From display gen12 onwards to support dual EDP two instances of pps added. > > Currently backlight controller and pps instance can be mapped together > > for a specific panel. Extended support for gen12 for dual EDP usage. > > > > v1: Iniital revision > > v2: Called intel_bios_panel_init w/o PNPID before intel_pps_init. > > [Jani] > > > > Cc: Jani Nikula <jani.nikula@intel.com> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Cc: Uma Shankar <uma.shankar@intel.com> > > Signed-off-by: Animesh Manna <animesh.manna@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_bios.c | 7 ------- > > drivers/gpu/drm/i915/display/intel_bios.h | 7 +++++++ > > drivers/gpu/drm/i915/display/intel_dp.c | 9 ++++++--- > > drivers/gpu/drm/i915/display/intel_pps.c | 2 +- > > 4 files changed, 14 insertions(+), 11 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c > > b/drivers/gpu/drm/i915/display/intel_bios.c > > index 28bdb936cd1f..5fd4c09dfa96 100644 > > --- a/drivers/gpu/drm/i915/display/intel_bios.c > > +++ b/drivers/gpu/drm/i915/display/intel_bios.c > > @@ -706,13 +706,6 @@ static int fallback_get_panel_type(struct > drm_i915_private *i915, > > return 0; > > } > > > > -enum panel_type { > > - PANEL_TYPE_OPREGION, > > - PANEL_TYPE_VBT, > > - PANEL_TYPE_PNPID, > > - PANEL_TYPE_FALLBACK, > > -}; > > - > > static int get_panel_type(struct drm_i915_private *i915, > > const struct intel_bios_encoder_data *devdata, > > const struct edid *edid) > > diff --git a/drivers/gpu/drm/i915/display/intel_bios.h > > b/drivers/gpu/drm/i915/display/intel_bios.h > > index e375405a7828..da01b13260ae 100644 > > --- a/drivers/gpu/drm/i915/display/intel_bios.h > > +++ b/drivers/gpu/drm/i915/display/intel_bios.h > > @@ -231,6 +231,13 @@ struct mipi_pps_data { > > u16 panel_power_cycle_delay; > > } __packed; > > > > +enum panel_type { > > + PANEL_TYPE_OPREGION, > > + PANEL_TYPE_VBT, > > + PANEL_TYPE_PNPID, > > + PANEL_TYPE_FALLBACK, > > +}; > > + > > void intel_bios_init(struct drm_i915_private *dev_priv); void > > intel_bios_init_panel(struct drm_i915_private *dev_priv, > > struct intel_panel *panel, > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > > b/drivers/gpu/drm/i915/display/intel_dp.c > > index c19e99ee06b6..6f7afa75ec4d 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > @@ -5222,6 +5222,9 @@ static bool intel_edp_init_connector(struct intel_dp > *intel_dp, > > return false; > > } > > > > + intel_bios_init_panel(dev_priv, &intel_connector->panel, > > + encoder->devdata, NULL); > > We don't want to go for the fallback type here if we the VBT wants us to use > pnpid. Maybe we should just remove the fallback type entirely? Or perhaps only > use it if the VBT panel type is entirely invalid? Ok, Can I add like below? If (!PANEL_TYPE_FALLBACK) intel_pps_init(intel_dp); But to read EDID pps_init should be called before it. Or else I can enable both the pps and later disable the unused one. Regards, Animesh > > + > > intel_pps_init(intel_dp); > > > > /* Cache DPCD and EDID for edp. */ > > @@ -5255,9 +5258,9 @@ static bool intel_edp_init_connector(struct intel_dp > *intel_dp, > > edid = ERR_PTR(-ENOENT); > > } > > intel_connector->edid = edid; > > - > > - intel_bios_init_panel(dev_priv, &intel_connector->panel, > > - encoder->devdata, IS_ERR(edid) ? NULL : edid); > > + if (intel_connector->panel.vbt.panel_type == PANEL_TYPE_FALLBACK) > > + intel_bios_init_panel(dev_priv, &intel_connector->panel, > > + encoder->devdata, IS_ERR(edid) ? NULL : > edid); > > > > intel_panel_add_edid_fixed_modes(intel_connector, > > intel_connector->panel.vbt.drrs_type > != DRRS_TYPE_NONE, diff > > --git a/drivers/gpu/drm/i915/display/intel_pps.c > > b/drivers/gpu/drm/i915/display/intel_pps.c > > index b972fa6ec00d..4b8413382c5d 100644 > > --- a/drivers/gpu/drm/i915/display/intel_pps.c > > +++ b/drivers/gpu/drm/i915/display/intel_pps.c > > @@ -1430,7 +1430,7 @@ void intel_pps_init(struct intel_dp *intel_dp) > > intel_dp->pps.initializing = true; > > INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, > > edp_panel_vdd_work); > > > > - if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) > > + if (IS_GEMINILAKE(i915) || IS_BROXTON(i915) || DISPLAY_VER(i915) >= > > +12) > > intel_dp->get_pps_idx = bxt_power_sequencer_idx; > > else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) > > intel_dp->get_pps_idx = vlv_power_sequencer_pipe; > > -- > > 2.29.0 > > -- > Ville Syrjälä > Intel ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario 2022-09-16 11:02 ` Manna, Animesh @ 2022-09-16 11:29 ` Jani Nikula 2022-09-20 13:49 ` Manna, Animesh 0 siblings, 1 reply; 17+ messages in thread From: Jani Nikula @ 2022-09-16 11:29 UTC (permalink / raw) To: Manna, Animesh, Ville Syrjälä; +Cc: intel-gfx On Fri, 16 Sep 2022, "Manna, Animesh" <animesh.manna@intel.com> wrote: >> -----Original Message----- >> From: Ville Syrjälä <ville.syrjala@linux.intel.com> >> Sent: Friday, September 16, 2022 2:28 PM >> To: Manna, Animesh <animesh.manna@intel.com> >> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani <jani.nikula@intel.com>; >> Shankar, Uma <uma.shankar@intel.com> >> Subject: Re: [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario >> >> On Fri, Sep 16, 2022 at 02:01:02PM +0530, Animesh Manna wrote: >> > >From display gen12 onwards to support dual EDP two instances of pps added. >> > Currently backlight controller and pps instance can be mapped together >> > for a specific panel. Extended support for gen12 for dual EDP usage. >> > >> > v1: Iniital revision >> > v2: Called intel_bios_panel_init w/o PNPID before intel_pps_init. >> > [Jani] >> > >> > Cc: Jani Nikula <jani.nikula@intel.com> >> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> >> > Cc: Uma Shankar <uma.shankar@intel.com> >> > Signed-off-by: Animesh Manna <animesh.manna@intel.com> >> > --- >> > drivers/gpu/drm/i915/display/intel_bios.c | 7 ------- >> > drivers/gpu/drm/i915/display/intel_bios.h | 7 +++++++ >> > drivers/gpu/drm/i915/display/intel_dp.c | 9 ++++++--- >> > drivers/gpu/drm/i915/display/intel_pps.c | 2 +- >> > 4 files changed, 14 insertions(+), 11 deletions(-) >> > >> > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c >> > b/drivers/gpu/drm/i915/display/intel_bios.c >> > index 28bdb936cd1f..5fd4c09dfa96 100644 >> > --- a/drivers/gpu/drm/i915/display/intel_bios.c >> > +++ b/drivers/gpu/drm/i915/display/intel_bios.c >> > @@ -706,13 +706,6 @@ static int fallback_get_panel_type(struct >> drm_i915_private *i915, >> > return 0; >> > } >> > >> > -enum panel_type { >> > - PANEL_TYPE_OPREGION, >> > - PANEL_TYPE_VBT, >> > - PANEL_TYPE_PNPID, >> > - PANEL_TYPE_FALLBACK, >> > -}; >> > - >> > static int get_panel_type(struct drm_i915_private *i915, >> > const struct intel_bios_encoder_data *devdata, >> > const struct edid *edid) >> > diff --git a/drivers/gpu/drm/i915/display/intel_bios.h >> > b/drivers/gpu/drm/i915/display/intel_bios.h >> > index e375405a7828..da01b13260ae 100644 >> > --- a/drivers/gpu/drm/i915/display/intel_bios.h >> > +++ b/drivers/gpu/drm/i915/display/intel_bios.h >> > @@ -231,6 +231,13 @@ struct mipi_pps_data { >> > u16 panel_power_cycle_delay; >> > } __packed; >> > >> > +enum panel_type { >> > + PANEL_TYPE_OPREGION, >> > + PANEL_TYPE_VBT, >> > + PANEL_TYPE_PNPID, >> > + PANEL_TYPE_FALLBACK, >> > +}; >> > + I don't want enum panel_type exposed from intel_bios.c at all, there's no reason for that. >> > void intel_bios_init(struct drm_i915_private *dev_priv); void >> > intel_bios_init_panel(struct drm_i915_private *dev_priv, >> > struct intel_panel *panel, >> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c >> > b/drivers/gpu/drm/i915/display/intel_dp.c >> > index c19e99ee06b6..6f7afa75ec4d 100644 >> > --- a/drivers/gpu/drm/i915/display/intel_dp.c >> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c >> > @@ -5222,6 +5222,9 @@ static bool intel_edp_init_connector(struct intel_dp >> *intel_dp, >> > return false; >> > } >> > >> > + intel_bios_init_panel(dev_priv, &intel_connector->panel, >> > + encoder->devdata, NULL); >> >> We don't want to go for the fallback type here if we the VBT wants us to use >> pnpid. Maybe we should just remove the fallback type entirely? Or perhaps only >> use it if the VBT panel type is entirely invalid? > > Ok, Can I add like below? > If (!PANEL_TYPE_FALLBACK) > intel_pps_init(intel_dp); > > But to read EDID pps_init should be called before it. Or else I can enable both the pps and later disable the unused one. The first call should init everything if it can (panel type is *not* pnpid). Fallback is fine in that case too. If panel type indicates pnpid, intel_bios_init_panel() should set the pps id to, say, -1, so intel_pps_init() or more specifically bxt_power_sequencer_idx() can use some default or look at the hardware or whatever. intel_bios_init_panel() should probably also return a value on pnpid indicating intel_edp_init_connector() should call intel_bios_init_panel() again, this time with EDID. (Note: I kind of like separating returning the value and setting the pps id to -1. I don't want intel_edp_init_connector() to look at pps id, that's for pps, and I don't want to pass flags all the way to bxt_power_sequencer_idx() either.) BR, Jani. > > Regards, > Animesh > >> > + >> > intel_pps_init(intel_dp); >> > >> > /* Cache DPCD and EDID for edp. */ >> > @@ -5255,9 +5258,9 @@ static bool intel_edp_init_connector(struct intel_dp >> *intel_dp, >> > edid = ERR_PTR(-ENOENT); >> > } >> > intel_connector->edid = edid; >> > - >> > - intel_bios_init_panel(dev_priv, &intel_connector->panel, >> > - encoder->devdata, IS_ERR(edid) ? NULL : edid); >> > + if (intel_connector->panel.vbt.panel_type == PANEL_TYPE_FALLBACK) >> > + intel_bios_init_panel(dev_priv, &intel_connector->panel, >> > + encoder->devdata, IS_ERR(edid) ? NULL : >> edid); >> > >> > intel_panel_add_edid_fixed_modes(intel_connector, >> > intel_connector->panel.vbt.drrs_type >> != DRRS_TYPE_NONE, diff >> > --git a/drivers/gpu/drm/i915/display/intel_pps.c >> > b/drivers/gpu/drm/i915/display/intel_pps.c >> > index b972fa6ec00d..4b8413382c5d 100644 >> > --- a/drivers/gpu/drm/i915/display/intel_pps.c >> > +++ b/drivers/gpu/drm/i915/display/intel_pps.c >> > @@ -1430,7 +1430,7 @@ void intel_pps_init(struct intel_dp *intel_dp) >> > intel_dp->pps.initializing = true; >> > INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, >> > edp_panel_vdd_work); >> > >> > - if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) >> > + if (IS_GEMINILAKE(i915) || IS_BROXTON(i915) || DISPLAY_VER(i915) >= >> > +12) >> > intel_dp->get_pps_idx = bxt_power_sequencer_idx; >> > else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) >> > intel_dp->get_pps_idx = vlv_power_sequencer_pipe; >> > -- >> > 2.29.0 >> >> -- >> Ville Syrjälä >> Intel -- Jani Nikula, Intel Open Source Graphics Center ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario 2022-09-16 11:29 ` Jani Nikula @ 2022-09-20 13:49 ` Manna, Animesh 2022-09-26 10:35 ` Jani Nikula 0 siblings, 1 reply; 17+ messages in thread From: Manna, Animesh @ 2022-09-20 13:49 UTC (permalink / raw) To: Nikula, Jani, Ville Syrjälä; +Cc: intel-gfx > -----Original Message----- > From: Nikula, Jani <jani.nikula@intel.com> > Sent: Friday, September 16, 2022 5:00 PM > To: Manna, Animesh <animesh.manna@intel.com>; Ville Syrjälä > <ville.syrjala@linux.intel.com> > Cc: intel-gfx@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com> > Subject: RE: [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario > > On Fri, 16 Sep 2022, "Manna, Animesh" <animesh.manna@intel.com> wrote: > >> -----Original Message----- > >> From: Ville Syrjälä <ville.syrjala@linux.intel.com> > >> Sent: Friday, September 16, 2022 2:28 PM > >> To: Manna, Animesh <animesh.manna@intel.com> > >> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani > >> <jani.nikula@intel.com>; Shankar, Uma <uma.shankar@intel.com> > >> Subject: Re: [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP > >> scenario > >> > >> On Fri, Sep 16, 2022 at 02:01:02PM +0530, Animesh Manna wrote: > >> > >From display gen12 onwards to support dual EDP two instances of pps > added. > >> > Currently backlight controller and pps instance can be mapped > >> > together for a specific panel. Extended support for gen12 for dual EDP > usage. > >> > > >> > v1: Iniital revision > >> > v2: Called intel_bios_panel_init w/o PNPID before intel_pps_init. > >> > [Jani] > >> > > >> > Cc: Jani Nikula <jani.nikula@intel.com> > >> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > >> > Cc: Uma Shankar <uma.shankar@intel.com> > >> > Signed-off-by: Animesh Manna <animesh.manna@intel.com> > >> > --- > >> > drivers/gpu/drm/i915/display/intel_bios.c | 7 ------- > >> > drivers/gpu/drm/i915/display/intel_bios.h | 7 +++++++ > >> > drivers/gpu/drm/i915/display/intel_dp.c | 9 ++++++--- > >> > drivers/gpu/drm/i915/display/intel_pps.c | 2 +- > >> > 4 files changed, 14 insertions(+), 11 deletions(-) > >> > > >> > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c > >> > b/drivers/gpu/drm/i915/display/intel_bios.c > >> > index 28bdb936cd1f..5fd4c09dfa96 100644 > >> > --- a/drivers/gpu/drm/i915/display/intel_bios.c > >> > +++ b/drivers/gpu/drm/i915/display/intel_bios.c > >> > @@ -706,13 +706,6 @@ static int fallback_get_panel_type(struct > >> drm_i915_private *i915, > >> > return 0; > >> > } > >> > > >> > -enum panel_type { > >> > - PANEL_TYPE_OPREGION, > >> > - PANEL_TYPE_VBT, > >> > - PANEL_TYPE_PNPID, > >> > - PANEL_TYPE_FALLBACK, > >> > -}; > >> > - > >> > static int get_panel_type(struct drm_i915_private *i915, > >> > const struct intel_bios_encoder_data *devdata, > >> > const struct edid *edid) diff --git > >> > a/drivers/gpu/drm/i915/display/intel_bios.h > >> > b/drivers/gpu/drm/i915/display/intel_bios.h > >> > index e375405a7828..da01b13260ae 100644 > >> > --- a/drivers/gpu/drm/i915/display/intel_bios.h > >> > +++ b/drivers/gpu/drm/i915/display/intel_bios.h > >> > @@ -231,6 +231,13 @@ struct mipi_pps_data { > >> > u16 panel_power_cycle_delay; > >> > } __packed; > >> > > >> > +enum panel_type { > >> > + PANEL_TYPE_OPREGION, > >> > + PANEL_TYPE_VBT, > >> > + PANEL_TYPE_PNPID, > >> > + PANEL_TYPE_FALLBACK, > >> > +}; > >> > + > > I don't want enum panel_type exposed from intel_bios.c at all, there's no reason > for that. Hi Jani, Thanks for your inputs. I have made the changes as per your suggestion. I have a doubt which is mentioned below, currently have sent to trybot for quick feedback. https://patchwork.freedesktop.org/patch/503759/?series=108786&rev=1 > > >> > void intel_bios_init(struct drm_i915_private *dev_priv); void > >> > intel_bios_init_panel(struct drm_i915_private *dev_priv, > >> > struct intel_panel *panel, diff --git > >> > a/drivers/gpu/drm/i915/display/intel_dp.c > >> > b/drivers/gpu/drm/i915/display/intel_dp.c > >> > index c19e99ee06b6..6f7afa75ec4d 100644 > >> > --- a/drivers/gpu/drm/i915/display/intel_dp.c > >> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > >> > @@ -5222,6 +5222,9 @@ static bool intel_edp_init_connector(struct > >> > intel_dp > >> *intel_dp, > >> > return false; > >> > } > >> > > >> > + intel_bios_init_panel(dev_priv, &intel_connector->panel, > >> > + encoder->devdata, NULL); > >> > >> We don't want to go for the fallback type here if we the VBT wants us > >> to use pnpid. Maybe we should just remove the fallback type entirely? > >> Or perhaps only use it if the VBT panel type is entirely invalid? > > > > Ok, Can I add like below? > > If (!PANEL_TYPE_FALLBACK) > > intel_pps_init(intel_dp); > > > > But to read EDID pps_init should be called before it. Or else I can enable both > the pps and later disable the unused one. > > The first call should init everything if it can (panel type is *not* pnpid). Fallback is > fine in that case too. First time intel_bios_init_panel() will be called with null edid and panel type will be set to PANEL_TYPE_FALLBACK. > > If panel type indicates pnpid, intel_bios_init_panel() should set the pps id to, say, > -1, so intel_pps_init() or more specifically > bxt_power_sequencer_idx() can use some default or look at the hardware or > whatever. Currently checking for PANEL_TYPE_PNPID in intel_bios_init_panel() and setting pps id to -1. But I am not sure why special handling is needed in bxt_power_sequencer_idx(). Is backlight_controller value can be used to derive pps instance for PANEL_TYPE_PNPID. > > intel_bios_init_panel() should probably also return a value on pnpid indicating > intel_edp_init_connector() should call > intel_bios_init_panel() again, this time with EDID. (Note: I kind of like separating > returning the value and setting the pps id to -1. I don't want > intel_edp_init_connector() to look at pps id, that's for pps, and I don't want to > pass flags all the way to bxt_power_sequencer_idx() > either.) For PANEL_TYPE_PNPID am returning boolean retry, with that don’t need to move panet type enum to intel_bios.h. If the retry is true will call intel_bios_init_panel() with edid to check for PANEL_TYPE_PNPID. Regards, Animesh > > > BR, > Jani. > > > > > > Regards, > > Animesh > > > >> > + > >> > intel_pps_init(intel_dp); > >> > > >> > /* Cache DPCD and EDID for edp. */ @@ -5255,9 +5258,9 @@ static > >> > bool intel_edp_init_connector(struct intel_dp > >> *intel_dp, > >> > edid = ERR_PTR(-ENOENT); > >> > } > >> > intel_connector->edid = edid; > >> > - > >> > - intel_bios_init_panel(dev_priv, &intel_connector->panel, > >> > - encoder->devdata, IS_ERR(edid) ? NULL : edid); > >> > + if (intel_connector->panel.vbt.panel_type == PANEL_TYPE_FALLBACK) > >> > + intel_bios_init_panel(dev_priv, &intel_connector->panel, > >> > + encoder->devdata, IS_ERR(edid) ? NULL : > >> edid); > >> > > >> > intel_panel_add_edid_fixed_modes(intel_connector, > >> > > >> > intel_connector->panel.vbt.drrs_type > >> != DRRS_TYPE_NONE, diff > >> > --git a/drivers/gpu/drm/i915/display/intel_pps.c > >> > b/drivers/gpu/drm/i915/display/intel_pps.c > >> > index b972fa6ec00d..4b8413382c5d 100644 > >> > --- a/drivers/gpu/drm/i915/display/intel_pps.c > >> > +++ b/drivers/gpu/drm/i915/display/intel_pps.c > >> > @@ -1430,7 +1430,7 @@ void intel_pps_init(struct intel_dp *intel_dp) > >> > intel_dp->pps.initializing = true; > >> > INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, > >> > edp_panel_vdd_work); > >> > > >> > - if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) > >> > + if (IS_GEMINILAKE(i915) || IS_BROXTON(i915) || > >> > +DISPLAY_VER(i915) >= > >> > +12) > >> > intel_dp->get_pps_idx = bxt_power_sequencer_idx; > >> > else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) > >> > intel_dp->get_pps_idx = vlv_power_sequencer_pipe; > >> > -- > >> > 2.29.0 > >> > >> -- > >> Ville Syrjälä > >> Intel > > -- > Jani Nikula, Intel Open Source Graphics Center ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario 2022-09-20 13:49 ` Manna, Animesh @ 2022-09-26 10:35 ` Jani Nikula 2022-09-27 17:53 ` Manna, Animesh 0 siblings, 1 reply; 17+ messages in thread From: Jani Nikula @ 2022-09-26 10:35 UTC (permalink / raw) To: Manna, Animesh, Ville Syrjälä; +Cc: intel-gfx On Tue, 20 Sep 2022, "Manna, Animesh" <animesh.manna@intel.com> wrote: >> -----Original Message----- >> From: Nikula, Jani <jani.nikula@intel.com> >> Sent: Friday, September 16, 2022 5:00 PM >> To: Manna, Animesh <animesh.manna@intel.com>; Ville Syrjälä >> <ville.syrjala@linux.intel.com> >> Cc: intel-gfx@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com> >> Subject: RE: [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario >> >> On Fri, 16 Sep 2022, "Manna, Animesh" <animesh.manna@intel.com> wrote: >> >> -----Original Message----- >> >> From: Ville Syrjälä <ville.syrjala@linux.intel.com> >> >> Sent: Friday, September 16, 2022 2:28 PM >> >> To: Manna, Animesh <animesh.manna@intel.com> >> >> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani >> >> <jani.nikula@intel.com>; Shankar, Uma <uma.shankar@intel.com> >> >> Subject: Re: [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP >> >> scenario >> >> >> >> On Fri, Sep 16, 2022 at 02:01:02PM +0530, Animesh Manna wrote: >> >> > >From display gen12 onwards to support dual EDP two instances of pps >> added. >> >> > Currently backlight controller and pps instance can be mapped >> >> > together for a specific panel. Extended support for gen12 for dual EDP >> usage. >> >> > >> >> > v1: Iniital revision >> >> > v2: Called intel_bios_panel_init w/o PNPID before intel_pps_init. >> >> > [Jani] >> >> > >> >> > Cc: Jani Nikula <jani.nikula@intel.com> >> >> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> >> >> > Cc: Uma Shankar <uma.shankar@intel.com> >> >> > Signed-off-by: Animesh Manna <animesh.manna@intel.com> >> >> > --- >> >> > drivers/gpu/drm/i915/display/intel_bios.c | 7 ------- >> >> > drivers/gpu/drm/i915/display/intel_bios.h | 7 +++++++ >> >> > drivers/gpu/drm/i915/display/intel_dp.c | 9 ++++++--- >> >> > drivers/gpu/drm/i915/display/intel_pps.c | 2 +- >> >> > 4 files changed, 14 insertions(+), 11 deletions(-) >> >> > >> >> > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c >> >> > b/drivers/gpu/drm/i915/display/intel_bios.c >> >> > index 28bdb936cd1f..5fd4c09dfa96 100644 >> >> > --- a/drivers/gpu/drm/i915/display/intel_bios.c >> >> > +++ b/drivers/gpu/drm/i915/display/intel_bios.c >> >> > @@ -706,13 +706,6 @@ static int fallback_get_panel_type(struct >> >> drm_i915_private *i915, >> >> > return 0; >> >> > } >> >> > >> >> > -enum panel_type { >> >> > - PANEL_TYPE_OPREGION, >> >> > - PANEL_TYPE_VBT, >> >> > - PANEL_TYPE_PNPID, >> >> > - PANEL_TYPE_FALLBACK, >> >> > -}; >> >> > - >> >> > static int get_panel_type(struct drm_i915_private *i915, >> >> > const struct intel_bios_encoder_data *devdata, >> >> > const struct edid *edid) diff --git >> >> > a/drivers/gpu/drm/i915/display/intel_bios.h >> >> > b/drivers/gpu/drm/i915/display/intel_bios.h >> >> > index e375405a7828..da01b13260ae 100644 >> >> > --- a/drivers/gpu/drm/i915/display/intel_bios.h >> >> > +++ b/drivers/gpu/drm/i915/display/intel_bios.h >> >> > @@ -231,6 +231,13 @@ struct mipi_pps_data { >> >> > u16 panel_power_cycle_delay; >> >> > } __packed; >> >> > >> >> > +enum panel_type { >> >> > + PANEL_TYPE_OPREGION, >> >> > + PANEL_TYPE_VBT, >> >> > + PANEL_TYPE_PNPID, >> >> > + PANEL_TYPE_FALLBACK, >> >> > +}; >> >> > + >> >> I don't want enum panel_type exposed from intel_bios.c at all, there's no reason >> for that. > > Hi Jani, > > Thanks for your inputs. I have made the changes as per your suggestion. > I have a doubt which is mentioned below, currently have sent to trybot for quick feedback. > https://patchwork.freedesktop.org/patch/503759/?series=108786&rev=1 I'm not subscribed to the trybot list, so I can't easily reply with comments. Use trybot only to *test* stuff, not if you want human feedback. > >> >> >> > void intel_bios_init(struct drm_i915_private *dev_priv); void >> >> > intel_bios_init_panel(struct drm_i915_private *dev_priv, >> >> > struct intel_panel *panel, diff --git >> >> > a/drivers/gpu/drm/i915/display/intel_dp.c >> >> > b/drivers/gpu/drm/i915/display/intel_dp.c >> >> > index c19e99ee06b6..6f7afa75ec4d 100644 >> >> > --- a/drivers/gpu/drm/i915/display/intel_dp.c >> >> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c >> >> > @@ -5222,6 +5222,9 @@ static bool intel_edp_init_connector(struct >> >> > intel_dp >> >> *intel_dp, >> >> > return false; >> >> > } >> >> > >> >> > + intel_bios_init_panel(dev_priv, &intel_connector->panel, >> >> > + encoder->devdata, NULL); >> >> >> >> We don't want to go for the fallback type here if we the VBT wants us >> >> to use pnpid. Maybe we should just remove the fallback type entirely? >> >> Or perhaps only use it if the VBT panel type is entirely invalid? >> > >> > Ok, Can I add like below? >> > If (!PANEL_TYPE_FALLBACK) >> > intel_pps_init(intel_dp); >> > >> > But to read EDID pps_init should be called before it. Or else I can enable both >> the pps and later disable the unused one. >> >> The first call should init everything if it can (panel type is *not* pnpid). Fallback is >> fine in that case too. > > First time intel_bios_init_panel() will be called with null edid and panel type will be set to PANEL_TYPE_FALLBACK. > >> >> If panel type indicates pnpid, intel_bios_init_panel() should set the pps id to, say, >> -1, so intel_pps_init() or more specifically >> bxt_power_sequencer_idx() can use some default or look at the hardware or >> whatever. > > Currently checking for PANEL_TYPE_PNPID in intel_bios_init_panel() and setting pps id to -1. > But I am not sure why special handling is needed in bxt_power_sequencer_idx(). > Is backlight_controller value can be used to derive pps instance for PANEL_TYPE_PNPID. Backlight controller and pps index are basically the *same* thing. If PNPID is used, the backlight controller is uninitialized. This is actually a bug in the current code, even for single panel configurations, if someone has chosen to use the 2nd pps/backlight. BR, Jani. > >> >> intel_bios_init_panel() should probably also return a value on pnpid indicating >> intel_edp_init_connector() should call >> intel_bios_init_panel() again, this time with EDID. (Note: I kind of like separating >> returning the value and setting the pps id to -1. I don't want >> intel_edp_init_connector() to look at pps id, that's for pps, and I don't want to >> pass flags all the way to bxt_power_sequencer_idx() >> either.) > > For PANEL_TYPE_PNPID am returning boolean retry, with that don’t need to move panet type enum to intel_bios.h. > If the retry is true will call intel_bios_init_panel() with edid to check for PANEL_TYPE_PNPID. > > Regards, > Animesh > >> >> >> BR, >> Jani. >> >> >> > >> > Regards, >> > Animesh >> > >> >> > + >> >> > intel_pps_init(intel_dp); >> >> > >> >> > /* Cache DPCD and EDID for edp. */ @@ -5255,9 +5258,9 @@ static >> >> > bool intel_edp_init_connector(struct intel_dp >> >> *intel_dp, >> >> > edid = ERR_PTR(-ENOENT); >> >> > } >> >> > intel_connector->edid = edid; >> >> > - >> >> > - intel_bios_init_panel(dev_priv, &intel_connector->panel, >> >> > - encoder->devdata, IS_ERR(edid) ? NULL : edid); >> >> > + if (intel_connector->panel.vbt.panel_type == PANEL_TYPE_FALLBACK) >> >> > + intel_bios_init_panel(dev_priv, &intel_connector->panel, >> >> > + encoder->devdata, IS_ERR(edid) ? NULL : >> >> edid); >> >> > >> >> > intel_panel_add_edid_fixed_modes(intel_connector, >> >> > >> >> > intel_connector->panel.vbt.drrs_type >> >> != DRRS_TYPE_NONE, diff >> >> > --git a/drivers/gpu/drm/i915/display/intel_pps.c >> >> > b/drivers/gpu/drm/i915/display/intel_pps.c >> >> > index b972fa6ec00d..4b8413382c5d 100644 >> >> > --- a/drivers/gpu/drm/i915/display/intel_pps.c >> >> > +++ b/drivers/gpu/drm/i915/display/intel_pps.c >> >> > @@ -1430,7 +1430,7 @@ void intel_pps_init(struct intel_dp *intel_dp) >> >> > intel_dp->pps.initializing = true; >> >> > INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, >> >> > edp_panel_vdd_work); >> >> > >> >> > - if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) >> >> > + if (IS_GEMINILAKE(i915) || IS_BROXTON(i915) || >> >> > +DISPLAY_VER(i915) >= >> >> > +12) >> >> > intel_dp->get_pps_idx = bxt_power_sequencer_idx; >> >> > else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) >> >> > intel_dp->get_pps_idx = vlv_power_sequencer_pipe; >> >> > -- >> >> > 2.29.0 >> >> >> >> -- >> >> Ville Syrjälä >> >> Intel >> >> -- >> Jani Nikula, Intel Open Source Graphics Center -- Jani Nikula, Intel Open Source Graphics Center ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario 2022-09-26 10:35 ` Jani Nikula @ 2022-09-27 17:53 ` Manna, Animesh 0 siblings, 0 replies; 17+ messages in thread From: Manna, Animesh @ 2022-09-27 17:53 UTC (permalink / raw) To: Nikula, Jani, Ville Syrjälä; +Cc: intel-gfx > -----Original Message----- > From: Nikula, Jani <jani.nikula@intel.com> > Sent: Monday, September 26, 2022 4:06 PM > To: Manna, Animesh <animesh.manna@intel.com>; Ville Syrjälä > <ville.syrjala@linux.intel.com> > Cc: intel-gfx@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com> > Subject: RE: [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario > > On Tue, 20 Sep 2022, "Manna, Animesh" <animesh.manna@intel.com> wrote: > >> -----Original Message----- > >> From: Nikula, Jani <jani.nikula@intel.com> > >> Sent: Friday, September 16, 2022 5:00 PM > >> To: Manna, Animesh <animesh.manna@intel.com>; Ville Syrjälä > >> <ville.syrjala@linux.intel.com> > >> Cc: intel-gfx@lists.freedesktop.org; Shankar, Uma > >> <uma.shankar@intel.com> > >> Subject: RE: [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP > >> scenario > >> > >> On Fri, 16 Sep 2022, "Manna, Animesh" <animesh.manna@intel.com> wrote: > >> >> -----Original Message----- > >> >> From: Ville Syrjälä <ville.syrjala@linux.intel.com> > >> >> Sent: Friday, September 16, 2022 2:28 PM > >> >> To: Manna, Animesh <animesh.manna@intel.com> > >> >> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani > >> >> <jani.nikula@intel.com>; Shankar, Uma <uma.shankar@intel.com> > >> >> Subject: Re: [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP > >> >> scenario > >> >> > >> >> On Fri, Sep 16, 2022 at 02:01:02PM +0530, Animesh Manna wrote: > >> >> > >From display gen12 onwards to support dual EDP two instances of > >> >> > >pps > >> added. > >> >> > Currently backlight controller and pps instance can be mapped > >> >> > together for a specific panel. Extended support for gen12 for > >> >> > dual EDP > >> usage. > >> >> > > >> >> > v1: Iniital revision > >> >> > v2: Called intel_bios_panel_init w/o PNPID before intel_pps_init. > >> >> > [Jani] > >> >> > > >> >> > Cc: Jani Nikula <jani.nikula@intel.com> > >> >> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > >> >> > Cc: Uma Shankar <uma.shankar@intel.com> > >> >> > Signed-off-by: Animesh Manna <animesh.manna@intel.com> > >> >> > --- > >> >> > drivers/gpu/drm/i915/display/intel_bios.c | 7 ------- > >> >> > drivers/gpu/drm/i915/display/intel_bios.h | 7 +++++++ > >> >> > drivers/gpu/drm/i915/display/intel_dp.c | 9 ++++++--- > >> >> > drivers/gpu/drm/i915/display/intel_pps.c | 2 +- > >> >> > 4 files changed, 14 insertions(+), 11 deletions(-) > >> >> > > >> >> > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c > >> >> > b/drivers/gpu/drm/i915/display/intel_bios.c > >> >> > index 28bdb936cd1f..5fd4c09dfa96 100644 > >> >> > --- a/drivers/gpu/drm/i915/display/intel_bios.c > >> >> > +++ b/drivers/gpu/drm/i915/display/intel_bios.c > >> >> > @@ -706,13 +706,6 @@ static int fallback_get_panel_type(struct > >> >> drm_i915_private *i915, > >> >> > return 0; > >> >> > } > >> >> > > >> >> > -enum panel_type { > >> >> > - PANEL_TYPE_OPREGION, > >> >> > - PANEL_TYPE_VBT, > >> >> > - PANEL_TYPE_PNPID, > >> >> > - PANEL_TYPE_FALLBACK, > >> >> > -}; > >> >> > - > >> >> > static int get_panel_type(struct drm_i915_private *i915, > >> >> > const struct intel_bios_encoder_data *devdata, > >> >> > const struct edid *edid) diff --git > >> >> > a/drivers/gpu/drm/i915/display/intel_bios.h > >> >> > b/drivers/gpu/drm/i915/display/intel_bios.h > >> >> > index e375405a7828..da01b13260ae 100644 > >> >> > --- a/drivers/gpu/drm/i915/display/intel_bios.h > >> >> > +++ b/drivers/gpu/drm/i915/display/intel_bios.h > >> >> > @@ -231,6 +231,13 @@ struct mipi_pps_data { > >> >> > u16 panel_power_cycle_delay; } __packed; > >> >> > > >> >> > +enum panel_type { > >> >> > + PANEL_TYPE_OPREGION, > >> >> > + PANEL_TYPE_VBT, > >> >> > + PANEL_TYPE_PNPID, > >> >> > + PANEL_TYPE_FALLBACK, > >> >> > +}; > >> >> > + > >> > >> I don't want enum panel_type exposed from intel_bios.c at all, > >> there's no reason for that. > > > > Hi Jani, > > > > Thanks for your inputs. I have made the changes as per your suggestion. > > I have a doubt which is mentioned below, currently have sent to trybot for > quick feedback. > > https://patchwork.freedesktop.org/patch/503759/?series=108786&rev=1 > > I'm not subscribed to the trybot list, so I can't easily reply with comments. > > Use trybot only to *test* stuff, not if you want human feedback. > > > > >> > >> >> > void intel_bios_init(struct drm_i915_private *dev_priv); void > >> >> > intel_bios_init_panel(struct drm_i915_private *dev_priv, > >> >> > struct intel_panel *panel, diff --git > >> >> > a/drivers/gpu/drm/i915/display/intel_dp.c > >> >> > b/drivers/gpu/drm/i915/display/intel_dp.c > >> >> > index c19e99ee06b6..6f7afa75ec4d 100644 > >> >> > --- a/drivers/gpu/drm/i915/display/intel_dp.c > >> >> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > >> >> > @@ -5222,6 +5222,9 @@ static bool > >> >> > intel_edp_init_connector(struct intel_dp > >> >> *intel_dp, > >> >> > return false; > >> >> > } > >> >> > > >> >> > + intel_bios_init_panel(dev_priv, &intel_connector->panel, > >> >> > + encoder->devdata, NULL); > >> >> > >> >> We don't want to go for the fallback type here if we the VBT wants > >> >> us to use pnpid. Maybe we should just remove the fallback type entirely? > >> >> Or perhaps only use it if the VBT panel type is entirely invalid? > >> > > >> > Ok, Can I add like below? > >> > If (!PANEL_TYPE_FALLBACK) > >> > intel_pps_init(intel_dp); > >> > > >> > But to read EDID pps_init should be called before it. Or else I can > >> > enable both > >> the pps and later disable the unused one. > >> > >> The first call should init everything if it can (panel type is *not* > >> pnpid). Fallback is fine in that case too. > > > > First time intel_bios_init_panel() will be called with null edid and panel type will > be set to PANEL_TYPE_FALLBACK. > > > >> > >> If panel type indicates pnpid, intel_bios_init_panel() should set the > >> pps id to, say, -1, so intel_pps_init() or more specifically > >> bxt_power_sequencer_idx() can use some default or look at the > >> hardware or whatever. > > > > Currently checking for PANEL_TYPE_PNPID in intel_bios_init_panel() and > setting pps id to -1. > > But I am not sure why special handling is needed in > bxt_power_sequencer_idx(). > > Is backlight_controller value can be used to derive pps instance for > PANEL_TYPE_PNPID. > > Backlight controller and pps index are basically the *same* thing. If PNPID is > used, the backlight controller is uninitialized. > > This is actually a bug in the current code, even for single panel configurations, if > someone has chosen to use the 2nd pps/backlight. I have sent the next version for review. https://patchwork.freedesktop.org/series/109135/ Can you please have a look. Regards, Animesh > > BR, > Jani. > > > > >> > >> intel_bios_init_panel() should probably also return a value on pnpid > >> indicating > >> intel_edp_init_connector() should call > >> intel_bios_init_panel() again, this time with EDID. (Note: I kind of > >> like separating returning the value and setting the pps id to -1. I > >> don't want > >> intel_edp_init_connector() to look at pps id, that's for pps, and I > >> don't want to pass flags all the way to bxt_power_sequencer_idx() > >> either.) > > > > For PANEL_TYPE_PNPID am returning boolean retry, with that don’t need to > move panet type enum to intel_bios.h. > > If the retry is true will call intel_bios_init_panel() with edid to check for > PANEL_TYPE_PNPID. > > > > Regards, > > Animesh > > > >> > >> > >> BR, > >> Jani. > >> > >> > >> > > >> > Regards, > >> > Animesh > >> > > >> >> > + > >> >> > intel_pps_init(intel_dp); > >> >> > > >> >> > /* Cache DPCD and EDID for edp. */ @@ -5255,9 +5258,9 @@ > >> >> > static bool intel_edp_init_connector(struct intel_dp > >> >> *intel_dp, > >> >> > edid = ERR_PTR(-ENOENT); > >> >> > } > >> >> > intel_connector->edid = edid; > >> >> > - > >> >> > - intel_bios_init_panel(dev_priv, &intel_connector->panel, > >> >> > - encoder->devdata, IS_ERR(edid) ? NULL : edid); > >> >> > + if (intel_connector->panel.vbt.panel_type == PANEL_TYPE_FALLBACK) > >> >> > + intel_bios_init_panel(dev_priv, &intel_connector->panel, > >> >> > + encoder->devdata, IS_ERR(edid) ? NULL : > >> >> edid); > >> >> > > >> >> > intel_panel_add_edid_fixed_modes(intel_connector, > >> >> > > >> >> > intel_connector->panel.vbt.drrs_type > >> >> != DRRS_TYPE_NONE, diff > >> >> > --git a/drivers/gpu/drm/i915/display/intel_pps.c > >> >> > b/drivers/gpu/drm/i915/display/intel_pps.c > >> >> > index b972fa6ec00d..4b8413382c5d 100644 > >> >> > --- a/drivers/gpu/drm/i915/display/intel_pps.c > >> >> > +++ b/drivers/gpu/drm/i915/display/intel_pps.c > >> >> > @@ -1430,7 +1430,7 @@ void intel_pps_init(struct intel_dp *intel_dp) > >> >> > intel_dp->pps.initializing = true; > >> >> > INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, > >> >> > edp_panel_vdd_work); > >> >> > > >> >> > - if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) > >> >> > + if (IS_GEMINILAKE(i915) || IS_BROXTON(i915) || > >> >> > +DISPLAY_VER(i915) >= > >> >> > +12) > >> >> > intel_dp->get_pps_idx = bxt_power_sequencer_idx; > >> >> > else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) > >> >> > intel_dp->get_pps_idx = vlv_power_sequencer_pipe; > >> >> > -- > >> >> > 2.29.0 > >> >> > >> >> -- > >> >> Ville Syrjälä > >> >> Intel > >> > >> -- > >> Jani Nikula, Intel Open Source Graphics Center > > -- > Jani Nikula, Intel Open Source Graphics Center ^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup 2022-09-16 8:31 [Intel-gfx] [PATCH 1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup Animesh Manna 2022-09-16 8:31 ` [Intel-gfx] [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario Animesh Manna @ 2022-09-16 10:16 ` Patchwork 2022-09-16 14:29 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 2 siblings, 0 replies; 17+ messages in thread From: Patchwork @ 2022-09-16 10:16 UTC (permalink / raw) To: Animesh Manna; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 11844 bytes --] == Series Details == Series: series starting with [1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup URL : https://patchwork.freedesktop.org/series/108643/ State : success == Summary == CI Bug Log - changes from CI_DRM_12145 -> Patchwork_108643v1 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/index.html Participating hosts (44 -> 41) ------------------------------ Additional (2): fi-apl-guc bat-dg1-5 Missing (5): fi-hsw-4200u fi-icl-u2 fi-ctg-p8600 bat-dg2-11 fi-bdw-samus Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_108643v1: ### IGT changes ### #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt@i915_pm_rpm@module-reload: - {fi-tgl-mst}: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12145/fi-tgl-mst/igt@i915_pm_rpm@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/fi-tgl-mst/igt@i915_pm_rpm@module-reload.html Known issues ------------ Here are the changes found in Patchwork_108643v1 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@fbdev@nullptr: - bat-dg1-5: NOTRUN -> [SKIP][3] ([i915#2582]) +4 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/bat-dg1-5/igt@fbdev@nullptr.html * igt@gem_mmap@basic: - bat-dg1-5: NOTRUN -> [SKIP][4] ([i915#4083]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/bat-dg1-5/igt@gem_mmap@basic.html * igt@gem_tiled_blits@basic: - bat-dg1-5: NOTRUN -> [SKIP][5] ([i915#4077]) +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/bat-dg1-5/igt@gem_tiled_blits@basic.html * igt@gem_tiled_pread_basic: - bat-dg1-5: NOTRUN -> [SKIP][6] ([i915#4079]) +1 similar issue [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/bat-dg1-5/igt@gem_tiled_pread_basic.html * igt@i915_pm_backlight@basic-brightness: - bat-dg1-5: NOTRUN -> [SKIP][7] ([i915#1155]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/bat-dg1-5/igt@i915_pm_backlight@basic-brightness.html * igt@i915_pm_rps@basic-api: - bat-dg1-5: NOTRUN -> [SKIP][8] ([i915#6621]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/bat-dg1-5/igt@i915_pm_rps@basic-api.html * igt@i915_selftest@live@gt_engines: - bat-dg1-5: NOTRUN -> [INCOMPLETE][9] ([i915#4418]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/bat-dg1-5/igt@i915_selftest@live@gt_engines.html * igt@i915_selftest@live@requests: - fi-pnv-d510: [PASS][10] -> [DMESG-FAIL][11] ([i915#4528]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12145/fi-pnv-d510/igt@i915_selftest@live@requests.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/fi-pnv-d510/igt@i915_selftest@live@requests.html * igt@kms_addfb_basic@basic-x-tiled-legacy: - bat-dg1-5: NOTRUN -> [SKIP][12] ([i915#4212]) +7 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/bat-dg1-5/igt@kms_addfb_basic@basic-x-tiled-legacy.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-dg1-5: NOTRUN -> [SKIP][13] ([i915#4215]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/bat-dg1-5/igt@kms_addfb_basic@basic-y-tiled-legacy.html * igt@kms_busy@basic: - bat-dg1-5: NOTRUN -> [SKIP][14] ([i915#1845] / [i915#4303]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/bat-dg1-5/igt@kms_busy@basic.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-bsw-nick: NOTRUN -> [SKIP][15] ([fdo#109271] / [fdo#111827]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/fi-bsw-nick/igt@kms_chamelium@common-hpd-after-suspend.html * igt@kms_chamelium@dp-crc-fast: - bat-dg1-5: NOTRUN -> [SKIP][16] ([fdo#111827]) +7 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/bat-dg1-5/igt@kms_chamelium@dp-crc-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size: - fi-bsw-kefka: [PASS][17] -> [FAIL][18] ([i915#6298]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12145/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size.html * igt@kms_force_connector_basic@force-load-detect: - bat-dg1-5: NOTRUN -> [SKIP][19] ([fdo#109285]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/bat-dg1-5/igt@kms_force_connector_basic@force-load-detect.html * igt@kms_pipe_crc_basic@nonblocking-crc: - bat-dg1-5: NOTRUN -> [SKIP][20] ([i915#4078]) +13 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/bat-dg1-5/igt@kms_pipe_crc_basic@nonblocking-crc.html * igt@kms_pipe_crc_basic@suspend-read-crc: - fi-bsw-nick: NOTRUN -> [SKIP][21] ([fdo#109271]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/fi-bsw-nick/igt@kms_pipe_crc_basic@suspend-read-crc.html * igt@kms_psr@primary_page_flip: - bat-dg1-5: NOTRUN -> [SKIP][22] ([i915#1072] / [i915#4078]) +3 similar issues [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/bat-dg1-5/igt@kms_psr@primary_page_flip.html * igt@kms_setmode@basic-clone-single-crtc: - bat-dg1-5: NOTRUN -> [SKIP][23] ([i915#3555]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/bat-dg1-5/igt@kms_setmode@basic-clone-single-crtc.html * igt@prime_vgem@basic-fence-flip: - bat-dg1-5: NOTRUN -> [SKIP][24] ([i915#1845] / [i915#3708]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/bat-dg1-5/igt@prime_vgem@basic-fence-flip.html * igt@prime_vgem@basic-fence-read: - bat-dg1-5: NOTRUN -> [SKIP][25] ([i915#3708]) +2 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/bat-dg1-5/igt@prime_vgem@basic-fence-read.html * igt@prime_vgem@basic-gtt: - bat-dg1-5: NOTRUN -> [SKIP][26] ([i915#3708] / [i915#4077]) +1 similar issue [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/bat-dg1-5/igt@prime_vgem@basic-gtt.html * igt@prime_vgem@basic-userptr: - bat-dg1-5: NOTRUN -> [SKIP][27] ([i915#3708] / [i915#4873]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/bat-dg1-5/igt@prime_vgem@basic-userptr.html * igt@runner@aborted: - bat-dg1-5: NOTRUN -> [FAIL][28] ([i915#4312] / [i915#5257]) [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/bat-dg1-5/igt@runner@aborted.html - fi-pnv-d510: NOTRUN -> [FAIL][29] ([fdo#109271] / [i915#2403] / [i915#4312]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/fi-pnv-d510/igt@runner@aborted.html - fi-apl-guc: NOTRUN -> [FAIL][30] ([i915#6599]) [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/fi-apl-guc/igt@runner@aborted.html #### Possible fixes #### * igt@i915_module_load@reload: - {fi-tgl-mst}: [WARN][31] ([i915#6596]) -> [PASS][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12145/fi-tgl-mst/igt@i915_module_load@reload.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/fi-tgl-mst/igt@i915_module_load@reload.html * igt@i915_selftest@live@hugepages: - {bat-rpls-1}: [DMESG-WARN][33] ([i915#5278]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12145/bat-rpls-1/igt@i915_selftest@live@hugepages.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/bat-rpls-1/igt@i915_selftest@live@hugepages.html * igt@i915_selftest@live@late_gt_pm: - fi-bsw-nick: [DMESG-FAIL][35] ([i915#3428] / [i915#6217]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12145/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html * igt@i915_selftest@live@slpc: - {bat-rpls-1}: [DMESG-FAIL][37] ([i915#6367]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12145/bat-rpls-1/igt@i915_selftest@live@slpc.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/bat-rpls-1/igt@i915_selftest@live@slpc.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155 [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845 [i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403 [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582 [i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428 [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708 [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077 [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078 [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079 [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083 [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212 [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215 [i915#4303]: https://gitlab.freedesktop.org/drm/intel/issues/4303 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#4418]: https://gitlab.freedesktop.org/drm/intel/issues/4418 [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528 [i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873 [i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257 [i915#5278]: https://gitlab.freedesktop.org/drm/intel/issues/5278 [i915#6217]: https://gitlab.freedesktop.org/drm/intel/issues/6217 [i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298 [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367 [i915#6596]: https://gitlab.freedesktop.org/drm/intel/issues/6596 [i915#6599]: https://gitlab.freedesktop.org/drm/intel/issues/6599 [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621 Build changes ------------- * Linux: CI_DRM_12145 -> Patchwork_108643v1 CI-20190529: 20190529 CI_DRM_12145: 2dc9ea03abff1bfc8c8ebe0f7ef056edf77cc29e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6656: 24100c4e181c50e3678aeca9c641b8a43555ad73 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_108643v1: 2dc9ea03abff1bfc8c8ebe0f7ef056edf77cc29e @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits a6b5b569346d drm/i915/pps: Enable 2nd pps for dual EDP scenario 2f8ff59b8963 drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/index.html [-- Attachment #2: Type: text/html, Size: 13889 bytes --] ^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup 2022-09-16 8:31 [Intel-gfx] [PATCH 1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup Animesh Manna 2022-09-16 8:31 ` [Intel-gfx] [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario Animesh Manna 2022-09-16 10:16 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup Patchwork @ 2022-09-16 14:29 ` Patchwork 2 siblings, 0 replies; 17+ messages in thread From: Patchwork @ 2022-09-16 14:29 UTC (permalink / raw) To: Manna, Animesh; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 28981 bytes --] == Series Details == Series: series starting with [1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup URL : https://patchwork.freedesktop.org/series/108643/ State : success == Summary == CI Bug Log - changes from CI_DRM_12145_full -> Patchwork_108643v1_full ==================================================== Summary ------- **SUCCESS** No regressions found. Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Known issues ------------ Here are the changes found in Patchwork_108643v1_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_ctx_exec@basic-nohangcheck: - shard-tglb: [PASS][1] -> [FAIL][2] ([i915#6268]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12145/shard-tglb3/igt@gem_ctx_exec@basic-nohangcheck.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-tglb2/igt@gem_ctx_exec@basic-nohangcheck.html * igt@gem_exec_endless@dispatch@vecs0: - shard-tglb: [PASS][3] -> [INCOMPLETE][4] ([i915#3778]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12145/shard-tglb3/igt@gem_exec_endless@dispatch@vecs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-tglb2/igt@gem_exec_endless@dispatch@vecs0.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-tglb: [PASS][5] -> [FAIL][6] ([i915#2842]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12145/shard-tglb2/igt@gem_exec_fair@basic-flow@rcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-tglb6/igt@gem_exec_fair@basic-flow@rcs0.html * igt@gem_exec_fair@basic-none@vcs0: - shard-glk: [PASS][7] -> [FAIL][8] ([i915#2842]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12145/shard-glk5/igt@gem_exec_fair@basic-none@vcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-glk8/igt@gem_exec_fair@basic-none@vcs0.html * igt@gem_lmem_swapping@parallel-random-engines: - shard-apl: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4613]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-apl3/igt@gem_lmem_swapping@parallel-random-engines.html * igt@gem_pwrite@basic-exhaustion: - shard-iclb: NOTRUN -> [WARN][10] ([i915#2658]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-iclb6/igt@gem_pwrite@basic-exhaustion.html * igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-mc-ccs: - shard-iclb: NOTRUN -> [SKIP][11] ([i915#768]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-iclb6/igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-mc-ccs.html * igt@gen9_exec_parse@allowed-single: - shard-apl: [PASS][12] -> [DMESG-WARN][13] ([i915#5566] / [i915#716]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12145/shard-apl2/igt@gen9_exec_parse@allowed-single.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-apl6/igt@gen9_exec_parse@allowed-single.html * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip: - shard-iclb: NOTRUN -> [SKIP][14] ([i915#5286]) +1 similar issue [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-iclb6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html * igt@kms_big_fb@x-tiled-16bpp-rotate-270: - shard-iclb: NOTRUN -> [SKIP][15] ([fdo#110725] / [fdo#111614]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-iclb6/igt@kms_big_fb@x-tiled-16bpp-rotate-270.html * igt@kms_big_fb@yf-tiled-64bpp-rotate-180: - shard-iclb: NOTRUN -> [SKIP][16] ([fdo#110723]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-iclb6/igt@kms_big_fb@yf-tiled-64bpp-rotate-180.html * igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc: - shard-apl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#3886]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-apl3/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs: - shard-iclb: NOTRUN -> [SKIP][18] ([fdo#109278] / [i915#3886]) +1 similar issue [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-iclb6/igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_gen12_mc_ccs: - shard-iclb: NOTRUN -> [SKIP][19] ([fdo#109278]) +6 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-iclb6/igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_gen12_mc_ccs.html * igt@kms_chamelium@hdmi-audio-edid: - shard-apl: NOTRUN -> [SKIP][20] ([fdo#109271] / [fdo#111827]) +1 similar issue [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-apl1/igt@kms_chamelium@hdmi-audio-edid.html * igt@kms_chamelium@vga-hpd-for-each-pipe: - shard-iclb: NOTRUN -> [SKIP][21] ([fdo#109284] / [fdo#111827]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-iclb6/igt@kms_chamelium@vga-hpd-for-each-pipe.html * igt@kms_content_protection@uevent: - shard-iclb: NOTRUN -> [SKIP][22] ([fdo#109300] / [fdo#111066]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-iclb6/igt@kms_content_protection@uevent.html * igt@kms_cursor_crc@cursor-sliding-max-size: - shard-iclb: NOTRUN -> [SKIP][23] ([i915#3555]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-iclb6/igt@kms_cursor_crc@cursor-sliding-max-size.html * igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions: - shard-glk: [PASS][24] -> [FAIL][25] ([i915#2346]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12145/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html * igt@kms_flip@2x-absolute-wf_vblank: - shard-iclb: NOTRUN -> [SKIP][26] ([fdo#109274]) [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-iclb6/igt@kms_flip@2x-absolute-wf_vblank.html * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-default-mode: - shard-iclb: NOTRUN -> [SKIP][27] ([i915#2672]) +3 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-default-mode.html * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling@pipe-a-valid-mode: - shard-iclb: NOTRUN -> [SKIP][28] ([i915#2587] / [i915#2672]) +2 similar issues [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-iclb6/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling@pipe-a-valid-mode.html * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling@pipe-a-default-mode: - shard-iclb: NOTRUN -> [SKIP][29] ([i915#2672] / [i915#3555]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling@pipe-a-default-mode.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-pgflip-blt: - shard-iclb: NOTRUN -> [SKIP][30] ([fdo#109280]) +6 similar issues [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-pgflip-blt.html * igt@kms_plane_alpha_blend@pipe-d-alpha-7efc: - shard-apl: NOTRUN -> [SKIP][31] ([fdo#109271]) +46 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-apl3/igt@kms_plane_alpha_blend@pipe-d-alpha-7efc.html * igt@kms_plane_lowres@tiling-x@pipe-b-edp-1: - shard-iclb: NOTRUN -> [SKIP][32] ([i915#3536]) +2 similar issues [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-iclb6/igt@kms_plane_lowres@tiling-x@pipe-b-edp-1.html * igt@kms_plane_lowres@tiling-y@pipe-b-hdmi-a-2: - shard-glk: [PASS][33] -> [FAIL][34] ([i915#1888]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12145/shard-glk7/igt@kms_plane_lowres@tiling-y@pipe-b-hdmi-a-2.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-glk9/igt@kms_plane_lowres@tiling-y@pipe-b-hdmi-a-2.html * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-c-hdmi-a-1: - shard-glk: NOTRUN -> [SKIP][35] ([fdo#109271]) +3 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-glk6/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-c-hdmi-a-1.html * igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf: - shard-apl: NOTRUN -> [SKIP][36] ([fdo#109271] / [i915#658]) [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-apl1/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf.html * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area: - shard-iclb: NOTRUN -> [SKIP][37] ([fdo#111068] / [i915#658]) +1 similar issue [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-iclb6/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html * igt@kms_psr2_su@frontbuffer-xrgb8888: - shard-iclb: [PASS][38] -> [SKIP][39] ([fdo#109642] / [fdo#111068] / [i915#658]) [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12145/shard-iclb2/igt@kms_psr2_su@frontbuffer-xrgb8888.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-iclb4/igt@kms_psr2_su@frontbuffer-xrgb8888.html * igt@kms_psr@psr2_sprite_render: - shard-iclb: [PASS][40] -> [SKIP][41] ([fdo#109441]) [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12145/shard-iclb2/igt@kms_psr@psr2_sprite_render.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-iclb4/igt@kms_psr@psr2_sprite_render.html * igt@kms_writeback@writeback-fb-id: - shard-iclb: NOTRUN -> [SKIP][42] ([i915#2437]) [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-iclb6/igt@kms_writeback@writeback-fb-id.html * igt@nouveau_crc@pipe-d-ctx-flip-skip-current-frame: - shard-iclb: NOTRUN -> [SKIP][43] ([fdo#109278] / [i915#2530]) [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-iclb6/igt@nouveau_crc@pipe-d-ctx-flip-skip-current-frame.html * igt@perf@polling-parameterized: - shard-tglb: [PASS][44] -> [FAIL][45] ([i915#5639]) [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12145/shard-tglb1/igt@perf@polling-parameterized.html [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-tglb7/igt@perf@polling-parameterized.html - shard-glk: [PASS][46] -> [FAIL][47] ([i915#5639]) [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12145/shard-glk6/igt@perf@polling-parameterized.html [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-glk3/igt@perf@polling-parameterized.html * igt@prime_nv_api@nv_i915_reimport_twice_check_flink_name: - shard-iclb: NOTRUN -> [SKIP][48] ([fdo#109291]) [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-iclb6/igt@prime_nv_api@nv_i915_reimport_twice_check_flink_name.html * igt@prime_vgem@fence-flip-hang: - shard-iclb: NOTRUN -> [SKIP][49] ([fdo#109295]) [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-iclb6/igt@prime_vgem@fence-flip-hang.html * igt@sysfs_clients@split-50: - shard-iclb: NOTRUN -> [SKIP][50] ([i915#2994]) [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-iclb6/igt@sysfs_clients@split-50.html #### Possible fixes #### * igt@gem_exec_fair@basic-deadline: - shard-glk: [FAIL][51] ([i915#2846]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12145/shard-glk8/igt@gem_exec_fair@basic-deadline.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-glk1/igt@gem_exec_fair@basic-deadline.html * igt@gem_exec_fair@basic-none-share@rcs0: - {shard-tglu}: [FAIL][53] ([i915#2842]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12145/shard-tglu-2/igt@gem_exec_fair@basic-none-share@rcs0.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-tglu-4/igt@gem_exec_fair@basic-none-share@rcs0.html - shard-tglb: [FAIL][55] ([i915#2842]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12145/shard-tglb8/igt@gem_exec_fair@basic-none-share@rcs0.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-tglb6/igt@gem_exec_fair@basic-none-share@rcs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [FAIL][57] ([i915#2842]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12145/shard-glk6/igt@gem_exec_fair@basic-pace-share@rcs0.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-glk6/igt@gem_exec_fair@basic-pace-share@rcs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-iclb: [FAIL][59] ([i915#2842]) -> [PASS][60] +1 similar issue [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12145/shard-iclb3/igt@gem_exec_fair@basic-throttle@rcs0.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-iclb3/igt@gem_exec_fair@basic-throttle@rcs0.html * igt@gem_exec_reloc@basic-cpu-gtt-active: - {shard-rkl}: [SKIP][61] ([i915#3281]) -> [PASS][62] +1 similar issue [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12145/shard-rkl-6/igt@gem_exec_reloc@basic-cpu-gtt-active.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-rkl-5/igt@gem_exec_reloc@basic-cpu-gtt-active.html * igt@gem_exec_suspend@basic-s3@smem: - shard-apl: [DMESG-WARN][63] ([i915#180]) -> [PASS][64] +2 similar issues [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12145/shard-apl2/igt@gem_exec_suspend@basic-s3@smem.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-apl1/igt@gem_exec_suspend@basic-s3@smem.html * igt@gen9_exec_parse@allowed-single: - shard-glk: [DMESG-WARN][65] ([i915#5566] / [i915#716]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12145/shard-glk6/igt@gen9_exec_parse@allowed-single.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-glk6/igt@gen9_exec_parse@allowed-single.html * igt@gen9_exec_parse@cmd-crossing-page: - {shard-rkl}: [SKIP][67] ([i915#2527]) -> [PASS][68] [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12145/shard-rkl-6/igt@gen9_exec_parse@cmd-crossing-page.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-rkl-5/igt@gen9_exec_parse@cmd-crossing-page.html * igt@i915_pm_dc@dc5-psr: - shard-tglb: [FAIL][69] ([i915#3989]) -> [PASS][70] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12145/shard-tglb6/igt@i915_pm_dc@dc5-psr.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-tglb5/igt@i915_pm_dc@dc5-psr.html * igt@kms_cursor_crc@cursor-onscreen-256x85@pipe-a-hdmi-a-1: - {shard-tglu}: [FAIL][71] ([i915#1888]) -> [PASS][72] [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12145/shard-tglu-1/igt@kms_cursor_crc@cursor-onscreen-256x85@pipe-a-hdmi-a-1.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-tglu-3/igt@kms_cursor_crc@cursor-onscreen-256x85@pipe-a-hdmi-a-1.html * igt@kms_plane_lowres@tiling-y@pipe-a-hdmi-a-2: - shard-glk: [DMESG-FAIL][73] ([i915#118] / [i915#1888]) -> [PASS][74] [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12145/shard-glk7/igt@kms_plane_lowres@tiling-y@pipe-a-hdmi-a-2.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-glk9/igt@kms_plane_lowres@tiling-y@pipe-a-hdmi-a-2.html * igt@kms_plane_lowres@tiling-y@pipe-c-hdmi-a-1: - shard-glk: [FAIL][75] ([i915#1888]) -> [PASS][76] [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12145/shard-glk7/igt@kms_plane_lowres@tiling-y@pipe-c-hdmi-a-1.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-glk9/igt@kms_plane_lowres@tiling-y@pipe-c-hdmi-a-1.html * igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1: - shard-iclb: [SKIP][77] ([i915#5235]) -> [PASS][78] +2 similar issues [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12145/shard-iclb2/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-iclb1/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1.html * igt@kms_psr@psr2_sprite_plane_onoff: - shard-iclb: [SKIP][79] ([fdo#109441]) -> [PASS][80] +2 similar issues [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12145/shard-iclb4/igt@kms_psr@psr2_sprite_plane_onoff.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-iclb2/igt@kms_psr@psr2_sprite_plane_onoff.html * igt@kms_psr_stress_test@invalidate-primary-flip-overlay: - shard-iclb: [SKIP][81] ([i915#5519]) -> [PASS][82] [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12145/shard-iclb7/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-iclb6/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html #### Warnings #### * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb: - shard-iclb: [SKIP][83] ([i915#658]) -> [SKIP][84] ([i915#2920]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12145/shard-iclb4/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html * igt@kms_psr2_su@page_flip-nv12: - shard-iclb: [FAIL][85] ([i915#5939]) -> [SKIP][86] ([fdo#109642] / [fdo#111068] / [i915#658]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12145/shard-iclb2/igt@kms_psr2_su@page_flip-nv12.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-iclb1/igt@kms_psr2_su@page_flip-nv12.html * igt@runner@aborted: - shard-apl: ([FAIL][87], [FAIL][88], [FAIL][89], [FAIL][90], [FAIL][91]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257] / [i915#6599]) -> ([FAIL][92], [FAIL][93], [FAIL][94]) ([fdo#109271] / [i915#3002] / [i915#4312] / [i915#5257] / [i915#6599]) [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12145/shard-apl3/igt@runner@aborted.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12145/shard-apl2/igt@runner@aborted.html [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12145/shard-apl8/igt@runner@aborted.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12145/shard-apl2/igt@runner@aborted.html [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12145/shard-apl2/igt@runner@aborted.html [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-apl2/igt@runner@aborted.html [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-apl7/igt@runner@aborted.html [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/shard-apl6/igt@runner@aborted.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280 [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284 [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291 [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295 [fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300 [fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302 [fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303 [fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307 [fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189 [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723 [fdo#110725]: https://bugs.freedesktop.org/show_bug.cgi?id=110725 [fdo#111066]: https://bugs.freedesktop.org/show_bug.cgi?id=111066 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614 [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615 [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132 [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397 [i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825 [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839 [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845 [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1911]: https://gitlab.freedesktop.org/drm/intel/issues/1911 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346 [i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433 [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437 [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527 [i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530 [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582 [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587 [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658 [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672 [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705 [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280 [i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284 [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842 [i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846 [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920 [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994 [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002 [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012 [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281 [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282 [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291 [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297 [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301 [i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323 [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359 [i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361 [i915#3376]: https://gitlab.freedesktop.org/drm/intel/issues/3376 [i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536 [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546 [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 [i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558 [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637 [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638 [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689 [i915#3692]: https://gitlab.freedesktop.org/drm/intel/issues/3692 [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708 [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734 [i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742 [i915#3778]: https://gitlab.freedesktop.org/drm/intel/issues/3778 [i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826 [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886 [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955 [i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989 [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070 [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098 [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103 [i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426 [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991 [i915#5030]: https://gitlab.freedesktop.org/drm/intel/issues/5030 [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176 [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235 [i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257 [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286 [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289 [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325 [i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327 [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439 [i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519 [i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566 [i915#5639]: https://gitlab.freedesktop.org/drm/intel/issues/5639 [i915#5939]: https://gitlab.freedesktop.org/drm/intel/issues/5939 [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095 [i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230 [i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245 [i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248 [i915#6251]: https://gitlab.freedesktop.org/drm/intel/issues/6251 [i915#6252]: https://gitlab.freedesktop.org/drm/intel/issues/6252 [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268 [i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335 [i915#6344]: https://gitlab.freedesktop.org/drm/intel/issues/6344 [i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433 [i915#6474]: https://gitlab.freedesktop.org/drm/intel/issues/6474 [i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497 [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#6599]: https://gitlab.freedesktop.org/drm/intel/issues/6599 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#768]: https://gitlab.freedesktop.org/drm/intel/issues/768 Build changes ------------- * Linux: CI_DRM_12145 -> Patchwork_108643v1 CI-20190529: 20190529 CI_DRM_12145: 2dc9ea03abff1bfc8c8ebe0f7ef056edf77cc29e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6656: 24100c4e181c50e3678aeca9c641b8a43555ad73 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_108643v1: 2dc9ea03abff1bfc8c8ebe0f7ef056edf77cc29e @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108643v1/index.html [-- Attachment #2: Type: text/html, Size: 29025 bytes --] ^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] [PATCH 1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup @ 2022-09-27 17:45 Animesh Manna 2022-09-27 17:45 ` [Intel-gfx] [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario Animesh Manna 0 siblings, 1 reply; 17+ messages in thread From: Animesh Manna @ 2022-09-27 17:45 UTC (permalink / raw) To: intel-gfx; +Cc: Jani Nikula Simplified pps_get_register() which use get_pps_idx() hook to derive the pps instance and get_pps_idx() will be initialized at pps_init(). v1: Initial version. Got r-b from Jani. Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> --- .../gpu/drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_pps.c | 15 ++++++++++----- 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 0da9b208d56e..b78b29951241 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1693,6 +1693,7 @@ struct intel_dp { u8 (*preemph_max)(struct intel_dp *intel_dp); u8 (*voltage_max)(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state); + int (*get_pps_idx)(struct intel_dp *intel_dp); /* Displayport compliance testing */ struct intel_dp_compliance compliance; diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c index 21944f5bf3a8..b972fa6ec00d 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -364,12 +364,10 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp, struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); int pps_idx = 0; - memset(regs, 0, sizeof(*regs)); + if (intel_dp->get_pps_idx) + pps_idx = intel_dp->get_pps_idx(intel_dp); - if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) - pps_idx = bxt_power_sequencer_idx(intel_dp); - else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) - pps_idx = vlv_power_sequencer_pipe(intel_dp); + memset(regs, 0, sizeof(*regs)); regs->pp_ctrl = PP_CONTROL(pps_idx); regs->pp_stat = PP_STATUS(pps_idx); @@ -1432,6 +1430,13 @@ void intel_pps_init(struct intel_dp *intel_dp) intel_dp->pps.initializing = true; INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work); + if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) + intel_dp->get_pps_idx = bxt_power_sequencer_idx; + else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) + intel_dp->get_pps_idx = vlv_power_sequencer_pipe; + else + intel_dp->get_pps_idx = NULL; + pps_init_timestamps(intel_dp); with_intel_pps_lock(intel_dp, wakeref) { -- 2.29.0 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Intel-gfx] [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario 2022-09-27 17:45 [Intel-gfx] [PATCH 1/2] " Animesh Manna @ 2022-09-27 17:45 ` Animesh Manna 2022-10-04 7:48 ` Jani Nikula 0 siblings, 1 reply; 17+ messages in thread From: Animesh Manna @ 2022-09-27 17:45 UTC (permalink / raw) To: intel-gfx; +Cc: Jani Nikula From display gen12 onwards to support dual EDP two instances of pps added. Currently backlight controller and pps instance can be mapped together for a specific panel. Extended support for gen12 for dual EDP usage. v1: Iniital revision. v2: Called intel_bios_panel_init w/o PNPID before intel_pps_init. [Jani] v3: Set pps_id to -1 for pnpid type of panel which will be used by bxt_power_sequencer_idx() to set 2nd pps instance as default for 2nd EDP panel. [Jani] Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> --- drivers/gpu/drm/i915/display/intel_bios.c | 13 +++++++++++-- drivers/gpu/drm/i915/display/intel_bios.h | 2 +- drivers/gpu/drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_dp.c | 10 +++++++--- drivers/gpu/drm/i915/display/intel_pps.c | 12 +++++++++++- 5 files changed, 31 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 28bdb936cd1f..2015b6592754 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -3175,13 +3175,14 @@ void intel_bios_init(struct drm_i915_private *i915) kfree(oprom_vbt); } -void intel_bios_init_panel(struct drm_i915_private *i915, +bool intel_bios_init_panel(struct drm_i915_private *i915, struct intel_panel *panel, const struct intel_bios_encoder_data *devdata, const struct edid *edid) { - init_vbt_panel_defaults(panel); + bool retry = false; + init_vbt_panel_defaults(panel); panel->vbt.panel_type = get_panel_type(i915, devdata, edid); parse_panel_options(i915, panel); @@ -3195,6 +3196,14 @@ void intel_bios_init_panel(struct drm_i915_private *i915, parse_psr(i915, panel); parse_mipi_config(i915, panel); parse_mipi_sequence(i915, panel); + + if (panel->vbt.panel_type == PANEL_TYPE_PNPID || + panel->vbt.panel_type == PANEL_TYPE_FALLBACK) { + panel->vbt.edp.pps_id = -1; + retry = true; + } + + return retry; } /** diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h index e375405a7828..f8ef0274f3ee 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.h +++ b/drivers/gpu/drm/i915/display/intel_bios.h @@ -232,7 +232,7 @@ struct mipi_pps_data { } __packed; void intel_bios_init(struct drm_i915_private *dev_priv); -void intel_bios_init_panel(struct drm_i915_private *dev_priv, +bool intel_bios_init_panel(struct drm_i915_private *dev_priv, struct intel_panel *panel, const struct intel_bios_encoder_data *devdata, const struct edid *edid); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index b78b29951241..0edc0b8f3743 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -307,6 +307,7 @@ struct intel_vbt_panel_data { int preemphasis; int vswing; int bpp; + int pps_id; struct edp_power_seq pps; u8 drrs_msa_timing_delay; bool low_vswing; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index c19e99ee06b6..a94fc947cdb3 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5203,6 +5203,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, bool has_dpcd; enum pipe pipe = INVALID_PIPE; struct edid *edid; + bool retry; if (!intel_dp_is_edp(intel_dp)) return true; @@ -5222,6 +5223,9 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, return false; } + retry = intel_bios_init_panel(dev_priv, &intel_connector->panel, + encoder->devdata, NULL); + intel_pps_init(intel_dp); /* Cache DPCD and EDID for edp. */ @@ -5255,9 +5259,9 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, edid = ERR_PTR(-ENOENT); } intel_connector->edid = edid; - - intel_bios_init_panel(dev_priv, &intel_connector->panel, - encoder->devdata, IS_ERR(edid) ? NULL : edid); + if (retry) + intel_bios_init_panel(dev_priv, &intel_connector->panel, + encoder->devdata, IS_ERR(edid) ? NULL : edid); intel_panel_add_edid_fixed_modes(intel_connector, intel_connector->panel.vbt.drrs_type != DRRS_TYPE_NONE, diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c index b972fa6ec00d..da98b180639a 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -218,6 +218,16 @@ bxt_power_sequencer_idx(struct intel_dp *intel_dp) /* We should never land here with regular DP ports */ drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp)); + if (connector->panel.vbt.edp.pps_id == -1) { + /* + * Use 2nd PPS instance as default for 2nd EDP panel. + */ + if (connector->encoder->port == PORT_A) + return 0; + else + return 1; + } + if (!intel_dp->pps.pps_reset) return backlight_controller; @@ -1430,7 +1440,7 @@ void intel_pps_init(struct intel_dp *intel_dp) intel_dp->pps.initializing = true; INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work); - if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) + if (IS_GEMINILAKE(i915) || IS_BROXTON(i915) || DISPLAY_VER(i915) >= 12) intel_dp->get_pps_idx = bxt_power_sequencer_idx; else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) intel_dp->get_pps_idx = vlv_power_sequencer_pipe; -- 2.29.0 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario 2022-09-27 17:45 ` [Intel-gfx] [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario Animesh Manna @ 2022-10-04 7:48 ` Jani Nikula 2022-10-10 16:03 ` Manna, Animesh 0 siblings, 1 reply; 17+ messages in thread From: Jani Nikula @ 2022-10-04 7:48 UTC (permalink / raw) To: Animesh Manna, intel-gfx On Tue, 27 Sep 2022, Animesh Manna <animesh.manna@intel.com> wrote: > From display gen12 onwards to support dual EDP two instances of pps added. > Currently backlight controller and pps instance can be mapped together > for a specific panel. Extended support for gen12 for dual EDP usage. Frankly the dual PPS support was there already, but broken. This fixes it, and enables it for display 12+. > > v1: Iniital revision. > v2: Called intel_bios_panel_init w/o PNPID before intel_pps_init. [Jani] > v3: Set pps_id to -1 for pnpid type of panel which will be used by > bxt_power_sequencer_idx() to set 2nd pps instance as default for > 2nd EDP panel. [Jani] > > Cc: Jani Nikula <jani.nikula@intel.com> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Cc: Uma Shankar <uma.shankar@intel.com> > Signed-off-by: Animesh Manna <animesh.manna@intel.com> > --- > drivers/gpu/drm/i915/display/intel_bios.c | 13 +++++++++++-- > drivers/gpu/drm/i915/display/intel_bios.h | 2 +- > drivers/gpu/drm/i915/display/intel_display_types.h | 1 + > drivers/gpu/drm/i915/display/intel_dp.c | 10 +++++++--- > drivers/gpu/drm/i915/display/intel_pps.c | 12 +++++++++++- > 5 files changed, 31 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c > index 28bdb936cd1f..2015b6592754 100644 > --- a/drivers/gpu/drm/i915/display/intel_bios.c > +++ b/drivers/gpu/drm/i915/display/intel_bios.c > @@ -3175,13 +3175,14 @@ void intel_bios_init(struct drm_i915_private *i915) > kfree(oprom_vbt); > } > > -void intel_bios_init_panel(struct drm_i915_private *i915, > +bool intel_bios_init_panel(struct drm_i915_private *i915, > struct intel_panel *panel, > const struct intel_bios_encoder_data *devdata, > const struct edid *edid) > { > - init_vbt_panel_defaults(panel); > + bool retry = false; > > + init_vbt_panel_defaults(panel); > panel->vbt.panel_type = get_panel_type(i915, devdata, edid); > > parse_panel_options(i915, panel); > @@ -3195,6 +3196,14 @@ void intel_bios_init_panel(struct drm_i915_private *i915, > parse_psr(i915, panel); > parse_mipi_config(i915, panel); > parse_mipi_sequence(i915, panel); > + > + if (panel->vbt.panel_type == PANEL_TYPE_PNPID || > + panel->vbt.panel_type == PANEL_TYPE_FALLBACK) { > + panel->vbt.edp.pps_id = -1; > + retry = true; > + } Why do you initialize everything above if you know the panel type is garbage and we need to retry? I don't think the above functions were designed with the idea they could be called multiple times for the same panel. Return early if you know it's wrong. Also, don't return true if the EDID is provided. BR, Jani. > + > + return retry; > } > > /** > diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h > index e375405a7828..f8ef0274f3ee 100644 > --- a/drivers/gpu/drm/i915/display/intel_bios.h > +++ b/drivers/gpu/drm/i915/display/intel_bios.h > @@ -232,7 +232,7 @@ struct mipi_pps_data { > } __packed; > > void intel_bios_init(struct drm_i915_private *dev_priv); > -void intel_bios_init_panel(struct drm_i915_private *dev_priv, > +bool intel_bios_init_panel(struct drm_i915_private *dev_priv, > struct intel_panel *panel, > const struct intel_bios_encoder_data *devdata, > const struct edid *edid); > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h > index b78b29951241..0edc0b8f3743 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -307,6 +307,7 @@ struct intel_vbt_panel_data { > int preemphasis; > int vswing; > int bpp; > + int pps_id; > struct edp_power_seq pps; > u8 drrs_msa_timing_delay; > bool low_vswing; > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index c19e99ee06b6..a94fc947cdb3 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -5203,6 +5203,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, > bool has_dpcd; > enum pipe pipe = INVALID_PIPE; > struct edid *edid; > + bool retry; > > if (!intel_dp_is_edp(intel_dp)) > return true; > @@ -5222,6 +5223,9 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, > return false; > } > > + retry = intel_bios_init_panel(dev_priv, &intel_connector->panel, > + encoder->devdata, NULL); > + > intel_pps_init(intel_dp); > > /* Cache DPCD and EDID for edp. */ > @@ -5255,9 +5259,9 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, > edid = ERR_PTR(-ENOENT); > } > intel_connector->edid = edid; > - > - intel_bios_init_panel(dev_priv, &intel_connector->panel, > - encoder->devdata, IS_ERR(edid) ? NULL : edid); > + if (retry) > + intel_bios_init_panel(dev_priv, &intel_connector->panel, > + encoder->devdata, IS_ERR(edid) ? NULL : edid); > > intel_panel_add_edid_fixed_modes(intel_connector, > intel_connector->panel.vbt.drrs_type != DRRS_TYPE_NONE, > diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c > index b972fa6ec00d..da98b180639a 100644 > --- a/drivers/gpu/drm/i915/display/intel_pps.c > +++ b/drivers/gpu/drm/i915/display/intel_pps.c > @@ -218,6 +218,16 @@ bxt_power_sequencer_idx(struct intel_dp *intel_dp) > /* We should never land here with regular DP ports */ > drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp)); > > + if (connector->panel.vbt.edp.pps_id == -1) { > + /* > + * Use 2nd PPS instance as default for 2nd EDP panel. > + */ > + if (connector->encoder->port == PORT_A) > + return 0; > + else > + return 1; > + } > + > if (!intel_dp->pps.pps_reset) > return backlight_controller; > > @@ -1430,7 +1440,7 @@ void intel_pps_init(struct intel_dp *intel_dp) > intel_dp->pps.initializing = true; > INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work); > > - if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) > + if (IS_GEMINILAKE(i915) || IS_BROXTON(i915) || DISPLAY_VER(i915) >= 12) > intel_dp->get_pps_idx = bxt_power_sequencer_idx; > else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) > intel_dp->get_pps_idx = vlv_power_sequencer_pipe; -- Jani Nikula, Intel Open Source Graphics Center ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario 2022-10-04 7:48 ` Jani Nikula @ 2022-10-10 16:03 ` Manna, Animesh 0 siblings, 0 replies; 17+ messages in thread From: Manna, Animesh @ 2022-10-10 16:03 UTC (permalink / raw) To: Nikula, Jani, intel-gfx > -----Original Message----- > From: Nikula, Jani <jani.nikula@intel.com> > Sent: Tuesday, October 4, 2022 1:19 PM > To: Manna, Animesh <animesh.manna@intel.com>; intel- > gfx@lists.freedesktop.org > Cc: Manna, Animesh <animesh.manna@intel.com>; Ville Syrjälä > <ville.syrjala@linux.intel.com>; Shankar, Uma <uma.shankar@intel.com> > Subject: Re: [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario > > On Tue, 27 Sep 2022, Animesh Manna <animesh.manna@intel.com> wrote: > > From display gen12 onwards to support dual EDP two instances of pps added. > > Currently backlight controller and pps instance can be mapped together > > for a specific panel. Extended support for gen12 for dual EDP usage. > > Frankly the dual PPS support was there already, but broken. This fixes it, and > enables it for display 12+. > > > > > v1: Iniital revision. > > v2: Called intel_bios_panel_init w/o PNPID before intel_pps_init. > > [Jani] > > v3: Set pps_id to -1 for pnpid type of panel which will be used by > > bxt_power_sequencer_idx() to set 2nd pps instance as default for 2nd > > EDP panel. [Jani] > > > > Cc: Jani Nikula <jani.nikula@intel.com> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Cc: Uma Shankar <uma.shankar@intel.com> > > Signed-off-by: Animesh Manna <animesh.manna@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_bios.c | 13 +++++++++++-- > > drivers/gpu/drm/i915/display/intel_bios.h | 2 +- > > drivers/gpu/drm/i915/display/intel_display_types.h | 1 + > > drivers/gpu/drm/i915/display/intel_dp.c | 10 +++++++--- > > drivers/gpu/drm/i915/display/intel_pps.c | 12 +++++++++++- > > 5 files changed, 31 insertions(+), 7 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c > > b/drivers/gpu/drm/i915/display/intel_bios.c > > index 28bdb936cd1f..2015b6592754 100644 > > --- a/drivers/gpu/drm/i915/display/intel_bios.c > > +++ b/drivers/gpu/drm/i915/display/intel_bios.c > > @@ -3175,13 +3175,14 @@ void intel_bios_init(struct drm_i915_private > *i915) > > kfree(oprom_vbt); > > } > > > > -void intel_bios_init_panel(struct drm_i915_private *i915, > > +bool intel_bios_init_panel(struct drm_i915_private *i915, > > struct intel_panel *panel, > > const struct intel_bios_encoder_data *devdata, > > const struct edid *edid) > > { > > - init_vbt_panel_defaults(panel); > > + bool retry = false; > > > > + init_vbt_panel_defaults(panel); > > panel->vbt.panel_type = get_panel_type(i915, devdata, edid); > > > > parse_panel_options(i915, panel); > > @@ -3195,6 +3196,14 @@ void intel_bios_init_panel(struct drm_i915_private > *i915, > > parse_psr(i915, panel); > > parse_mipi_config(i915, panel); > > parse_mipi_sequence(i915, panel); > > + > > + if (panel->vbt.panel_type == PANEL_TYPE_PNPID || > > + panel->vbt.panel_type == PANEL_TYPE_FALLBACK) { > > + panel->vbt.edp.pps_id = -1; > > + retry = true; > > + } > > Why do you initialize everything above if you know the panel type is garbage and > we need to retry? I don't think the above functions were designed with the idea > they could be called multiple times for the same panel. > > Return early if you know it's wrong. Also, don't return true if the EDID is > provided. Thanks Jani for review, have sent the v4 after addressing the above comments. Regards, Animesh > > BR, > Jani. > > > + > > + return retry; > > } > > > > /** > > diff --git a/drivers/gpu/drm/i915/display/intel_bios.h > > b/drivers/gpu/drm/i915/display/intel_bios.h > > index e375405a7828..f8ef0274f3ee 100644 > > --- a/drivers/gpu/drm/i915/display/intel_bios.h > > +++ b/drivers/gpu/drm/i915/display/intel_bios.h > > @@ -232,7 +232,7 @@ struct mipi_pps_data { } __packed; > > > > void intel_bios_init(struct drm_i915_private *dev_priv); -void > > intel_bios_init_panel(struct drm_i915_private *dev_priv, > > +bool intel_bios_init_panel(struct drm_i915_private *dev_priv, > > struct intel_panel *panel, > > const struct intel_bios_encoder_data *devdata, > > const struct edid *edid); > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h > > b/drivers/gpu/drm/i915/display/intel_display_types.h > > index b78b29951241..0edc0b8f3743 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > > @@ -307,6 +307,7 @@ struct intel_vbt_panel_data { > > int preemphasis; > > int vswing; > > int bpp; > > + int pps_id; > > struct edp_power_seq pps; > > u8 drrs_msa_timing_delay; > > bool low_vswing; > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > > b/drivers/gpu/drm/i915/display/intel_dp.c > > index c19e99ee06b6..a94fc947cdb3 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > @@ -5203,6 +5203,7 @@ static bool intel_edp_init_connector(struct intel_dp > *intel_dp, > > bool has_dpcd; > > enum pipe pipe = INVALID_PIPE; > > struct edid *edid; > > + bool retry; > > > > if (!intel_dp_is_edp(intel_dp)) > > return true; > > @@ -5222,6 +5223,9 @@ static bool intel_edp_init_connector(struct intel_dp > *intel_dp, > > return false; > > } > > > > + retry = intel_bios_init_panel(dev_priv, &intel_connector->panel, > > + encoder->devdata, NULL); > > + > > intel_pps_init(intel_dp); > > > > /* Cache DPCD and EDID for edp. */ > > @@ -5255,9 +5259,9 @@ static bool intel_edp_init_connector(struct intel_dp > *intel_dp, > > edid = ERR_PTR(-ENOENT); > > } > > intel_connector->edid = edid; > > - > > - intel_bios_init_panel(dev_priv, &intel_connector->panel, > > - encoder->devdata, IS_ERR(edid) ? NULL : edid); > > + if (retry) > > + intel_bios_init_panel(dev_priv, &intel_connector->panel, > > + encoder->devdata, IS_ERR(edid) ? NULL : > edid); > > > > intel_panel_add_edid_fixed_modes(intel_connector, > > intel_connector->panel.vbt.drrs_type > != DRRS_TYPE_NONE, diff > > --git a/drivers/gpu/drm/i915/display/intel_pps.c > > b/drivers/gpu/drm/i915/display/intel_pps.c > > index b972fa6ec00d..da98b180639a 100644 > > --- a/drivers/gpu/drm/i915/display/intel_pps.c > > +++ b/drivers/gpu/drm/i915/display/intel_pps.c > > @@ -218,6 +218,16 @@ bxt_power_sequencer_idx(struct intel_dp *intel_dp) > > /* We should never land here with regular DP ports */ > > drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp)); > > > > + if (connector->panel.vbt.edp.pps_id == -1) { > > + /* > > + * Use 2nd PPS instance as default for 2nd EDP panel. > > + */ > > + if (connector->encoder->port == PORT_A) > > + return 0; > > + else > > + return 1; > > + } > > + > > if (!intel_dp->pps.pps_reset) > > return backlight_controller; > > > > @@ -1430,7 +1440,7 @@ void intel_pps_init(struct intel_dp *intel_dp) > > intel_dp->pps.initializing = true; > > INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, > > edp_panel_vdd_work); > > > > - if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) > > + if (IS_GEMINILAKE(i915) || IS_BROXTON(i915) || DISPLAY_VER(i915) >= > > +12) > > intel_dp->get_pps_idx = bxt_power_sequencer_idx; > > else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) > > intel_dp->get_pps_idx = vlv_power_sequencer_pipe; > > -- > Jani Nikula, Intel Open Source Graphics Center ^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] [PATCH 1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup @ 2022-10-10 15:54 Animesh Manna 2022-10-10 15:54 ` [Intel-gfx] [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario Animesh Manna 0 siblings, 1 reply; 17+ messages in thread From: Animesh Manna @ 2022-10-10 15:54 UTC (permalink / raw) To: intel-gfx; +Cc: Jani Nikula Simplified pps_get_register() which use get_pps_idx() hook to derive the pps instance and get_pps_idx() will be initialized at pps_init(). v1: Initial version. Got r-b from Jani. Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> --- .../gpu/drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_pps.c | 15 ++++++++++----- 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index e2b853e9e51d..44ab296c1f04 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1694,6 +1694,7 @@ struct intel_dp { u8 (*preemph_max)(struct intel_dp *intel_dp); u8 (*voltage_max)(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state); + int (*get_pps_idx)(struct intel_dp *intel_dp); /* Displayport compliance testing */ struct intel_dp_compliance compliance; diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c index 21944f5bf3a8..b972fa6ec00d 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -364,12 +364,10 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp, struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); int pps_idx = 0; - memset(regs, 0, sizeof(*regs)); + if (intel_dp->get_pps_idx) + pps_idx = intel_dp->get_pps_idx(intel_dp); - if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) - pps_idx = bxt_power_sequencer_idx(intel_dp); - else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) - pps_idx = vlv_power_sequencer_pipe(intel_dp); + memset(regs, 0, sizeof(*regs)); regs->pp_ctrl = PP_CONTROL(pps_idx); regs->pp_stat = PP_STATUS(pps_idx); @@ -1432,6 +1430,13 @@ void intel_pps_init(struct intel_dp *intel_dp) intel_dp->pps.initializing = true; INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work); + if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) + intel_dp->get_pps_idx = bxt_power_sequencer_idx; + else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) + intel_dp->get_pps_idx = vlv_power_sequencer_pipe; + else + intel_dp->get_pps_idx = NULL; + pps_init_timestamps(intel_dp); with_intel_pps_lock(intel_dp, wakeref) { -- 2.29.0 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Intel-gfx] [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario 2022-10-10 15:54 [Intel-gfx] [PATCH 1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup Animesh Manna @ 2022-10-10 15:54 ` Animesh Manna 2022-10-17 13:08 ` Jani Nikula 0 siblings, 1 reply; 17+ messages in thread From: Animesh Manna @ 2022-10-10 15:54 UTC (permalink / raw) To: intel-gfx; +Cc: Jani Nikula From display gen12 onwards to support dual EDP two instances of pps added. Currently backlight controller and pps instance can be mapped together for a specific panel. Currently dual PPS support is broken. This patch fixes it and enables for display 12+. v1: Iniital revision. v2: Called intel_bios_panel_init w/o PNPID before intel_pps_init. [Jani] v3: Set pps_id to -1 for pnpid type of panel which will be used by bxt_power_sequencer_idx() to set 2nd pps instance as default for 2nd EDP panel. [Jani] v4: Early return for PANEL_TYPE_FALLBACK. [Jani] Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> --- drivers/gpu/drm/i915/display/intel_bios.c | 13 +++++++++++-- drivers/gpu/drm/i915/display/intel_bios.h | 2 +- drivers/gpu/drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_dp.c | 10 +++++++--- drivers/gpu/drm/i915/display/intel_pps.c | 12 +++++++++++- 5 files changed, 31 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index c2987f2c2b2e..dd3cd2ca815d 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -3183,15 +3183,22 @@ void intel_bios_init(struct drm_i915_private *i915) kfree(oprom_vbt); } -void intel_bios_init_panel(struct drm_i915_private *i915, +bool intel_bios_init_panel(struct drm_i915_private *i915, struct intel_panel *panel, const struct intel_bios_encoder_data *devdata, const struct edid *edid) { init_vbt_panel_defaults(panel); - panel->vbt.panel_type = get_panel_type(i915, devdata, edid); + if (panel->vbt.panel_type == PANEL_TYPE_PNPID || + panel->vbt.panel_type == PANEL_TYPE_FALLBACK) { + panel->vbt.edp.pps_id = -1; + + if (!edid && intel_bios_encoder_supports_edp(devdata)) + return true; + } + parse_panel_options(i915, panel); parse_generic_dtd(i915, panel); parse_lfp_data(i915, panel); @@ -3203,6 +3210,8 @@ void intel_bios_init_panel(struct drm_i915_private *i915, parse_psr(i915, panel); parse_mipi_config(i915, panel); parse_mipi_sequence(i915, panel); + + return false; } /** diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h index e375405a7828..f8ef0274f3ee 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.h +++ b/drivers/gpu/drm/i915/display/intel_bios.h @@ -232,7 +232,7 @@ struct mipi_pps_data { } __packed; void intel_bios_init(struct drm_i915_private *dev_priv); -void intel_bios_init_panel(struct drm_i915_private *dev_priv, +bool intel_bios_init_panel(struct drm_i915_private *dev_priv, struct intel_panel *panel, const struct intel_bios_encoder_data *devdata, const struct edid *edid); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 44ab296c1f04..37e8309207bf 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -307,6 +307,7 @@ struct intel_vbt_panel_data { int preemphasis; int vswing; int bpp; + int pps_id; struct edp_power_seq pps; u8 drrs_msa_timing_delay; bool low_vswing; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 70b06806ec0d..50d9223562e2 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5235,6 +5235,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; bool has_dpcd; struct edid *edid; + bool retry; if (!intel_dp_is_edp(intel_dp)) return true; @@ -5254,6 +5255,9 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, return false; } + retry = intel_bios_init_panel(dev_priv, &intel_connector->panel, + encoder->devdata, NULL); + intel_pps_init(intel_dp); /* Cache DPCD and EDID for edp. */ @@ -5288,9 +5292,9 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, edid = ERR_PTR(-ENOENT); } intel_connector->edid = edid; - - intel_bios_init_panel(dev_priv, &intel_connector->panel, - encoder->devdata, IS_ERR(edid) ? NULL : edid); + if (retry) + intel_bios_init_panel(dev_priv, &intel_connector->panel, + encoder->devdata, IS_ERR(edid) ? NULL : edid); intel_panel_add_edid_fixed_modes(intel_connector, true); diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c index b972fa6ec00d..da98b180639a 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -218,6 +218,16 @@ bxt_power_sequencer_idx(struct intel_dp *intel_dp) /* We should never land here with regular DP ports */ drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp)); + if (connector->panel.vbt.edp.pps_id == -1) { + /* + * Use 2nd PPS instance as default for 2nd EDP panel. + */ + if (connector->encoder->port == PORT_A) + return 0; + else + return 1; + } + if (!intel_dp->pps.pps_reset) return backlight_controller; @@ -1430,7 +1440,7 @@ void intel_pps_init(struct intel_dp *intel_dp) intel_dp->pps.initializing = true; INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work); - if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) + if (IS_GEMINILAKE(i915) || IS_BROXTON(i915) || DISPLAY_VER(i915) >= 12) intel_dp->get_pps_idx = bxt_power_sequencer_idx; else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) intel_dp->get_pps_idx = vlv_power_sequencer_pipe; -- 2.29.0 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario 2022-10-10 15:54 ` [Intel-gfx] [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario Animesh Manna @ 2022-10-17 13:08 ` Jani Nikula 2022-10-18 8:50 ` Manna, Animesh 0 siblings, 1 reply; 17+ messages in thread From: Jani Nikula @ 2022-10-17 13:08 UTC (permalink / raw) To: Animesh Manna, intel-gfx On Mon, 10 Oct 2022, Animesh Manna <animesh.manna@intel.com> wrote: > From display gen12 onwards to support dual EDP two instances of pps added. > Currently backlight controller and pps instance can be mapped together > for a specific panel. Currently dual PPS support is broken. This patch fixes > it and enables for display 12+. > > v1: Iniital revision. > v2: Called intel_bios_panel_init w/o PNPID before intel_pps_init. [Jani] > v3: Set pps_id to -1 for pnpid type of panel which will be used by > bxt_power_sequencer_idx() to set 2nd pps instance as default for > 2nd EDP panel. [Jani] > v4: Early return for PANEL_TYPE_FALLBACK. [Jani] > > Cc: Jani Nikula <jani.nikula@intel.com> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Cc: Uma Shankar <uma.shankar@intel.com> > Signed-off-by: Animesh Manna <animesh.manna@intel.com> > --- > drivers/gpu/drm/i915/display/intel_bios.c | 13 +++++++++++-- > drivers/gpu/drm/i915/display/intel_bios.h | 2 +- > drivers/gpu/drm/i915/display/intel_display_types.h | 1 + > drivers/gpu/drm/i915/display/intel_dp.c | 10 +++++++--- > drivers/gpu/drm/i915/display/intel_pps.c | 12 +++++++++++- > 5 files changed, 31 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c > index c2987f2c2b2e..dd3cd2ca815d 100644 > --- a/drivers/gpu/drm/i915/display/intel_bios.c > +++ b/drivers/gpu/drm/i915/display/intel_bios.c > @@ -3183,15 +3183,22 @@ void intel_bios_init(struct drm_i915_private *i915) > kfree(oprom_vbt); > } > > -void intel_bios_init_panel(struct drm_i915_private *i915, > +bool intel_bios_init_panel(struct drm_i915_private *i915, > struct intel_panel *panel, > const struct intel_bios_encoder_data *devdata, > const struct edid *edid) > { > init_vbt_panel_defaults(panel); > - Please don't do superfluous whitespace changes. > panel->vbt.panel_type = get_panel_type(i915, devdata, edid); > > + if (panel->vbt.panel_type == PANEL_TYPE_PNPID || > + panel->vbt.panel_type == PANEL_TYPE_FALLBACK) { > + panel->vbt.edp.pps_id = -1; > + > + if (!edid && intel_bios_encoder_supports_edp(devdata)) > + return true; > + } > + if (panel->vbt.panel_type == PANEL_TYPE_FALLBACK && !edid) { panel->vbt.backlight.controller = -1; return true; } > parse_panel_options(i915, panel); > parse_generic_dtd(i915, panel); > parse_lfp_data(i915, panel); > @@ -3203,6 +3210,8 @@ void intel_bios_init_panel(struct drm_i915_private *i915, > parse_psr(i915, panel); > parse_mipi_config(i915, panel); > parse_mipi_sequence(i915, panel); > + > + return false; > } > > /** > diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h > index e375405a7828..f8ef0274f3ee 100644 > --- a/drivers/gpu/drm/i915/display/intel_bios.h > +++ b/drivers/gpu/drm/i915/display/intel_bios.h > @@ -232,7 +232,7 @@ struct mipi_pps_data { > } __packed; > > void intel_bios_init(struct drm_i915_private *dev_priv); > -void intel_bios_init_panel(struct drm_i915_private *dev_priv, > +bool intel_bios_init_panel(struct drm_i915_private *dev_priv, > struct intel_panel *panel, > const struct intel_bios_encoder_data *devdata, > const struct edid *edid); > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h > index 44ab296c1f04..37e8309207bf 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -307,6 +307,7 @@ struct intel_vbt_panel_data { > int preemphasis; > int vswing; > int bpp; > + int pps_id; Unnecessary. > struct edp_power_seq pps; > u8 drrs_msa_timing_delay; > bool low_vswing; > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index 70b06806ec0d..50d9223562e2 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -5235,6 +5235,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, > struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; > bool has_dpcd; > struct edid *edid; > + bool retry; > > if (!intel_dp_is_edp(intel_dp)) > return true; > @@ -5254,6 +5255,9 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, > return false; > } > > + retry = intel_bios_init_panel(dev_priv, &intel_connector->panel, > + encoder->devdata, NULL); > + > intel_pps_init(intel_dp); > > /* Cache DPCD and EDID for edp. */ > @@ -5288,9 +5292,9 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, > edid = ERR_PTR(-ENOENT); > } > intel_connector->edid = edid; > - > - intel_bios_init_panel(dev_priv, &intel_connector->panel, > - encoder->devdata, IS_ERR(edid) ? NULL : edid); > + if (retry) > + intel_bios_init_panel(dev_priv, &intel_connector->panel, > + encoder->devdata, IS_ERR(edid) ? NULL : edid); > > intel_panel_add_edid_fixed_modes(intel_connector, true); > > diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c > index b972fa6ec00d..da98b180639a 100644 > --- a/drivers/gpu/drm/i915/display/intel_pps.c > +++ b/drivers/gpu/drm/i915/display/intel_pps.c > @@ -218,6 +218,16 @@ bxt_power_sequencer_idx(struct intel_dp *intel_dp) > /* We should never land here with regular DP ports */ > drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp)); > > + if (connector->panel.vbt.edp.pps_id == -1) { if (backlight_controller == -1) backlight_controller = connector->encoder->port == PORT_A ? 0 : 1; > + /* > + * Use 2nd PPS instance as default for 2nd EDP panel. > + */ > + if (connector->encoder->port == PORT_A) > + return 0; > + else > + return 1; > + } > + > if (!intel_dp->pps.pps_reset) > return backlight_controller; > > @@ -1430,7 +1440,7 @@ void intel_pps_init(struct intel_dp *intel_dp) > intel_dp->pps.initializing = true; > INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work); > > - if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) > + if (IS_GEMINILAKE(i915) || IS_BROXTON(i915) || DISPLAY_VER(i915) >= 12) > intel_dp->get_pps_idx = bxt_power_sequencer_idx; > else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) > intel_dp->get_pps_idx = vlv_power_sequencer_pipe; -- Jani Nikula, Intel Open Source Graphics Center ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario 2022-10-17 13:08 ` Jani Nikula @ 2022-10-18 8:50 ` Manna, Animesh 0 siblings, 0 replies; 17+ messages in thread From: Manna, Animesh @ 2022-10-18 8:50 UTC (permalink / raw) To: Nikula, Jani, intel-gfx Thanks Jani for review. Floated a new version after addressing the review comments in this series. https://patchwork.freedesktop.org/series/109820/ Regards, Animesh > -----Original Message----- > From: Nikula, Jani <jani.nikula@intel.com> > Sent: Monday, October 17, 2022 6:39 PM > To: Manna, Animesh <animesh.manna@intel.com>; intel- > gfx@lists.freedesktop.org > Cc: Manna, Animesh <animesh.manna@intel.com>; Ville Syrjälä > <ville.syrjala@linux.intel.com>; Shankar, Uma <uma.shankar@intel.com> > Subject: Re: [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario > > On Mon, 10 Oct 2022, Animesh Manna <animesh.manna@intel.com> wrote: > > From display gen12 onwards to support dual EDP two instances of pps added. > > Currently backlight controller and pps instance can be mapped together > > for a specific panel. Currently dual PPS support is broken. This patch > > fixes it and enables for display 12+. > > > > v1: Iniital revision. > > v2: Called intel_bios_panel_init w/o PNPID before intel_pps_init. > > [Jani] > > v3: Set pps_id to -1 for pnpid type of panel which will be used by > > bxt_power_sequencer_idx() to set 2nd pps instance as default for 2nd > > EDP panel. [Jani] > > v4: Early return for PANEL_TYPE_FALLBACK. [Jani] > > > > Cc: Jani Nikula <jani.nikula@intel.com> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Cc: Uma Shankar <uma.shankar@intel.com> > > Signed-off-by: Animesh Manna <animesh.manna@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_bios.c | 13 +++++++++++-- > > drivers/gpu/drm/i915/display/intel_bios.h | 2 +- > > drivers/gpu/drm/i915/display/intel_display_types.h | 1 + > > drivers/gpu/drm/i915/display/intel_dp.c | 10 +++++++--- > > drivers/gpu/drm/i915/display/intel_pps.c | 12 +++++++++++- > > 5 files changed, 31 insertions(+), 7 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c > > b/drivers/gpu/drm/i915/display/intel_bios.c > > index c2987f2c2b2e..dd3cd2ca815d 100644 > > --- a/drivers/gpu/drm/i915/display/intel_bios.c > > +++ b/drivers/gpu/drm/i915/display/intel_bios.c > > @@ -3183,15 +3183,22 @@ void intel_bios_init(struct drm_i915_private > *i915) > > kfree(oprom_vbt); > > } > > > > -void intel_bios_init_panel(struct drm_i915_private *i915, > > +bool intel_bios_init_panel(struct drm_i915_private *i915, > > struct intel_panel *panel, > > const struct intel_bios_encoder_data *devdata, > > const struct edid *edid) > > { > > init_vbt_panel_defaults(panel); > > - > > Please don't do superfluous whitespace changes. > > > panel->vbt.panel_type = get_panel_type(i915, devdata, edid); > > > > + if (panel->vbt.panel_type == PANEL_TYPE_PNPID || > > + panel->vbt.panel_type == PANEL_TYPE_FALLBACK) { > > + panel->vbt.edp.pps_id = -1; > > + > > + if (!edid && intel_bios_encoder_supports_edp(devdata)) > > + return true; > > + } > > + > > if (panel->vbt.panel_type == PANEL_TYPE_FALLBACK && !edid) { > panel->vbt.backlight.controller = -1; > return true; > } > > > parse_panel_options(i915, panel); > > parse_generic_dtd(i915, panel); > > parse_lfp_data(i915, panel); > > @@ -3203,6 +3210,8 @@ void intel_bios_init_panel(struct drm_i915_private > *i915, > > parse_psr(i915, panel); > > parse_mipi_config(i915, panel); > > parse_mipi_sequence(i915, panel); > > + > > + return false; > > } > > > > /** > > diff --git a/drivers/gpu/drm/i915/display/intel_bios.h > > b/drivers/gpu/drm/i915/display/intel_bios.h > > index e375405a7828..f8ef0274f3ee 100644 > > --- a/drivers/gpu/drm/i915/display/intel_bios.h > > +++ b/drivers/gpu/drm/i915/display/intel_bios.h > > @@ -232,7 +232,7 @@ struct mipi_pps_data { } __packed; > > > > void intel_bios_init(struct drm_i915_private *dev_priv); -void > > intel_bios_init_panel(struct drm_i915_private *dev_priv, > > +bool intel_bios_init_panel(struct drm_i915_private *dev_priv, > > struct intel_panel *panel, > > const struct intel_bios_encoder_data *devdata, > > const struct edid *edid); > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h > > b/drivers/gpu/drm/i915/display/intel_display_types.h > > index 44ab296c1f04..37e8309207bf 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > > @@ -307,6 +307,7 @@ struct intel_vbt_panel_data { > > int preemphasis; > > int vswing; > > int bpp; > > + int pps_id; > > Unnecessary. > > > struct edp_power_seq pps; > > u8 drrs_msa_timing_delay; > > bool low_vswing; > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > > b/drivers/gpu/drm/i915/display/intel_dp.c > > index 70b06806ec0d..50d9223562e2 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > @@ -5235,6 +5235,7 @@ static bool intel_edp_init_connector(struct intel_dp > *intel_dp, > > struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; > > bool has_dpcd; > > struct edid *edid; > > + bool retry; > > > > if (!intel_dp_is_edp(intel_dp)) > > return true; > > @@ -5254,6 +5255,9 @@ static bool intel_edp_init_connector(struct intel_dp > *intel_dp, > > return false; > > } > > > > + retry = intel_bios_init_panel(dev_priv, &intel_connector->panel, > > + encoder->devdata, NULL); > > + > > intel_pps_init(intel_dp); > > > > /* Cache DPCD and EDID for edp. */ > > @@ -5288,9 +5292,9 @@ static bool intel_edp_init_connector(struct intel_dp > *intel_dp, > > edid = ERR_PTR(-ENOENT); > > } > > intel_connector->edid = edid; > > - > > - intel_bios_init_panel(dev_priv, &intel_connector->panel, > > - encoder->devdata, IS_ERR(edid) ? NULL : edid); > > + if (retry) > > + intel_bios_init_panel(dev_priv, &intel_connector->panel, > > + encoder->devdata, IS_ERR(edid) ? NULL : > edid); > > > > intel_panel_add_edid_fixed_modes(intel_connector, true); > > > > diff --git a/drivers/gpu/drm/i915/display/intel_pps.c > > b/drivers/gpu/drm/i915/display/intel_pps.c > > index b972fa6ec00d..da98b180639a 100644 > > --- a/drivers/gpu/drm/i915/display/intel_pps.c > > +++ b/drivers/gpu/drm/i915/display/intel_pps.c > > @@ -218,6 +218,16 @@ bxt_power_sequencer_idx(struct intel_dp *intel_dp) > > /* We should never land here with regular DP ports */ > > drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp)); > > > > + if (connector->panel.vbt.edp.pps_id == -1) { > > if (backlight_controller == -1) > backlight_controller = connector->encoder->port == PORT_A ? 0 : 1; > > > + /* > > + * Use 2nd PPS instance as default for 2nd EDP panel. > > + */ > > + if (connector->encoder->port == PORT_A) > > + return 0; > > + else > > + return 1; > > + } > > + > > if (!intel_dp->pps.pps_reset) > > return backlight_controller; > > > > @@ -1430,7 +1440,7 @@ void intel_pps_init(struct intel_dp *intel_dp) > > intel_dp->pps.initializing = true; > > INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, > > edp_panel_vdd_work); > > > > - if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) > > + if (IS_GEMINILAKE(i915) || IS_BROXTON(i915) || DISPLAY_VER(i915) >= > > +12) > > intel_dp->get_pps_idx = bxt_power_sequencer_idx; > > else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) > > intel_dp->get_pps_idx = vlv_power_sequencer_pipe; > > -- > Jani Nikula, Intel Open Source Graphics Center ^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] [PATCH 1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup @ 2022-10-18 8:39 Animesh Manna 2022-10-18 8:39 ` [Intel-gfx] [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario Animesh Manna 0 siblings, 1 reply; 17+ messages in thread From: Animesh Manna @ 2022-10-18 8:39 UTC (permalink / raw) To: intel-gfx; +Cc: Jani Nikula Simplified pps_get_register() which use get_pps_idx() hook to derive the pps instance and get_pps_idx() will be initialized at pps_init(). v1: Initial version. Got r-b from Jani. v2: Corrected unintentional change around memset() call. [Jani] Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> --- drivers/gpu/drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_pps.c | 14 +++++++++----- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index e2b853e9e51d..44ab296c1f04 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1694,6 +1694,7 @@ struct intel_dp { u8 (*preemph_max)(struct intel_dp *intel_dp); u8 (*voltage_max)(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state); + int (*get_pps_idx)(struct intel_dp *intel_dp); /* Displayport compliance testing */ struct intel_dp_compliance compliance; diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c index 21944f5bf3a8..9ed62c891b8c 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -365,11 +365,8 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp, int pps_idx = 0; memset(regs, 0, sizeof(*regs)); - - if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) - pps_idx = bxt_power_sequencer_idx(intel_dp); - else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) - pps_idx = vlv_power_sequencer_pipe(intel_dp); + if (intel_dp->get_pps_idx) + pps_idx = intel_dp->get_pps_idx(intel_dp); regs->pp_ctrl = PP_CONTROL(pps_idx); regs->pp_stat = PP_STATUS(pps_idx); @@ -1432,6 +1429,13 @@ void intel_pps_init(struct intel_dp *intel_dp) intel_dp->pps.initializing = true; INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work); + if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) + intel_dp->get_pps_idx = bxt_power_sequencer_idx; + else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) + intel_dp->get_pps_idx = vlv_power_sequencer_pipe; + else + intel_dp->get_pps_idx = NULL; + pps_init_timestamps(intel_dp); with_intel_pps_lock(intel_dp, wakeref) { -- 2.29.0 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Intel-gfx] [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario 2022-10-18 8:39 [Intel-gfx] [PATCH 1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup Animesh Manna @ 2022-10-18 8:39 ` Animesh Manna 0 siblings, 0 replies; 17+ messages in thread From: Animesh Manna @ 2022-10-18 8:39 UTC (permalink / raw) To: intel-gfx; +Cc: Jani Nikula From display gen12 onwards to support dual EDP two instances of pps added. Currently backlight controller and pps instance can be mapped together for a specific panel. Currently dual PPS support is broken. This patch fixes it and enables for display 12+. v1: Iniital revision. v2: Called intel_bios_panel_init w/o PNPID before intel_pps_init. [Jani] v3: Set pps_id to -1 for pnpid type of panel which will be used by bxt_power_sequencer_idx() to set 2nd pps instance as default for 2nd EDP panel. [Jani] v4: Early return for PANEL_TYPE_FALLBACK. [Jani] v5: Removed additional pps_id variable and reused backlight controller. [Jani] Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> --- drivers/gpu/drm/i915/display/intel_bios.c | 9 ++++++++- drivers/gpu/drm/i915/display/intel_bios.h | 2 +- drivers/gpu/drm/i915/display/intel_dp.c | 10 +++++++--- drivers/gpu/drm/i915/display/intel_pps.c | 12 +++++++++++- 4 files changed, 27 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index c2987f2c2b2e..1c1eea061fbb 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -3183,7 +3183,7 @@ void intel_bios_init(struct drm_i915_private *i915) kfree(oprom_vbt); } -void intel_bios_init_panel(struct drm_i915_private *i915, +bool intel_bios_init_panel(struct drm_i915_private *i915, struct intel_panel *panel, const struct intel_bios_encoder_data *devdata, const struct edid *edid) @@ -3192,6 +3192,11 @@ void intel_bios_init_panel(struct drm_i915_private *i915, panel->vbt.panel_type = get_panel_type(i915, devdata, edid); + if (panel->vbt.panel_type == PANEL_TYPE_FALLBACK && !edid) { + panel->vbt.backlight.controller = -1; + return true; + } + parse_panel_options(i915, panel); parse_generic_dtd(i915, panel); parse_lfp_data(i915, panel); @@ -3203,6 +3208,8 @@ void intel_bios_init_panel(struct drm_i915_private *i915, parse_psr(i915, panel); parse_mipi_config(i915, panel); parse_mipi_sequence(i915, panel); + + return false; } /** diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h index e375405a7828..f8ef0274f3ee 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.h +++ b/drivers/gpu/drm/i915/display/intel_bios.h @@ -232,7 +232,7 @@ struct mipi_pps_data { } __packed; void intel_bios_init(struct drm_i915_private *dev_priv); -void intel_bios_init_panel(struct drm_i915_private *dev_priv, +bool intel_bios_init_panel(struct drm_i915_private *dev_priv, struct intel_panel *panel, const struct intel_bios_encoder_data *devdata, const struct edid *edid); diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index a060903891b2..6d3a0fe06359 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5234,6 +5234,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; bool has_dpcd; struct edid *edid; + bool retry; if (!intel_dp_is_edp(intel_dp)) return true; @@ -5253,6 +5254,9 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, return false; } + retry = intel_bios_init_panel(dev_priv, &intel_connector->panel, + encoder->devdata, NULL); + intel_pps_init(intel_dp); /* Cache DPCD and EDID for edp. */ @@ -5287,9 +5291,9 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, edid = ERR_PTR(-ENOENT); } intel_connector->edid = edid; - - intel_bios_init_panel(dev_priv, &intel_connector->panel, - encoder->devdata, IS_ERR(edid) ? NULL : edid); + if (retry) + intel_bios_init_panel(dev_priv, &intel_connector->panel, + encoder->devdata, IS_ERR(edid) ? NULL : edid); intel_panel_add_edid_fixed_modes(intel_connector, true); diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c index 9ed62c891b8c..f9899305d6e0 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -218,6 +218,16 @@ bxt_power_sequencer_idx(struct intel_dp *intel_dp) /* We should never land here with regular DP ports */ drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp)); + if (backlight_controller == -1) { + /* + * Use 2nd PPS instance as default for 2nd EDP panel. + */ + if (connector->encoder->port == PORT_A) + return 0; + else + return 1; + } + if (!intel_dp->pps.pps_reset) return backlight_controller; @@ -1429,7 +1439,7 @@ void intel_pps_init(struct intel_dp *intel_dp) intel_dp->pps.initializing = true; INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work); - if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) + if (IS_GEMINILAKE(i915) || IS_BROXTON(i915) || DISPLAY_VER(i915) >= 12) intel_dp->get_pps_idx = bxt_power_sequencer_idx; else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) intel_dp->get_pps_idx = vlv_power_sequencer_pipe; -- 2.29.0 ^ permalink raw reply related [flat|nested] 17+ messages in thread
end of thread, other threads:[~2022-10-18 8:51 UTC | newest] Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-09-16 8:31 [Intel-gfx] [PATCH 1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup Animesh Manna 2022-09-16 8:31 ` [Intel-gfx] [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario Animesh Manna 2022-09-16 8:58 ` Ville Syrjälä 2022-09-16 11:02 ` Manna, Animesh 2022-09-16 11:29 ` Jani Nikula 2022-09-20 13:49 ` Manna, Animesh 2022-09-26 10:35 ` Jani Nikula 2022-09-27 17:53 ` Manna, Animesh 2022-09-16 10:16 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup Patchwork 2022-09-16 14:29 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 2022-09-27 17:45 [Intel-gfx] [PATCH 1/2] " Animesh Manna 2022-09-27 17:45 ` [Intel-gfx] [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario Animesh Manna 2022-10-04 7:48 ` Jani Nikula 2022-10-10 16:03 ` Manna, Animesh 2022-10-10 15:54 [Intel-gfx] [PATCH 1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup Animesh Manna 2022-10-10 15:54 ` [Intel-gfx] [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario Animesh Manna 2022-10-17 13:08 ` Jani Nikula 2022-10-18 8:50 ` Manna, Animesh 2022-10-18 8:39 [Intel-gfx] [PATCH 1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup Animesh Manna 2022-10-18 8:39 ` [Intel-gfx] [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario Animesh Manna
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