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Niedermayr" To: , CC: , , , Subject: [PATCH v5 0/3] gpmc wait-pin additions Date: Fri, 16 Sep 2022 14:07:46 +0200 Message-ID: <20220916120749.2517727-1-benedikt.niedermayr@siemens.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [144.145.220.65] X-ClientProxiedBy: DEMCHDC89XA.ad011.siemens.net (139.25.226.103) To DEMCHDC89XA.ad011.siemens.net (139.25.226.103) X-TM-AS-Product-Ver: SMEX-14.0.0.3080-8.6.1018-26680.007 X-TM-AS-Result: No-10--17.586200-8.000000 X-TMASE-MatchedRID: bAH4BEb3OaKdIa4Z4akFf4mIDnzSS8mZtE4rffipOm437vkU5XIl4H+s iCf/QKJTsS0sZEB7c8b8MCBvciFjZ6ZSzaLPCwndmx4L2mG7WWDEzah3MhwU3YlSWYvdSPSY5GN m5cTRaUfMApOK4R8F4vSCiap+6KvtkKwzGM++sccw3q04xc4gVuJPyge9irBS9FQh3flUIh4mKH /Kj46+VdWM2x6EZ/S9sHT5iFhz4jxhnmcId02xRZbK9NqUDMpYRwPZcL7YQSYqsMfMfrOZReP6p +9mEWlCIFYJ0Vciv4/qzkhCUQRGlwK7UFMzsbiB59JoNf8FRHhiWV0DQ85LUqiUivh0j2PvjWP6 asaL88WXuKyHuSLTfHxZFXOgydpQfS0Ip2eEHnwj/1Rbkzl1EymDnI5x2hWC9xS3mVzWUuBk431 H65J9AA== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--17.586200-8.000000 X-TMASE-Version: SMEX-14.0.0.3080-8.6.1018-26680.007 X-TM-SNTS-SMTP: 2C33C451ADE99D9D5CB74F3DD155B9FF06A153ECDE12C31819AE177D8C5DF31D2000:8 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: HE1EUR01FT063:EE_|AM0PR10MB3652:EE_ X-MS-Office365-Filtering-Correlation-Id: 7ddf7de0-6d6c-4b8c-2f89-08da97dc1cc8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: k6Wtg3k9S9QL7IgMk5aoMPZGy9w1vmyglqr6qNXUT4daWX2YJsDuF7Uz2b7kbLGxMuzeeAGlNvUs1gguSObl5jmxU1NIfcWg5aBEHuL2BHXc5o1aSkz2p5E41eDH8Y90qBDwSXGa1yzP9nO/90/4VbZa7ssxrTo+n6J3n14S+7lUfHV1kAUVbghnugVhK1HNPowPz8hkNJlUvXaK6nqA707kyJ0vwhcQV/Ek5xjOrXU7cITHGRidLqvtSNmyks2KWfakgS6VA1z0ryvRURLRNIyPtQUujPEXaomdcie7qMxCpGSNF08h6Z5MTAYuY0cOaBjIq/U6YzPYQVbfz0GcFsvhD8KTcyYp11OCY1SpItZ1mYUNZx1r9aEssWrrMSZfAYMP2CvBLOzHR0H/Qb6h23jPZdnuJ95OG43WPbqboP4nM5oDm8BuPEOcDTGqr/Ed+rXaFYjqZMC7A2y8oPlm7LSrkIw2InCfblyVgeZZxjGsiA/Ts4DW+XJrY0ceJbRhuJHcvv47f6ZmDOe1Ui0vNMZfmMaadsODmGZCGg1JiJw7SbNylK6qPPcADdgeS3MoqQ99lpjFtNZtjxzigLE/LBhcyHgXmLkvsbJTJJJT7XuFs8vhXiJeft0jfyxOm4pScl0RfSKyzSoRibW+lMOi7ApRVZY0lItc/GbA7BLYBToy9zovsT3I9FT0fm5qxF3mtF2KaO0+TpOtlKPDwNx2i9V9E/0ao3/9f2rdtAjth8ykNJaxoLDtRovGYPn3eeZ2sHrQDEOFy2Zj50eoqoyabQ== X-Forefront-Antispam-Report: CIP:194.138.21.74;CTRY:DE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:hybrid.siemens.com;PTR:hybrid.siemens.com;CAT:NONE;SFS:(13230022)(4636009)(346002)(376002)(39860400002)(136003)(396003)(451199015)(40470700004)(36840700001)(46966006)(36860700001)(36756003)(478600001)(70206006)(70586007)(41300700001)(4326008)(6666004)(86362001)(8676002)(7596003)(82310400005)(8936002)(356005)(26005)(7636003)(40480700001)(54906003)(82740400003)(82960400001)(47076005)(186003)(1076003)(110136005)(40460700003)(83380400001)(5660300002)(316002)(336012)(956004)(2616005)(16526019)(2906002);DIR:OUT;SFP:1101; X-OriginatorOrg: siemens.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Sep 2022 12:08:05.6889 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7ddf7de0-6d6c-4b8c-2f89-08da97dc1cc8 X-MS-Exchange-CrossTenant-Id: 38ae3bcd-9579-4fd4-adda-b42e1495d55a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=38ae3bcd-9579-4fd4-adda-b42e1495d55a;Ip=[194.138.21.74];Helo=[hybrid.siemens.com] X-MS-Exchange-CrossTenant-AuthSource: HE1EUR01FT063.eop-EUR01.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR10MB3652 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Benedikt Niedermayr Currently it is not possible to configure the WAIT0PINPOLARITY and WAIT1PINPOLARITY bits of the GPMC_CONFIG register directly via device tree properties. It is also not possible to use the same wait-pin for different cs-regions. While the current implementation may fullfill most usecases, it may not be sufficient for more complex setups (e.g. FPGA/ASIC interfaces), where more complex interfacing options where possible. For example interfacing an ASIC which offers multiple cs-regions but only one waitpin the current driver and dt-bindings are not sufficient. While using the same waitpin for different cs-regions worked for older kernels (4.14) the omap-gpmc.c driver refused to probe (-EBUSY) with newer kernels (>5.10). Changes since v1: * Rebase against recent 6.0.0-rc3 kernel, but the maintainers list stays the same! * Updated eMail recipients list Changes since v2: * Remove the gpmc register configuration out of the gpiochip callbacks. In this case the memory interface configuration is not done via gpio bindings. * Some minor code fixes * Changed git commit descriptions Change since v3: * Use a uint32 dt-property instean a boolean one * If the dt-property is not set, then don't touch the GPMC_CONFIG register * Changed git commit descriptions Changes since v4: * Use checkpatch with "--strict" option * Moved wait-pin sanity checks to gpmc_read_settings_dt() * Always assign WAITPINPOLARITY_DEFAULT on error cases * Track waitpin allocation within gpmc for determine allocation origin Benedikt Niedermayr (3): memory: omap-gpmc: allow shared wait pins memory: omap-gpmc: add support for wait pin polarity dt-bindings: memory-controllers: gpmc-child: add wait-pin polarity .../memory-controllers/ti,gpmc-child.yaml | 7 ++++ drivers/memory/omap-gpmc.c | 39 ++++++++++++++++++- include/linux/platform_data/gpmc-omap.h | 6 +++ 3 files changed, 50 insertions(+), 2 deletions(-) -- 2.34.1