From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D51DEECAAD3 for ; Mon, 19 Sep 2022 19:42:08 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 1E15084C4E; Mon, 19 Sep 2022 21:41:45 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1663616505; bh=AhN6mPptBY7yxm0QQNT+LMjxDwIcJlGiNu7MtqOwbLU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=VQjekAClfKaJQdBXAe/QrWcSp5JkAd+qmyYxCwEqjcnRsI7jXaTQGPlr7XfRmT2EF dIcqcesLfS0XvPvHrCkXbVLiQQ43Hngfl4OqZV0LSHuNJpAO/8axRmhSc3HIu1WVm9 R0d65yyHbj9rYr+yGpLXHrLBtXs89e50Dugege/m8hVB0voBDIGeLiXJvn53+0qQS+ kJaSKIZC2BINP3t3aFriB8HdxIx7VDtoRnfBv8PrC5q8RurI9PQSBkIRbJ3BIFM//Y iAp3uKe32zxgftHuoxBJ+JrFI+FMT0RKRHBUH2vUAw31dYKgUX4qMbuop7nT1i54OK KkR97dkisRRIg== Received: from tr.lan (ip-86-49-12-201.bb.vodafone.cz [86.49.12.201]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 659EE84C3B; Mon, 19 Sep 2022 21:41:37 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1663616497; bh=AhN6mPptBY7yxm0QQNT+LMjxDwIcJlGiNu7MtqOwbLU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Dg66s3FDnQaFuI/km4rH87Yhcvfe1A+vLd5wO6ef8t3rxlH68MFKFTat/2uFF+E23 PbnbHfcnCdPWR3LwmiMgA3xJvTXXSwLudrcRsEJYoGxXPnjVzu1BPTyu0UhJd6Vl/Y 0tZjZlJ38qAIrN+9EKBoryVT3LDDnExQyQW106q0JFsX5zdSn9v/LLCAVF6m+n/b1/ TyxLu+vCmzIvIW680F4DZrHd44jwC/yjBrs1oAKPESHIVLo0dpeiTZk19wQNSHgCUb j9h3kcqUx0Gp3JLaavEW2Vo059E2lFO8hWzGGjf+BQRhVGgTC+gR+YmbJGzHJ7D0fH Smhm9EQEWUKBg== From: Marek Vasut To: u-boot@lists.denx.de Cc: Marek Vasut , Fabio Estevam , Marcel Ziswiler , Max Krummenacher , Peng Fan , Stefano Babic Subject: [PATCH 4/4] ARM: dts: imx8m: imx8mm-mx8menlo: Enable SPL SDP support Date: Mon, 19 Sep 2022 21:41:18 +0200 Message-Id: <20220919194118.105820-4-marex@denx.de> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220919194118.105820-1-marex@denx.de> References: <20220919194118.105820-1-marex@denx.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Enable DM USB, DM PHY and USB gadget support in imx8mm-mx8menlo SPL to let the board continue SDP loading of second stage after the first stage was loaded by BootROM SDP implementation. It is not possible to jump back into BootROM v1 and let the BootROM implementation continue the SDP loading, all this has to be performed by the U-Boot CI HDRC controller driver and SDP protocol implementation, both of which fit into the SPL just barely. With this patch, it is possible to start both U-Boot SPL and U-Boot using e.g. uuu on this board as follows: $ uuu -brun spl flash.bin Signed-off-by: Marek Vasut --- Cc: Fabio Estevam Cc: Marcel Ziswiler Cc: Max Krummenacher Cc: Peng Fan Cc: Stefano Babic --- arch/arm/dts/imx8mm-mx8menlo-u-boot.dtsi | 20 ++++++++++++++++++++ configs/imx8mm-mx8menlo_defconfig | 17 ++++++++++++++++- 2 files changed, 36 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/imx8mm-mx8menlo-u-boot.dtsi b/arch/arm/dts/imx8mm-mx8menlo-u-boot.dtsi index 484d493e33c..7f5f8c384e8 100644 --- a/arch/arm/dts/imx8mm-mx8menlo-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-mx8menlo-u-boot.dtsi @@ -17,6 +17,26 @@ }; }; +&aips4 { + u-boot,dm-spl; +}; + &i2c4 { /delete-node/ codec@1a; }; + +®_usb_otg1_vbus { + u-boot,dm-spl; +}; + +&usbmisc1 { + u-boot,dm-spl; +}; + +&usbphynop1 { + u-boot,dm-spl; +}; + +&usbotg1 { + u-boot,dm-spl; +}; diff --git a/configs/imx8mm-mx8menlo_defconfig b/configs/imx8mm-mx8menlo_defconfig index 929ff382f27..ad6885942d3 100644 --- a/configs/imx8mm-mx8menlo_defconfig +++ b/configs/imx8mm-mx8menlo_defconfig @@ -50,6 +50,9 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y +CONFIG_SPL_USB_HOST=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_SPL_WATCHDOG=y CONFIG_SYS_MAXARGS=64 CONFIG_SYS_CBSIZE=2048 @@ -65,6 +68,8 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_BOOTCOUNT=y CONFIG_CMD_CACHE=y CONFIG_CMD_UUID=y @@ -106,6 +111,8 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_FEC_MXC=y CONFIG_MII=y +CONFIG_SPL_PHY=y +CONFIG_SPL_NOP_PHY=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y @@ -125,7 +132,15 @@ CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y CONFIG_USB=y -# CONFIG_SPL_DM_USB is not set CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +# CONFIG_USB_STORAGE is not set +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Menlo" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_SDP_LOADADDR=0x40400000 +CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_IMX_WATCHDOG=y CONFIG_OF_LIBFDT_OVERLAY=y -- 2.35.1