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From: Jasdeep Dhillon <jdhillon@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: stylon.wang@amd.com, Aric Cyr <aric.cyr@amd.com>,
	Jaehyun Chung <jaehyun.chung@amd.com>,
	Sunpeng.Li@amd.com, Harry.Wentland@amd.com,
	qingqing.zhuo@amd.com, Jasdeep Dhillon <jdhillon@amd.com>,
	Rodrigo.Siqueira@amd.com, roman.li@amd.com, solomon.chiu@amd.com,
	Aurabindo.Pillai@amd.com, wayne.lin@amd.com,
	Bhawanpreet.Lakha@amd.com, agustin.gutierrez@amd.com,
	pavle.kotarac@amd.com
Subject: [PATCH 04/31] drm/amd/display: Remove interface for periodic interrupt 1
Date: Wed, 21 Sep 2022 20:17:54 -0400	[thread overview]
Message-ID: <20220922001821.320255-5-jdhillon@amd.com> (raw)
In-Reply-To: <20220922001821.320255-1-jdhillon@amd.com>

From: Aric Cyr <aric.cyr@amd.com>

[why]
Only a single VLINE interrupt is available so interface should not
expose the second one which is used by DMU firmware.

[how]
Remove references to periodic_interrupt1 and VLINE1 from DC interfaces.

Reviewed-by: Jaehyun Chung <jaehyun.chung@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c      | 16 +++------
 drivers/gpu/drm/amd/display/dc/dc_stream.h    |  6 ++--
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 35 ++++++-------------
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.h |  3 +-
 .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |  8 +----
 5 files changed, 18 insertions(+), 50 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 390adc00cd28..d93393cc66c0 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2768,11 +2768,8 @@ static void copy_stream_update_to_stream(struct dc *dc,
 	if (update->abm_level)
 		stream->abm_level = *update->abm_level;
 
-	if (update->periodic_interrupt0)
-		stream->periodic_interrupt0 = *update->periodic_interrupt0;
-
-	if (update->periodic_interrupt1)
-		stream->periodic_interrupt1 = *update->periodic_interrupt1;
+	if (update->periodic_interrupt)
+		stream->periodic_interrupt = *update->periodic_interrupt;
 
 	if (update->gamut_remap)
 		stream->gamut_remap_matrix = *update->gamut_remap;
@@ -2992,13 +2989,8 @@ static void commit_planes_do_stream_update(struct dc *dc,
 
 		if (!pipe_ctx->top_pipe &&  !pipe_ctx->prev_odm_pipe && pipe_ctx->stream == stream) {
 
-			if (stream_update->periodic_interrupt0 &&
-					dc->hwss.setup_periodic_interrupt)
-				dc->hwss.setup_periodic_interrupt(dc, pipe_ctx, VLINE0);
-
-			if (stream_update->periodic_interrupt1 &&
-					dc->hwss.setup_periodic_interrupt)
-				dc->hwss.setup_periodic_interrupt(dc, pipe_ctx, VLINE1);
+			if (stream_update->periodic_interrupt && dc->hwss.setup_periodic_interrupt)
+				dc->hwss.setup_periodic_interrupt(dc, pipe_ctx);
 
 			if ((stream_update->hdr_static_metadata && !stream->use_dynamic_meta) ||
 					stream_update->vrr_infopacket ||
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index 9fcf9dc5bce4..9e6025c98db9 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -212,8 +212,7 @@ struct dc_stream_state {
 	/* DMCU info */
 	unsigned int abm_level;
 
-	struct periodic_interrupt_config periodic_interrupt0;
-	struct periodic_interrupt_config periodic_interrupt1;
+	struct periodic_interrupt_config periodic_interrupt;
 
 	/* from core_stream struct */
 	struct dc_context *ctx;
@@ -281,8 +280,7 @@ struct dc_stream_update {
 	struct dc_info_packet *hdr_static_metadata;
 	unsigned int *abm_level;
 
-	struct periodic_interrupt_config *periodic_interrupt0;
-	struct periodic_interrupt_config *periodic_interrupt1;
+	struct periodic_interrupt_config *periodic_interrupt;
 
 	struct dc_info_packet *vrr_infopacket;
 	struct dc_info_packet *vsc_infopacket;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 287fdecc0b10..72521749c01d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -3812,7 +3812,7 @@ void dcn10_calc_vupdate_position(
 {
 	const struct dc_crtc_timing *dc_crtc_timing = &pipe_ctx->stream->timing;
 	int vline_int_offset_from_vupdate =
-			pipe_ctx->stream->periodic_interrupt0.lines_offset;
+			pipe_ctx->stream->periodic_interrupt.lines_offset;
 	int vupdate_offset_from_vsync = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);
 	int start_position;
 
@@ -3837,18 +3837,10 @@ void dcn10_calc_vupdate_position(
 static void dcn10_cal_vline_position(
 		struct dc *dc,
 		struct pipe_ctx *pipe_ctx,
-		enum vline_select vline,
 		uint32_t *start_line,
 		uint32_t *end_line)
 {
-	enum vertical_interrupt_ref_point ref_point = INVALID_POINT;
-
-	if (vline == VLINE0)
-		ref_point = pipe_ctx->stream->periodic_interrupt0.ref_point;
-	else if (vline == VLINE1)
-		ref_point = pipe_ctx->stream->periodic_interrupt1.ref_point;
-
-	switch (ref_point) {
+	switch (pipe_ctx->stream->periodic_interrupt.ref_point) {
 	case START_V_UPDATE:
 		dcn10_calc_vupdate_position(
 				dc,
@@ -3857,7 +3849,9 @@ static void dcn10_cal_vline_position(
 				end_line);
 		break;
 	case START_V_SYNC:
-		// Suppose to do nothing because vsync is 0;
+		// vsync is line 0 so start_line is just the requested line offset
+		*start_line = pipe_ctx->stream->periodic_interrupt.lines_offset;
+		*end_line = *start_line + 2;
 		break;
 	default:
 		ASSERT(0);
@@ -3867,24 +3861,15 @@ static void dcn10_cal_vline_position(
 
 void dcn10_setup_periodic_interrupt(
 		struct dc *dc,
-		struct pipe_ctx *pipe_ctx,
-		enum vline_select vline)
+		struct pipe_ctx *pipe_ctx)
 {
 	struct timing_generator *tg = pipe_ctx->stream_res.tg;
+	uint32_t start_line = 0;
+	uint32_t end_line = 0;
 
-	if (vline == VLINE0) {
-		uint32_t start_line = 0;
-		uint32_t end_line = 0;
+	dcn10_cal_vline_position(dc, pipe_ctx, &start_line, &end_line);
 
-		dcn10_cal_vline_position(dc, pipe_ctx, vline, &start_line, &end_line);
-
-		tg->funcs->setup_vertical_interrupt0(tg, start_line, end_line);
-
-	} else if (vline == VLINE1) {
-		pipe_ctx->stream_res.tg->funcs->setup_vertical_interrupt1(
-				tg,
-				pipe_ctx->stream->periodic_interrupt1.lines_offset);
-	}
+	tg->funcs->setup_vertical_interrupt0(tg, start_line, end_line);
 }
 
 void dcn10_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
index 9ae07c77fdc0..0ef7bf7ddb75 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
@@ -175,8 +175,7 @@ void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx);
 void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx);
 void dcn10_setup_periodic_interrupt(
 		struct dc *dc,
-		struct pipe_ctx *pipe_ctx,
-		enum vline_select vline);
+		struct pipe_ctx *pipe_ctx);
 enum dc_status dcn10_set_clock(struct dc *dc,
 		enum dc_clock_type clock_type,
 		uint32_t clk_khz,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 60cbd423c911..d04b68dad413 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -32,11 +32,6 @@
 #include "inc/hw/link_encoder.h"
 #include "core_status.h"
 
-enum vline_select {
-	VLINE0,
-	VLINE1
-};
-
 struct pipe_ctx;
 struct dc_state;
 struct dc_stream_status;
@@ -118,8 +113,7 @@ struct hw_sequencer_funcs {
 			int group_index, int group_size,
 			struct pipe_ctx *grouped_pipes[]);
 	void (*setup_periodic_interrupt)(struct dc *dc,
-			struct pipe_ctx *pipe_ctx,
-			enum vline_select vline);
+			struct pipe_ctx *pipe_ctx);
 	void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes,
 			struct dc_crtc_timing_adjust adjust);
 	void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx,
-- 
2.25.1


  parent reply	other threads:[~2022-09-22  0:18 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-22  0:17 [PATCH 00/31] DC Patches Sept 26, 2022 Jasdeep Dhillon
2022-09-22  0:17 ` [PATCH 01/31] drm/amd/display: Refactor LTTPR mode selection Jasdeep Dhillon
2022-09-22  0:17 ` [PATCH 02/31] drm/amd/display: Update DCN32 to use new SR latencies Jasdeep Dhillon
2022-09-22  0:17 ` [PATCH 03/31] drm/amd/display: Fix various dynamic ODM transitions on DCN32 Jasdeep Dhillon
2022-09-22  0:17 ` Jasdeep Dhillon [this message]
2022-09-22  0:17 ` [PATCH 05/31] drm/amd/display: Avoid avoid unnecessary pixel rate divider programming Jasdeep Dhillon
2022-09-22  0:17 ` [PATCH 06/31] drm/amd/display: Wrap OTG disable workaround with FIFO control Jasdeep Dhillon
2022-09-22  0:17 ` [PATCH 07/31] drm/amd/display: Add explicit FIFO disable for DP blank Jasdeep Dhillon
2022-09-22  0:17 ` [PATCH 08/31] drm/amd/display: Do DIO FIFO enable after DP video stream enable Jasdeep Dhillon
2022-09-22  0:17 ` [PATCH 09/31] drm/amd/display: Change EDID fallback condition Jasdeep Dhillon
2022-09-22  0:18 ` [PATCH 10/31] drm/amd/display: skip phantom pipes when checking for pending flip Jasdeep Dhillon
2022-09-22  0:18 ` [PATCH 11/31] drm/amd/display: fix a divide by zero error Jasdeep Dhillon
2022-09-22  0:18 ` [PATCH 12/31] drm/amd/display: Update MALL SS NumWays calculation Jasdeep Dhillon
2022-09-22  0:18 ` [PATCH 13/31] drm/amd/display: add missing null check Jasdeep Dhillon
2022-09-22  0:18 ` [PATCH 14/31] drm/amd/display: Fix audio on display after unplugging another Jasdeep Dhillon
2022-09-22  0:18 ` [PATCH 15/31] drm/amd/display: add debug keys for override bios settings Jasdeep Dhillon
2022-09-22  0:18 ` [PATCH 16/31] drm/amd/display: Fix typo in get_pixel_rate_div Jasdeep Dhillon
2022-09-22  0:18 ` [PATCH 17/31] drm/amd/display: Disable MALL when TMZ surface Jasdeep Dhillon
2022-09-22  0:18 ` [PATCH 18/31] drm/amd/display: Fix CAB allocation calculation Jasdeep Dhillon
2022-09-22  0:18 ` [PATCH 19/31] drm/amd/display: fill in clock values when DPM is not enabled Jasdeep Dhillon
2022-09-22  0:18 ` [PATCH 20/31] drm/amd/display: polling vid stream status in hpo dp blank Jasdeep Dhillon
2022-09-22  0:18 ` [PATCH 21/31] Add ABM control to panel_config struct Jasdeep Dhillon
2022-09-22 14:12   ` Pillai, Aurabindo
2022-09-22  0:18 ` [PATCH 22/31] drm/amd/display: Avoid unnecessary pixel rate divider programming Jasdeep Dhillon
2022-09-22  0:18 ` [PATCH 23/31] Add debug option for exiting idle optimizations on cursor updates Jasdeep Dhillon
2022-09-22 14:13   ` Pillai, Aurabindo
2022-09-22  0:18 ` [PATCH 24/31] drm/amd/display: Cursor Info Update refactor Jasdeep Dhillon
2022-09-22  0:18 ` [PATCH 25/31] drm/amd/display: Remove assert for odm transition case Jasdeep Dhillon
2022-09-22  0:18 ` [PATCH 26/31] drm/amd/display: 3.2.205 Jasdeep Dhillon
2022-09-22  0:18 ` [PATCH 27/31] drm/amd/display: Reduce number of arguments of dml314's CalculateWatermarksAndDRAMSpeedChangeSupport() Jasdeep Dhillon
2022-09-22  0:18 ` [PATCH 28/31] drm/amd/display: Reduce number of arguments of dml314's CalculateFlipSchedule() Jasdeep Dhillon
2022-09-22  0:18 ` [PATCH 29/31] drm/amd/display: remove redundant CalculateTWait's Jasdeep Dhillon
2022-09-22  0:18 ` [PATCH 30/31] drm/amd/display: refactor CalculateWriteBackDelay to use vba_vars_st ptr Jasdeep Dhillon
2022-09-22  0:18 ` [PATCH 31/31] drm/amd/display: remove redundant CalculateRemoteSurfaceFlipDelay's Jasdeep Dhillon
2022-09-23 15:44 ` [PATCH 00/31] DC Patches Sept 26, 2022 Wheeler, Daniel
  -- strict thread matches above, loose matches on Subject: below --
2022-09-21 23:16 [PATCH 00/31] DC Patches Sept 20, 2022 Jasdeep Dhillon
2022-09-21 23:16 ` [PATCH 04/31] drm/amd/display: Remove interface for periodic interrupt 1 Jasdeep Dhillon

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