From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7F76EECAAD8 for ; Thu, 22 Sep 2022 03:32:05 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id D06E284BCE; Thu, 22 Sep 2022 05:31:51 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="gDq02p6W"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 0A53684B3E; Thu, 22 Sep 2022 05:31:51 +0200 (CEST) Received: from mail-pf1-x429.google.com (mail-pf1-x429.google.com [IPv6:2607:f8b0:4864:20::429]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id D76ED84CAA for ; Thu, 22 Sep 2022 05:31:47 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=judge.packham@gmail.com Received: by mail-pf1-x429.google.com with SMTP id l65so7974753pfl.8 for ; Wed, 21 Sep 2022 20:31:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=QFR0QHmbFLYe0smzIr8F8m2asRsdmd6VtWa7AmQopoM=; b=gDq02p6WJPbWnTGzAHHUWP07b0+mKBjlLAmb8VbDJ/USFDhXAmYKzP+uIhe8d4/Z0I 9/oHo77x7chV66oqvCoQoOFFtYragbQADENYPUIexsQZH9dTwGT53apM2v/FMWFiqNqw 5gSX/MMSoYUjgB+P6d4pUqjkVF3fNcQUubtyfFHmrus9rFlO/pBbSjJy9NSNAafIPg3Z 9pdPDNESSDFcEA14S4c0P6kg3yCHbMy2uet7SRsenN5UiibZKyr3Q2rEV1XWUjQPY8SN sseU7+Pm8wb4J8eKk01Uktmom/xGSCIlqjpPGQs9MVtXEvRtCCOzsZGUQJ0rCx/LMIXz EFZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=QFR0QHmbFLYe0smzIr8F8m2asRsdmd6VtWa7AmQopoM=; b=a1YvHc/5lOOhQZw7xO6e/enY8UqFFk6FSGV48gg3F3vYYgPQrY2N5hFtZ7WYa708Xe 5v7OagyqpeT/aSCkUH6Bac7sdBjS82xf8qmvUA+f/qmYntWrnkbrl+ewmjjxjAaBwBjH Cwpcy4k7xCc6WfX5v7+bqW5PKdkgrs8yplK+YlspAiSAYZYNzkMJ5BkxbK+kbchTYaCz E0IW27Se3CH0UMOO9EiEhne3RgNAOnHG50bdpB5+EVxj+7P/mc5IYPEktS8C2xvWyUxK sTZCjRdGjjSaKRz4fNI49q4hgN/sUa+9m51/9b+nuwQMQzgNZvSsZKBx3lcmcgcJ/brI ohpw== X-Gm-Message-State: ACrzQf3BhoF/VcDNT21XBzhCcroYRSjw29QcAOAe5ZzXAY72Dqps4iYk Luvm5JaaxOHY/pIf/YwzCKg= X-Google-Smtp-Source: AMsMyM7bPhYF1zT2Z1kH6kvR4nro2hRtKUwsbuYinNTp1uUTZLID9T5BHpGfF0xv0HP0Y+UJ94QVyw== X-Received: by 2002:aa7:9e0d:0:b0:540:94a7:9051 with SMTP id y13-20020aa79e0d000000b0054094a79051mr1567236pfq.59.1663817506107; Wed, 21 Sep 2022 20:31:46 -0700 (PDT) Received: from chrisp-dl.atlnz.lc ([2001:df5:b000:22:6e20:c7c5:8cff:c796]) by smtp.gmail.com with ESMTPSA id a5-20020aa795a5000000b0054095e1b2e5sm2977444pfk.215.2022.09.21.20.31.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Sep 2022 20:31:45 -0700 (PDT) From: Chris Packham To: Stefan Roese Cc: Elad Nachman , Vadym Kochan , Chris Packham , Adam Ford , Lukasz Majewski , =?UTF-8?q?Marek=20Beh=C3=BAn?= , Marek Vasut , =?UTF-8?q?Pali=20Roh=C3=A1r?= , Weijie Gao , u-boot@lists.denx.de Subject: [PATCH v4 2/5] usb: ehci: ehci-marvell: Support for marvell,ac5-ehci Date: Thu, 22 Sep 2022 15:31:13 +1200 Message-Id: <20220922033116.915635-3-judge.packham@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220922033116.915635-1-judge.packham@gmail.com> References: <20220922033116.915635-1-judge.packham@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Unlike the other 64-bit mvebu SoCs the AlleyCat5 uses the older ehci block from the 32-bit SoCs. Adapt the ehci-marvell.c driver to cope with the fact that the ac5 does not have the mbus infrastructure the 32-bit SoCs have and ensure USB_EHCI_IS_TDI is selected. Signed-off-by: Chris Packham --- (no changes since v1) drivers/usb/host/Kconfig | 1 + drivers/usb/host/ehci-marvell.c | 57 +++++++++++++++++++++++++++------ 2 files changed, 48 insertions(+), 10 deletions(-) diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index a0f48f09a7..628078f495 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -178,6 +178,7 @@ config USB_EHCI_MARVELL depends on ARCH_MVEBU || ARCH_KIRKWOOD || ARCH_ORION5X default y select USB_EHCI_IS_TDI if !ARM64 + select USB_EHCI_IS_TDI if ALLEYCAT_5 ---help--- Enables support for the on-chip EHCI controller on MVEBU SoCs. diff --git a/drivers/usb/host/ehci-marvell.c b/drivers/usb/host/ehci-marvell.c index b7e60c690a..7d859b9cce 100644 --- a/drivers/usb/host/ehci-marvell.c +++ b/drivers/usb/host/ehci-marvell.c @@ -48,12 +48,17 @@ struct ehci_mvebu_priv { fdt_addr_t hcd_base; }; +#define USB_TO_DRAM_TARGET_ID 0x2 +#define USB_TO_DRAM_ATTR_ID 0x0 +#define USB_DRAM_BASE 0x00000000 +#define USB_DRAM_SIZE 0xfff /* don't overrun u-boot source (was 0xffff) */ + /* * Once all the older Marvell SoC's (Orion, Kirkwood) are converted * to the common mvebu archticture including the mbus setup, this * will be the only function needed to configure the access windows */ -static void usb_brg_adrdec_setup(void *base) +static void usb_brg_adrdec_setup(struct udevice *dev, void *base) { const struct mbus_dram_target_info *dram; int i; @@ -65,16 +70,34 @@ static void usb_brg_adrdec_setup(void *base) writel(0, base + USB_WINDOW_BASE(i)); } - for (i = 0; i < dram->num_cs; i++) { - const struct mbus_dram_window *cs = dram->cs + i; + if (device_is_compatible(dev, "marvell,ac5-ehci")) { + /* + * use decoding window to map dram address seen by usb to 0x0 + */ /* Write size, attributes and target id to control register */ - writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) | - (dram->mbus_dram_target_id << 4) | 1, - base + USB_WINDOW_CTRL(i)); + writel((USB_DRAM_SIZE << 16) | (USB_TO_DRAM_ATTR_ID << 8) | + (USB_TO_DRAM_TARGET_ID << 4) | 1, + base + USB_WINDOW_CTRL(0)); /* Write base address to base register */ - writel(cs->base, base + USB_WINDOW_BASE(i)); + writel(USB_DRAM_BASE, base + USB_WINDOW_BASE(0)); + + debug("## AC5 decoding windows, ctrl[%p]=0x%x, base[%p]=0x%x\n", + base + USB_WINDOW_CTRL(0), readl(base + USB_WINDOW_CTRL(0)), + base + USB_WINDOW_BASE(0), readl(base + USB_WINDOW_BASE(0))); + } else { + for (i = 0; i < dram->num_cs; i++) { + const struct mbus_dram_window *cs = dram->cs + i; + + /* Write size, attributes and target id to control register */ + writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) | + (dram->mbus_dram_target_id << 4) | 1, + base + USB_WINDOW_CTRL(i)); + + /* Write base address to base register */ + writel(cs->base, base + USB_WINDOW_BASE(i)); + } } } @@ -126,15 +149,28 @@ static int ehci_mvebu_probe(struct udevice *dev) if (device_is_compatible(dev, "marvell,armada-3700-ehci")) marvell_ehci_ops.powerup_fixup = marvell_ehci_powerup_fixup; else - usb_brg_adrdec_setup((void *)priv->hcd_base); + usb_brg_adrdec_setup(dev, (void *)priv->hcd_base); hccr = (struct ehci_hccr *)(priv->hcd_base + 0x100); hcor = (struct ehci_hcor *) ((uintptr_t)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); debug("ehci-marvell: init hccr %lx and hcor %lx hc_length %ld\n", - (uintptr_t)hccr, (uintptr_t)hcor, - (uintptr_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase))); + (uintptr_t)hccr, (uintptr_t)hcor, + (uintptr_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase))); + +#define PHY_CALIB_OFFSET 0x808 + /* + * Trigger calibration during each usb start/reset: + * BIT 13 to 0, and then to 1 + */ + if (device_is_compatible(dev, "marvell,ac5-ehci")) { + void *phy_calib_reg = (void *)(priv->hcd_base + PHY_CALIB_OFFSET); + u32 val = readl(phy_calib_reg) & (~BIT(13)); + + writel(val, phy_calib_reg); + writel(val | BIT(13), phy_calib_reg); + } return ehci_register(dev, hccr, hcor, &marvell_ehci_ops, 0, USB_INIT_HOST); @@ -143,6 +179,7 @@ static int ehci_mvebu_probe(struct udevice *dev) static const struct udevice_id ehci_usb_ids[] = { { .compatible = "marvell,orion-ehci", }, { .compatible = "marvell,armada-3700-ehci", }, + { .compatible = "marvell,ac5-ehci", }, { } }; -- 2.37.3