From: Aristeu Rozanski <aris@redhat.com>
To: Borislav Petkov <bp@alien8.de>
Cc: linux-edac@vger.kernel.org, mchehab@kernel.org
Subject: Re: [RESEND PATCH] i5000_edac: fix slot number passed to determine_mtr()
Date: Thu, 22 Sep 2022 09:46:59 -0400 [thread overview]
Message-ID: <20220922134659.biiy6g743qplzgiq@redhat.com> (raw)
In-Reply-To: <YytoHtVULW7w3/8Z@zn.tnic>
On Wed, Sep 21, 2022 at 09:38:06PM +0200, Borislav Petkov wrote:
> So it looks to me like back then, the number of CS rows was twice the
> DIMMs per channel, implying two CS rows per DIMM, I guess dual-ranked
> DIMMs or so.
>
> Now you're saying the number CS rows is the number of DIMMs. Which
> means, single-ranked DIMMs?
I'm only fixing a out of bounds access, on purpose.
Look at 64e1fdaf55d6 and the new version of determine_mtr().
> But all this is broken as it needs to deal with both single-ranked and
> dual-ranked DIMMs elegantly and not assume any DIMM types...
That's correct, while talking to Mauro he suggested fixing the entire
thing.
> Do we have hardware where we can test this or can we declare this hw for
> dead?
And this is the reason why I decided to not do it. We do have the hardware
but last time I checked none of them had functional EINJ.
--
Aristeu
next prev parent reply other threads:[~2022-09-22 13:48 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-21 18:10 [RESEND PATCH] i5000_edac: fix slot number passed to determine_mtr() Aristeu Rozanski
2022-09-21 19:38 ` Borislav Petkov
2022-09-22 13:46 ` Aristeu Rozanski [this message]
2022-09-22 13:55 ` Borislav Petkov
2022-09-26 16:51 ` Aristeu Rozanski
2022-09-26 18:02 ` Borislav Petkov
2022-09-28 12:48 ` [PATCH] i5000_edac: mark as BROKEN Aristeu Rozanski
2022-10-17 14:41 ` Borislav Petkov
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