* [PATCH] dt-bindings: iommu: arm,smmu-v3: Relax order of interrupt names
@ 2022-09-16 13:31 ` Jean-Philippe Brucker
0 siblings, 0 replies; 8+ messages in thread
From: Jean-Philippe Brucker @ 2022-09-16 13:31 UTC (permalink / raw)
To: will, robin.murphy
Cc: robh+dt, krzysztof.kozlowski+dt, linux-arm-kernel, iommu,
devicetree, linux-kernel, Jean-Philippe Brucker
The QEMU devicetree uses a different order for SMMUv3 interrupt names,
and there isn't a good reason for enforcing a specific order. Since all
interrupt lines are optional, operating systems should not expect a
fixed interrupt array layout; they should instead match each interrupt
to its name individually. Besides, as a result of commit e4783856a2e8
("dt-bindings: iommu: arm,smmu-v3: make PRI IRQ optional"), "cmdq-sync"
and "priq" are already permutable. Relax the interrupt-names array
entirely by allowing any permutation, incidentally making the schema
more readable.
Note that dt-validate won't allow duplicate names here so we don't need
to specify maxItems or add additional checks, it's quite neat.
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
---
.../devicetree/bindings/iommu/arm,smmu-v3.yaml | 15 +++++----------
1 file changed, 5 insertions(+), 10 deletions(-)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
index c57a53d87e4e..75fcf4cb52d9 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
@@ -39,16 +39,11 @@ properties:
any others.
- minItems: 1
items:
- - enum:
- - eventq # Event Queue not empty
- - gerror # Global Error activated
- - const: gerror
- - enum:
- - cmdq-sync # CMD_SYNC complete
- - priq # PRI Queue not empty
- - enum:
- - cmdq-sync
- - priq
+ enum:
+ - eventq # Event Queue not empty
+ - gerror # Global Error activated
+ - cmdq-sync # CMD_SYNC complete
+ - priq # PRI Queue not empty
'#iommu-cells':
const: 1
--
2.37.3
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH] dt-bindings: iommu: arm,smmu-v3: Relax order of interrupt names
@ 2022-09-16 13:31 ` Jean-Philippe Brucker
0 siblings, 0 replies; 8+ messages in thread
From: Jean-Philippe Brucker @ 2022-09-16 13:31 UTC (permalink / raw)
To: will, robin.murphy
Cc: robh+dt, krzysztof.kozlowski+dt, linux-arm-kernel, iommu,
devicetree, linux-kernel, Jean-Philippe Brucker
The QEMU devicetree uses a different order for SMMUv3 interrupt names,
and there isn't a good reason for enforcing a specific order. Since all
interrupt lines are optional, operating systems should not expect a
fixed interrupt array layout; they should instead match each interrupt
to its name individually. Besides, as a result of commit e4783856a2e8
("dt-bindings: iommu: arm,smmu-v3: make PRI IRQ optional"), "cmdq-sync"
and "priq" are already permutable. Relax the interrupt-names array
entirely by allowing any permutation, incidentally making the schema
more readable.
Note that dt-validate won't allow duplicate names here so we don't need
to specify maxItems or add additional checks, it's quite neat.
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
---
.../devicetree/bindings/iommu/arm,smmu-v3.yaml | 15 +++++----------
1 file changed, 5 insertions(+), 10 deletions(-)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
index c57a53d87e4e..75fcf4cb52d9 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
@@ -39,16 +39,11 @@ properties:
any others.
- minItems: 1
items:
- - enum:
- - eventq # Event Queue not empty
- - gerror # Global Error activated
- - const: gerror
- - enum:
- - cmdq-sync # CMD_SYNC complete
- - priq # PRI Queue not empty
- - enum:
- - cmdq-sync
- - priq
+ enum:
+ - eventq # Event Queue not empty
+ - gerror # Global Error activated
+ - cmdq-sync # CMD_SYNC complete
+ - priq # PRI Queue not empty
'#iommu-cells':
const: 1
--
2.37.3
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH] dt-bindings: iommu: arm,smmu-v3: Relax order of interrupt names
2022-09-16 13:31 ` Jean-Philippe Brucker
@ 2022-09-22 12:54 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 8+ messages in thread
From: Krzysztof Kozlowski @ 2022-09-22 12:54 UTC (permalink / raw)
To: Jean-Philippe Brucker, will, robin.murphy
Cc: robh+dt, krzysztof.kozlowski+dt, linux-arm-kernel, iommu,
devicetree, linux-kernel
On 16/09/2022 15:31, Jean-Philippe Brucker wrote:
> The QEMU devicetree uses a different order for SMMUv3 interrupt names,
> and there isn't a good reason for enforcing a specific order. Since all
> interrupt lines are optional, operating systems should not expect a
> fixed interrupt array layout; they should instead match each interrupt
> to its name individually. Besides, as a result of commit e4783856a2e8
> ("dt-bindings: iommu: arm,smmu-v3: make PRI IRQ optional"), "cmdq-sync"
> and "priq" are already permutable. Relax the interrupt-names array
> entirely by allowing any permutation, incidentally making the schema
> more readable.
>
> Note that dt-validate won't allow duplicate names here so we don't need
> to specify maxItems or add additional checks, it's quite neat.
Nice explanation, much appriecated!
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] dt-bindings: iommu: arm,smmu-v3: Relax order of interrupt names
@ 2022-09-22 12:54 ` Krzysztof Kozlowski
0 siblings, 0 replies; 8+ messages in thread
From: Krzysztof Kozlowski @ 2022-09-22 12:54 UTC (permalink / raw)
To: Jean-Philippe Brucker, will, robin.murphy
Cc: robh+dt, krzysztof.kozlowski+dt, linux-arm-kernel, iommu,
devicetree, linux-kernel
On 16/09/2022 15:31, Jean-Philippe Brucker wrote:
> The QEMU devicetree uses a different order for SMMUv3 interrupt names,
> and there isn't a good reason for enforcing a specific order. Since all
> interrupt lines are optional, operating systems should not expect a
> fixed interrupt array layout; they should instead match each interrupt
> to its name individually. Besides, as a result of commit e4783856a2e8
> ("dt-bindings: iommu: arm,smmu-v3: make PRI IRQ optional"), "cmdq-sync"
> and "priq" are already permutable. Relax the interrupt-names array
> entirely by allowing any permutation, incidentally making the schema
> more readable.
>
> Note that dt-validate won't allow duplicate names here so we don't need
> to specify maxItems or add additional checks, it's quite neat.
Nice explanation, much appriecated!
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] dt-bindings: iommu: arm,smmu-v3: Relax order of interrupt names
2022-09-16 13:31 ` Jean-Philippe Brucker
@ 2022-09-22 21:08 ` Will Deacon
-1 siblings, 0 replies; 8+ messages in thread
From: Will Deacon @ 2022-09-22 21:08 UTC (permalink / raw)
To: Jean-Philippe Brucker, joro
Cc: robin.murphy, robh+dt, krzysztof.kozlowski+dt, linux-arm-kernel,
iommu, devicetree, linux-kernel
On Fri, Sep 16, 2022 at 02:31:47PM +0100, Jean-Philippe Brucker wrote:
> The QEMU devicetree uses a different order for SMMUv3 interrupt names,
> and there isn't a good reason for enforcing a specific order. Since all
> interrupt lines are optional, operating systems should not expect a
> fixed interrupt array layout; they should instead match each interrupt
> to its name individually. Besides, as a result of commit e4783856a2e8
> ("dt-bindings: iommu: arm,smmu-v3: make PRI IRQ optional"), "cmdq-sync"
> and "priq" are already permutable. Relax the interrupt-names array
> entirely by allowing any permutation, incidentally making the schema
> more readable.
>
> Note that dt-validate won't allow duplicate names here so we don't need
> to specify maxItems or add additional checks, it's quite neat.
>
> Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
> ---
> .../devicetree/bindings/iommu/arm,smmu-v3.yaml | 15 +++++----------
> 1 file changed, 5 insertions(+), 10 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
> index c57a53d87e4e..75fcf4cb52d9 100644
> --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
> @@ -39,16 +39,11 @@ properties:
> any others.
> - minItems: 1
> items:
> - - enum:
> - - eventq # Event Queue not empty
> - - gerror # Global Error activated
> - - const: gerror
> - - enum:
> - - cmdq-sync # CMD_SYNC complete
> - - priq # PRI Queue not empty
> - - enum:
> - - cmdq-sync
> - - priq
> + enum:
> + - eventq # Event Queue not empty
> + - gerror # Global Error activated
> + - cmdq-sync # CMD_SYNC complete
> + - priq # PRI Queue not empty
>
> '#iommu-cells':
> const: 1
Acked-by: Will Deacon <will@kernel.org>
Joerg -- please can you take this one directly for 6.1? I don't actually
have any other SMMU patches queued, so it doesn't seem worth sending a pull
request just for this.
Cheers,
Will
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] dt-bindings: iommu: arm,smmu-v3: Relax order of interrupt names
@ 2022-09-22 21:08 ` Will Deacon
0 siblings, 0 replies; 8+ messages in thread
From: Will Deacon @ 2022-09-22 21:08 UTC (permalink / raw)
To: Jean-Philippe Brucker, joro
Cc: robin.murphy, robh+dt, krzysztof.kozlowski+dt, linux-arm-kernel,
iommu, devicetree, linux-kernel
On Fri, Sep 16, 2022 at 02:31:47PM +0100, Jean-Philippe Brucker wrote:
> The QEMU devicetree uses a different order for SMMUv3 interrupt names,
> and there isn't a good reason for enforcing a specific order. Since all
> interrupt lines are optional, operating systems should not expect a
> fixed interrupt array layout; they should instead match each interrupt
> to its name individually. Besides, as a result of commit e4783856a2e8
> ("dt-bindings: iommu: arm,smmu-v3: make PRI IRQ optional"), "cmdq-sync"
> and "priq" are already permutable. Relax the interrupt-names array
> entirely by allowing any permutation, incidentally making the schema
> more readable.
>
> Note that dt-validate won't allow duplicate names here so we don't need
> to specify maxItems or add additional checks, it's quite neat.
>
> Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
> ---
> .../devicetree/bindings/iommu/arm,smmu-v3.yaml | 15 +++++----------
> 1 file changed, 5 insertions(+), 10 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
> index c57a53d87e4e..75fcf4cb52d9 100644
> --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
> @@ -39,16 +39,11 @@ properties:
> any others.
> - minItems: 1
> items:
> - - enum:
> - - eventq # Event Queue not empty
> - - gerror # Global Error activated
> - - const: gerror
> - - enum:
> - - cmdq-sync # CMD_SYNC complete
> - - priq # PRI Queue not empty
> - - enum:
> - - cmdq-sync
> - - priq
> + enum:
> + - eventq # Event Queue not empty
> + - gerror # Global Error activated
> + - cmdq-sync # CMD_SYNC complete
> + - priq # PRI Queue not empty
>
> '#iommu-cells':
> const: 1
Acked-by: Will Deacon <will@kernel.org>
Joerg -- please can you take this one directly for 6.1? I don't actually
have any other SMMU patches queued, so it doesn't seem worth sending a pull
request just for this.
Cheers,
Will
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] dt-bindings: iommu: arm,smmu-v3: Relax order of interrupt names
2022-09-22 21:08 ` Will Deacon
@ 2022-09-26 12:06 ` Joerg Roedel
-1 siblings, 0 replies; 8+ messages in thread
From: Joerg Roedel @ 2022-09-26 12:06 UTC (permalink / raw)
To: Will Deacon
Cc: Jean-Philippe Brucker, robin.murphy, robh+dt,
krzysztof.kozlowski+dt, linux-arm-kernel, iommu, devicetree,
linux-kernel
On Thu, Sep 22, 2022 at 10:08:56PM +0100, Will Deacon wrote:
> Acked-by: Will Deacon <will@kernel.org>
>
> Joerg -- please can you take this one directly for 6.1? I don't actually
> have any other SMMU patches queued, so it doesn't seem worth sending a pull
> request just for this.
Applied, thanks.
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] dt-bindings: iommu: arm,smmu-v3: Relax order of interrupt names
@ 2022-09-26 12:06 ` Joerg Roedel
0 siblings, 0 replies; 8+ messages in thread
From: Joerg Roedel @ 2022-09-26 12:06 UTC (permalink / raw)
To: Will Deacon
Cc: Jean-Philippe Brucker, robin.murphy, robh+dt,
krzysztof.kozlowski+dt, linux-arm-kernel, iommu, devicetree,
linux-kernel
On Thu, Sep 22, 2022 at 10:08:56PM +0100, Will Deacon wrote:
> Acked-by: Will Deacon <will@kernel.org>
>
> Joerg -- please can you take this one directly for 6.1? I don't actually
> have any other SMMU patches queued, so it doesn't seem worth sending a pull
> request just for this.
Applied, thanks.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2022-09-26 14:06 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-09-16 13:31 [PATCH] dt-bindings: iommu: arm,smmu-v3: Relax order of interrupt names Jean-Philippe Brucker
2022-09-16 13:31 ` Jean-Philippe Brucker
2022-09-22 12:54 ` Krzysztof Kozlowski
2022-09-22 12:54 ` Krzysztof Kozlowski
2022-09-22 21:08 ` Will Deacon
2022-09-22 21:08 ` Will Deacon
2022-09-26 12:06 ` Joerg Roedel
2022-09-26 12:06 ` Joerg Roedel
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