From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C74DDC433FE for ; Mon, 3 Oct 2022 17:32:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230044AbiJCRcZ (ORCPT ); Mon, 3 Oct 2022 13:32:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45656 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229947AbiJCRbz (ORCPT ); Mon, 3 Oct 2022 13:31:55 -0400 Received: from mail-pl1-x62a.google.com (mail-pl1-x62a.google.com [IPv6:2607:f8b0:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1466D3A490 for ; Mon, 3 Oct 2022 10:31:47 -0700 (PDT) Received: by mail-pl1-x62a.google.com with SMTP id h10so7568271plb.2 for ; Mon, 03 Oct 2022 10:31:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date; bh=brOcpUsUebGaNnS9rr/mt+efWwjd5MMft3vidAloMCk=; b=GpXJl7r64TNCgnOm/rwzqm9/zk7r5bZs1M5dug+kDOLMHf5hbIymxV51Z69U+kH4ec Xh+SzqohGNj3VGnNBOgqyJHMF0dIC9NSQLfJh1llp1R+BxRxZ/qIGnDPQdSLmPX14uio of8Xxx4zz2IGzaRCl+H1y+LAFkYlycpJPRqBs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date; bh=brOcpUsUebGaNnS9rr/mt+efWwjd5MMft3vidAloMCk=; b=Atel0saJERy1NESjcp/O36z30FhK7Uyov52RjZM7zmNL/dNEosihwD+1kzdbIsAJBq BP7nGm5YmeS2KHXxVXYiTBcc1upkGGVNBn5MpUZA7rN+XZnP6bXn4K+Xu1yiO36bVlUN F4AF1PKlclmTipZaZuexXitfua5NRzdeHE7MXL97tMBPoppO/1ShzLXclttxP1o1f1pV Qlh5pLtmTco+5AGQSwtrjaJ/CA56JgMfJDgQh1HWYPhbYN2L5DIDP4ugD6d/kT+w9v/j LXLUUoU4O1c7oCW+vsTP7KOl8JpRpTDxCWgQBdkaTucNsnws0DGnyNAtrdnBW2HlzJoe NQxw== X-Gm-Message-State: ACrzQf3zOx/nuv0eK6h2/XYX1CPHTrSv6JWHWR9SywAESyUvcgAmtTri ud1d7tNQSBcTSPz9x8aMxV50VA== X-Google-Smtp-Source: AMsMyM57IJgx9Y5p5pOQkLFB+rSBDgUxwSCSiOSFplteoE6b0dUVolrJ3ykqvwSNZ198SqBVgt1Gug== X-Received: by 2002:a17:902:7081:b0:178:6154:9d79 with SMTP id z1-20020a170902708100b0017861549d79mr23572512plk.79.1664818307148; Mon, 03 Oct 2022 10:31:47 -0700 (PDT) Received: from www.outflux.net (smtp.outflux.net. [198.145.64.163]) by smtp.gmail.com with ESMTPSA id y23-20020a17090264d700b00176e2fa216csm7562816pli.52.2022.10.03.10.31.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Oct 2022 10:31:46 -0700 (PDT) Date: Mon, 3 Oct 2022 10:31:45 -0700 From: Kees Cook To: Rick Edgecombe Cc: x86@kernel.org, "H . Peter Anvin" , Thomas Gleixner , Ingo Molnar , linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-api@vger.kernel.org, Arnd Bergmann , Andy Lutomirski , Balbir Singh , Borislav Petkov , Cyrill Gorcunov , Dave Hansen , Eugene Syromiatnikov , Florian Weimer , "H . J . Lu" , Jann Horn , Jonathan Corbet , Mike Kravetz , Nadav Amit , Oleg Nesterov , Pavel Machek , Peter Zijlstra , Randy Dunlap , "Ravi V . Shankar" , Weijiang Yang , "Kirill A . Shutemov" , joao.moreira@intel.com, John Allen , kcc@google.com, eranian@google.com, rppt@kernel.org, jamorris@linux.microsoft.com, dethoma@microsoft.com, Yu-cheng Yu Subject: Re: [PATCH v2 04/39] x86/cpufeatures: Enable CET CR4 bit for shadow stack Message-ID: <202210031031.E2942B66@keescook> References: <20220929222936.14584-1-rick.p.edgecombe@intel.com> <20220929222936.14584-5-rick.p.edgecombe@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220929222936.14584-5-rick.p.edgecombe@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Sep 29, 2022 at 03:29:01PM -0700, Rick Edgecombe wrote: > From: Yu-cheng Yu > > Utilizing CET features requires a CR4 bit to be enabled as well as bits > to be set in CET MSRs. Setting the CR4 bit does two things: > 1. Enables the usage of WRUSS instruction, which the kernel can use to > write to userspace shadow stacks. > 2. Allows those individual aspects of CET to be enabled later via the MSR. > 3. Allows CET to be enabled in guests > > While future patches will allow the MSR values to be saved and restored > per task, the CR4 bit will allow for WRUSS to be used regardless of if a > tasks CET MSRs have been restored. > > Kernel IBT already enables the CET CR4 bit when it detects IBT HW support > and is configured with kernel IBT. However future patches that enable > userspace shadow stack support will need the bit set as well. So change > the logic to enable it in either case. > > Clear MSR_IA32_U_CET in cet_disable() so that it can't live to see > userspace in a new kexec-ed kernel that has CR4.CET set from kernel IBT. > > Signed-off-by: Yu-cheng Yu > Co-developed-by: Rick Edgecombe > Signed-off-by: Rick Edgecombe > Cc: Kees Cook Reviewed-by: Kees Cook -- Kees Cook