All of lore.kernel.org
 help / color / mirror / Atom feed
From: Alan Previn <alan.previn.teres.alexis@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v2 3/7] drm/i915/pxp: Make intel_pxp_is_active implicitly sort PXP-owning-GT
Date: Wed,  5 Oct 2022 21:38:29 -0700	[thread overview]
Message-ID: <20221006043834.606220-4-alan.previn.teres.alexis@intel.com> (raw)
In-Reply-To: <20221006043834.606220-1-alan.previn.teres.alexis@intel.com>

Make intel_pxp_is_active implicitly find the PXP-owning-GT.
As per prior two patches, callers of this function shall now
pass in i915 since PXP is a global GPU feature. Make
intel_pxp_is_active implicitly find the right gt to check if
PXP is active so it's transparent to the callers.

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_context.c  |  2 +-
 drivers/gpu/drm/i915/pxp/intel_pxp.c         | 11 ++++++++---
 drivers/gpu/drm/i915/pxp/intel_pxp.h         |  2 +-
 drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c |  4 ++--
 drivers/gpu/drm/i915/pxp/intel_pxp_irq.c     |  2 +-
 5 files changed, 13 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index df03c1c7feb9..8443b485c62f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -271,7 +271,7 @@ static int proto_context_set_protected(struct drm_i915_private *i915,
 		 */
 		pc->pxp_wakeref = intel_runtime_pm_get(&i915->runtime_pm);
 
-		if (!intel_pxp_is_active(&to_gt(i915)->pxp))
+		if (!intel_pxp_is_active(i915))
 			ret = intel_pxp_start(&to_gt(i915)->pxp);
 	}
 
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 93e9bc383461..57b4e9f9e4d1 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -72,9 +72,14 @@ bool intel_pxp_is_enabled(struct drm_i915_private *i915)
 	return _pxp_is_enabled(&gt->pxp);
 }
 
-bool intel_pxp_is_active(const struct intel_pxp *pxp)
+bool intel_pxp_is_active(struct drm_i915_private *i915)
 {
-	return pxp->arb_is_valid;
+	struct intel_gt *gt = intel_pxp_get_owning_gt(i915);
+
+	if (!gt)
+		return false;
+
+	return gt->pxp.arb_is_valid;
 }
 
 /* KCR register definitions */
@@ -292,7 +297,7 @@ int intel_pxp_key_check(struct intel_pxp *pxp,
 			struct drm_i915_gem_object *obj,
 			bool assign)
 {
-	if (!intel_pxp_is_active(pxp))
+	if (!intel_pxp_is_active(pxp_to_gt(pxp)->i915))
 		return -ENODEV;
 
 	if (!i915_gem_object_is_protected(obj))
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index e82154a147b9..0219ff285788 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -16,7 +16,7 @@ struct drm_i915_private;
 struct intel_gt *pxp_to_gt(const struct intel_pxp *pxp);
 struct intel_gt *intel_pxp_get_owning_gt(struct drm_i915_private *i915);
 bool intel_pxp_is_enabled(struct drm_i915_private *i915);
-bool intel_pxp_is_active(const struct intel_pxp *pxp);
+bool intel_pxp_is_active(struct drm_i915_private *i915);
 
 void intel_pxp_init(struct intel_pxp *pxp);
 void intel_pxp_fini(struct intel_pxp *pxp);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c b/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c
index 907d3aba7a9c..210dd2f28c42 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c
@@ -25,7 +25,7 @@ static int pxp_info_show(struct seq_file *m, void *data)
 		return 0;
 	}
 
-	drm_printf(&p, "active: %s\n", str_yes_no(intel_pxp_is_active(pxp)));
+	drm_printf(&p, "active: %s\n", str_yes_no(intel_pxp_is_active(pxp_to_gt(pxp)->i915)));
 	drm_printf(&p, "instance counter: %u\n", pxp->key_instance);
 
 	return 0;
@@ -43,7 +43,7 @@ static int pxp_terminate_set(void *data, u64 val)
 	struct intel_pxp *pxp = data;
 	struct intel_gt *gt = pxp_to_gt(pxp);
 
-	if (!intel_pxp_is_active(pxp))
+	if (!intel_pxp_is_active(gt->i915))
 		return -ENODEV;
 
 	/* simulate a termination interrupt */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
index 6f515c163d2f..a8baffb51389 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
@@ -89,7 +89,7 @@ void intel_pxp_irq_disable(struct intel_pxp *pxp)
 	 * called in a path were the driver consider the session as valid and
 	 * doesn't call a termination on restart.
 	 */
-	GEM_WARN_ON(intel_pxp_is_active(pxp));
+	GEM_WARN_ON(intel_pxp_is_active(gt->i915));
 
 	spin_lock_irq(gt->irq_lock);
 
-- 
2.34.1


  parent reply	other threads:[~2022-10-06  4:36 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-06  4:38 [Intel-gfx] [PATCH v2 0/7] drm/i915/pxp: Prepare intel_pxp entry points for MTL Alan Previn
2022-10-06  4:38 ` [Intel-gfx] [PATCH v2 1/7] drm/i915/pxp: Make gt and pxp init/fini aware of PXP-owning-GT Alan Previn
2022-10-13 20:48   ` Ceraolo Spurio, Daniele
2022-10-17 17:01     ` Teres Alexis, Alan Previn
2022-10-21  3:54       ` Teres Alexis, Alan Previn
2022-10-21  8:16       ` Teres Alexis, Alan Previn
2022-10-06  4:38 ` [Intel-gfx] [PATCH v2 2/7] drm/i915/pxp: Make intel_pxp_is_enabled implicitly sort PXP-owning-GT Alan Previn
2022-10-13 21:10   ` Ceraolo Spurio, Daniele
2022-10-17 17:12     ` Teres Alexis, Alan Previn
2022-10-06  4:38 ` Alan Previn [this message]
2022-10-06  4:38 ` [Intel-gfx] [PATCH v2 4/7] drm/i915/pxp: Make PXP tee component bind/unbind aware of PXP-owning-GT Alan Previn
2022-10-06  4:38 ` [Intel-gfx] [PATCH v2 5/7] drm/i915/pxp: Make intel_pxp_start implicitly sort PXP-owning-GT Alan Previn
2022-10-06  4:38 ` [Intel-gfx] [PATCH v2 6/7] drm/i915/pxp: Make intel_pxp_key_check " Alan Previn
2022-10-06  4:38 ` [Intel-gfx] [PATCH v2 7/7] drm/i915/pxp: Make intel_pxp power management " Alan Previn
2022-10-21 16:29   ` Teres Alexis, Alan Previn
2022-10-06  5:09 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/pxp: Prepare intel_pxp entry points for MTL (rev2) Patchwork
2022-10-06  5:09 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-10-06  5:32 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-10-06 18:19 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-10-10 19:05   ` Teres Alexis, Alan Previn

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20221006043834.606220-4-alan.previn.teres.alexis@intel.com \
    --to=alan.previn.teres.alexis@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.