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From: Mika Kahola <mika.kahola@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 13/20] drm/i915/mtl: For DP2.0 10G and 20G rates use MPLLA
Date: Fri, 14 Oct 2022 15:47:33 +0300	[thread overview]
Message-ID: <20221014124740.774835-14-mika.kahola@intel.com> (raw)
In-Reply-To: <20221014124740.774835-1-mika.kahola@intel.com>

Use MPLLA for DP2.0 rates 20G and 20G, when ssc is enabled.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index aab606520a62..9ce55b0c1cdc 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -1728,8 +1728,12 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
 		if (intel_dp_is_edp(intel_dp) && !intel_panel_use_ssc(i915))
 			ssc_enabled = false;
 
-		/* TODO: DP2.0 10G and 20G rates enable MPLLA*/
-		val |= ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
+		/* DP2.0 10G and 20G rates enable MPLLA*/
+		if (crtc_state->port_clock == 1000000 || crtc_state->port_clock == 2000000) {
+			val |= ssc_enabled ? XELPDP_SSC_ENABLE_PLLA : 0;
+		} else {
+			val |= ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
+		}
 	}
 
 	intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
-- 
2.34.1


  parent reply	other threads:[~2022-10-14 12:52 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-14 12:47 [Intel-gfx] [PATCH 00/20] drm/i915/mtl: Add C10 and C20 phy support Mika Kahola
2022-10-14 12:47 ` [Intel-gfx] [PATCH 01/20] drm/i915/mtl: Initial DDI port setup Mika Kahola
2022-11-29  0:23   ` Sripada, Radhakrishna
2022-10-14 12:47 ` [Intel-gfx] [PATCH 02/20] drm/i915/mtl: Add DP rates Mika Kahola
2022-10-14 12:47 ` [Intel-gfx] [PATCH 03/20] drm/i915/mtl: Create separate reg file for PICA registers Mika Kahola
2022-11-02 16:54   ` Jani Nikula
2022-11-02 16:59     ` Jani Nikula
2022-10-14 12:47 ` [Intel-gfx] [PATCH 04/20] drm/i915/mtl: Add Support for C10 PHY message bus and pll programming Mika Kahola
2022-10-14 12:47 ` [Intel-gfx] [PATCH 05/20] drm/i915/mtl: Add C10 phy programming for HDMI Mika Kahola
2022-10-14 12:47 ` [Intel-gfx] [PATCH 06/20] drm/i915/mtl: Add vswing programming for C10 phys Mika Kahola
2022-10-31 20:29   ` Taylor, Clinton A
2022-11-01  7:31     ` Kahola, Mika
2022-10-14 12:47 ` [Intel-gfx] [PATCH 07/20] drm/i915/mtl: Add support for PM DEMAND Mika Kahola
2022-11-01  2:38   ` Sripada, Radhakrishna
2022-11-15 12:56     ` Kahola, Mika
2022-10-14 12:47 ` [Intel-gfx] [PATCH 08/20] drm/i915/mtl: C20 PLL programming Mika Kahola
2022-10-14 12:47 ` [Intel-gfx] [PATCH 09/20] drm/i915/mtl: C20 HW readout Mika Kahola
2022-10-14 12:47 ` [Intel-gfx] [PATCH 10/20] drm/i915/mtl: C20 port clock calculation Mika Kahola
2022-10-14 12:47 ` [Intel-gfx] [PATCH 11/20] drm/i915/mtl: C20 HDMI state calculations Mika Kahola
2022-10-14 12:47 ` [Intel-gfx] [PATCH 12/20] drm/i915/mtl: Add voltage swing sequence for C20 Mika Kahola
2022-10-14 12:47 ` Mika Kahola [this message]
2022-10-14 12:47 ` [Intel-gfx] [PATCH 14/20] drm/i915/mtl: Enabling/disabling sequence Thunderbolt pll Mika Kahola
2022-10-14 12:47 ` [Intel-gfx] [PATCH 15/20] drm/i915/mtl: Readout Thunderbolt HW state Mika Kahola
2022-10-14 12:47 ` [Intel-gfx] [PATCH 16/20] drm/i915/mtl: Enable TC ports Mika Kahola
2022-10-14 12:47 ` [Intel-gfx] [PATCH 17/20] drm/i915/mtl: MTL PICA hotplug detection Mika Kahola
2022-10-14 12:47 ` [Intel-gfx] [PATCH 18/20] drm/i915/mtl: Define mask for DDI AUX interrupts Mika Kahola
2022-10-14 12:47 ` [Intel-gfx] [PATCH 19/20] drm/i915/mtl: Power up TCSS Mika Kahola
2022-10-14 12:47 ` [Intel-gfx] [PATCH 20/20] drm/i915/mtl: Pin assignment for TypeC Mika Kahola
2022-10-26 14:26   ` Imre Deak
2022-10-27  8:15     ` Kahola, Mika
2022-10-14 13:11 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/mtl: Add C10 and C20 phy support Patchwork
2022-10-14 13:11 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-10-14 13:34 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-10-14 14:50 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-10-31 21:49 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/mtl: Add C10 and C20 phy support (rev2) Patchwork
2022-11-01  7:55 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/mtl: Add C10 and C20 phy support (rev3) Patchwork

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