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Thu, 20 Oct 2022 15:31:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=stgolabs.net; s=dreamhost; t=1666305088; bh=FiZrMkrbNubHQO8sAmPoXSgTBVbDs1cimp79mld8fpA=; h=Date:From:To:Cc:Subject:Content-Type; b=lFUWZ1HJ7mmYeXIfNiicNJE0dqTPoTi2U4KK0rnhhmzHnnhyujr2zjjISe4Qh9y1E anJ/DuBCb8G8WfHRY/U2DYpscNQMSu2HoreF3ypP2ICRL407+JFZWL7PIoAZks6uYT sijaNFmupE/KaIlbkK7Y3Bp0/4Q7tcDP4giwELxs1GaUP5hYdsnj5dUZW74tIH2cId +Gy08RBSU/HzhaSfgLbBt9BTy4VvX2Z/Ib3WaCXJszqywGe/pHjjtVJHdlW7GmtTx/ a89+yMYhEcb0IEsneQISmRtI8BqhFsx/CDW/hS9smUxHB80pwY3BqkrEQs2hN5dNNy muNhtGg5ceHYg== Date: Thu, 20 Oct 2022 15:31:25 -0700 From: Davidlohr Bueso To: Jonathan Cameron Cc: dan.j.williams@intel.com, ira.weiny@intel.com, dave.jiang@intel.com, alison.schofield@intel.com, bwidawsk@kernel.org, vishal.l.verma@intel.com, a.manzanares@samsung.com, linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/2] cxl/pci: Add generic MSI-X/MSI irq support Message-ID: <20221020223125.hyrfpt2noiicisxa@offworld> References: <20221018030010.20913-1-dave@stgolabs.net> <20221018030010.20913-2-dave@stgolabs.net> <20221018103619.00004c39@huawei.com> <20221018115227.00002a4c@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Disposition: inline In-Reply-To: <20221018115227.00002a4c@huawei.com> User-Agent: NeoMutt/20220429 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 18 Oct 2022, Jonathan Cameron wrote: >Reality is that it is cleaner to more or less ignore the infrastructure >proposed in this patch. > >1. Query how many CPMU devices there are. Whilst there stash the maximim > cpmu vector number in the cxlds. >2. Run a stub in this infrastructure that does max(irq, cxlds->irq_num); >3. Carry on as before. > >Thus destroying the point of this infrastructure for that usecase at least >and leaving an extra bit of state in the cxl_dev_state that is just >to squirt a value into the callback... If it doesn't fit, then it doesn't fit. However, while I was expecting pass one to be in the callback, I wasn't expecting that both pass 1 and 2 shared the cpmu_regs_array. If the array could be reconstructed during pass 2, then it would fit a bit better; albeit the extra allocation, cycles etc., but this is probing phase, so overhead isn't that important (and cpmu_count isn't big enough to matter). But if we're going to go with a free-for-all approach, can we establish who goes for the initial pci_alloc_irq_vectors()? I think perhaps mbox since it's the most straightforward and with least requirements, I'm also unsure of the status yet to merge events and pmu, but regardless they are still larger patchsets. If folks agree I can send a new mbox-only patch. Thanks, Davidlohr