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From: Jianmin Lv <lvjianmin@loongson.cn>
To: Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>
Cc: linux-kernel@vger.kernel.org, loongarch@lists.linux.dev,
	Jiaxun Yang <jiaxun.yang@flygoat.com>,
	Huacai Chen <chenhuacai@loongson.cn>,
	Bjorn Helgaas <bhelgaas@google.com>, Len Brown <lenb@kernel.org>,
	rafael@kernel.org, linux-pci@vger.kernel.org,
	linux-acpi@vger.kernel.org
Subject: [PATCH V5 1/4] ACPI / PCI: fix LPIC IRQ model default PCI IRQ polarity
Date: Sat, 22 Oct 2022 15:59:52 +0800	[thread overview]
Message-ID: <20221022075955.11726-2-lvjianmin@loongson.cn> (raw)
In-Reply-To: <20221022075955.11726-1-lvjianmin@loongson.cn>

On LoongArch based systems, the PCI devices (e.g. SATA controllers and
PCI-to-PCI bridge controllers) in Loongson chipsets output high-level
interrupt signal to the interrupt controller they are connected (see
Loongson 7A1000 Bridge User Manual v2.00, sec 5.3, "For the bridge chip,
AC97 DMA interrupts are edge triggered, gpio interrupts can be configured
to be level triggered or edge triggered as needed, and the rest of the
interrupts are level triggered and active high."), while the IRQs are
active low from the perspective of PCI (see Conventional PCI spec r3.0,
sec 2.2.6, "Interrupts on PCI are optional and defined as level sensitive,
asserted low."), which means that the interrupt output of PCI devices plugged
into PCI-to-PCI bridges of Loongson chipset will be also converted to high-level.
So high level triggered type is required to be passed to acpi_register_gsi()
when creating mappings for PCI devices.

Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
---
 drivers/acpi/pci_irq.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/acpi/pci_irq.c b/drivers/acpi/pci_irq.c
index 08e15774fb9f..ff30ceca2203 100644
--- a/drivers/acpi/pci_irq.c
+++ b/drivers/acpi/pci_irq.c
@@ -387,13 +387,15 @@ int acpi_pci_irq_enable(struct pci_dev *dev)
 	u8 pin;
 	int triggering = ACPI_LEVEL_SENSITIVE;
 	/*
-	 * On ARM systems with the GIC interrupt model, level interrupts
+	 * On ARM systems with the GIC interrupt model, or LoongArch
+	 * systems with the LPIC interrupt model, level interrupts
 	 * are always polarity high by specification; PCI legacy
 	 * IRQs lines are inverted before reaching the interrupt
 	 * controller and must therefore be considered active high
 	 * as default.
 	 */
-	int polarity = acpi_irq_model == ACPI_IRQ_MODEL_GIC ?
+	int polarity = acpi_irq_model == ACPI_IRQ_MODEL_GIC ||
+		       acpi_irq_model == ACPI_IRQ_MODEL_LPIC ?
 				      ACPI_ACTIVE_HIGH : ACPI_ACTIVE_LOW;
 	char *link = NULL;
 	char link_desc[16];
-- 
2.31.1


  reply	other threads:[~2022-10-22  7:59 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-22  7:59 [PATCH V5 0/4] irqchip: Support to set irq type for ACPI path Jianmin Lv
2022-10-22  7:59 ` Jianmin Lv [this message]
2022-11-26 13:34   ` [irqchip: irq/irqchip-next] ACPI / PCI: fix LPIC IRQ model default PCI IRQ polarity irqchip-bot for Jianmin Lv
2022-10-22  7:59 ` [PATCH V5 2/4] irqchip/loongson-pch-pic: fix translate callback for DT path Jianmin Lv
2022-11-26 13:34   ` [irqchip: irq/irqchip-next] irqchip/loongson-pch-pic: Fix " irqchip-bot for Jianmin Lv
2022-10-22  7:59 ` [PATCH V5 3/4] irqchip/loongson-pch-pic: Support to set IRQ type for ACPI path Jianmin Lv
2022-11-26 13:34   ` [irqchip: irq/irqchip-next] " irqchip-bot for Jianmin Lv
2022-10-22  7:59 ` [PATCH V5 4/4] irqchip/loongson-liointc: " Jianmin Lv
2022-11-26 13:34   ` [irqchip: irq/irqchip-next] " irqchip-bot for Jianmin Lv
2022-10-22  8:05 ` [PATCH V5 0/4] irqchip: Support to set irq " Huacai Chen

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