[Intel-gfx] [PATCH 00/11] drm/i915: More gamma work

[Intel-gfx] [PATCH 00/11] drm/i915: More gamma work

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Another serires of (mostly) cleanups to the color management
code.

The one functional thing in there is the last patch that
reworks how we handle the split gamma mode now that we
have a way to cook up internal LUTs.

Still not full readout+state check I'm afraid. That will
be in the next series.

Ville Syrjälä (11):
  drm/i915: Use sizeof(variable) instead sizeof(type)
  drm/i915: Use _MMIO_PIPE() for SKL_BOTTOM_COLOR
  drm/i915: s/dev_priv/i915/ in intel_color.c
  drm/i915: s/icl_load_gcmax/ivb_load_lut_max/
  drm/i915: Split ivb_load_lut_ext_max() into two parts
  drm/i915: Deconfuse the ilk+ 12.4 LUT entry functions
  drm/i915: Pass limited_range explicitly to ilk_csc_convert_ctm()
  drm/i915: Reuse ilk_gamma_mode() on ivb+
  drm/i915: Reject YCbCr output with degamma+gamma on pre-icl
  drm/i915: Share {csc,gamma}_enable calculation for ilk/snb vs. ivb+
  drm/i915: Create resized LUTs for ivb+ split gamma mode

 drivers/gpu/drm/i915/display/intel_color.c | 529 ++++++++++++---------
 drivers/gpu/drm/i915/i915_reg.h            |   3 +-
 2 files changed, 302 insertions(+), 230 deletions(-)

-- 
2.37.4

[Intel-gfx] [PATCH 01/11] drm/i915: Use sizeof(variable) instead sizeof(type)

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Use sizeof(variable) instead of sizeof(type) in the hopes of
less chance of screwing things up.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 4bb113c39f4b..92cc43d5bad6 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -565,7 +565,7 @@ create_linear_lut(struct drm_i915_private *i915, int lut_size)
 	int i;
 
 	blob = drm_property_create_blob(&i915->drm,
-					sizeof(struct drm_color_lut) * lut_size,
+					sizeof(lut[0]) * lut_size,
 					NULL);
 	if (IS_ERR(blob))
 		return blob;
@@ -1895,7 +1895,7 @@ static struct drm_property_blob *i9xx_read_lut_8(struct intel_crtc *crtc)
 	int i;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
-					sizeof(struct drm_color_lut) * LEGACY_LUT_LENGTH,
+					sizeof(lut[0]) * LEGACY_LUT_LENGTH,
 					NULL);
 	if (IS_ERR(blob))
 		return NULL;
@@ -1930,7 +1930,7 @@ static struct drm_property_blob *i965_read_lut_10p6(struct intel_crtc *crtc)
 	struct drm_color_lut *lut;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
-					sizeof(struct drm_color_lut) * lut_size,
+					sizeof(lut[0]) * lut_size,
 					NULL);
 	if (IS_ERR(blob))
 		return NULL;
@@ -1973,7 +1973,7 @@ static struct drm_property_blob *chv_read_cgm_gamma(struct intel_crtc *crtc)
 	struct drm_color_lut *lut;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
-					sizeof(struct drm_color_lut) * lut_size,
+					sizeof(lut[0]) * lut_size,
 					NULL);
 	if (IS_ERR(blob))
 		return NULL;
@@ -2009,7 +2009,7 @@ static struct drm_property_blob *ilk_read_lut_8(struct intel_crtc *crtc)
 	int i;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
-					sizeof(struct drm_color_lut) * LEGACY_LUT_LENGTH,
+					sizeof(lut[0]) * LEGACY_LUT_LENGTH,
 					NULL);
 	if (IS_ERR(blob))
 		return NULL;
@@ -2034,7 +2034,7 @@ static struct drm_property_blob *ilk_read_lut_10(struct intel_crtc *crtc)
 	struct drm_color_lut *lut;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
-					sizeof(struct drm_color_lut) * lut_size,
+					sizeof(lut[0]) * lut_size,
 					NULL);
 	if (IS_ERR(blob))
 		return NULL;
@@ -2087,7 +2087,7 @@ static struct drm_property_blob *bdw_read_lut_10(struct intel_crtc *crtc,
 	drm_WARN_ON(&dev_priv->drm, lut_size != hw_lut_size);
 
 	blob = drm_property_create_blob(&dev_priv->drm,
-					sizeof(struct drm_color_lut) * lut_size,
+					sizeof(lut[0]) * lut_size,
 					NULL);
 	if (IS_ERR(blob))
 		return NULL;
@@ -2138,7 +2138,7 @@ icl_read_lut_multi_segment(struct intel_crtc *crtc)
 	struct drm_color_lut *lut;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
-					sizeof(struct drm_color_lut) * lut_size,
+					sizeof(lut[0]) * lut_size,
 					NULL);
 	if (IS_ERR(blob))
 		return NULL;
-- 
2.37.4

[Intel-gfx] [PATCH 02/11] drm/i915: Use _MMIO_PIPE() for SKL_BOTTOM_COLOR

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

No need to use _MMIO_PIPE2() for SKL_BOTTOM_COLOR
since all pipe registers are evenly spread on skl+.
Switch to _MMIO_PIPE() and thus avoid the hidden dev_priv.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 99a853519395..89ad893bbf07 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3758,9 +3758,10 @@
 
 /* Skylake+ pipe bottom (background) color */
 #define _SKL_BOTTOM_COLOR_A		0x70034
+#define _SKL_BOTTOM_COLOR_B		0x71034
 #define   SKL_BOTTOM_COLOR_GAMMA_ENABLE		REG_BIT(31)
 #define   SKL_BOTTOM_COLOR_CSC_ENABLE		REG_BIT(30)
-#define SKL_BOTTOM_COLOR(pipe)		_MMIO_PIPE2(pipe, _SKL_BOTTOM_COLOR_A)
+#define SKL_BOTTOM_COLOR(pipe)		_MMIO_PIPE(pipe, _SKL_BOTTOM_COLOR_A, _SKL_BOTTOM_COLOR_B)
 
 #define _ICL_PIPE_A_STATUS			0x70058
 #define ICL_PIPESTATUS(pipe)			_MMIO_PIPE2(pipe, _ICL_PIPE_A_STATUS)
-- 
2.37.4

[Intel-gfx] [PATCH 03/11] drm/i915: s/dev_priv/i915/ in intel_color.c

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Switch intel_color.c over to the modern 'i915' variable
naming scehme. The only exceptions are the i9xx LUT access
functions which still need the magic 'dev_priv' for the
register macros.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 278 ++++++++++-----------
 1 file changed, 139 insertions(+), 139 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 92cc43d5bad6..415e0a6839a4 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -184,31 +184,31 @@ static void ilk_update_pipe_csc(struct intel_crtc *crtc,
 				const u16 coeff[9],
 				const u16 postoff[3])
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 
-	intel_de_write_fw(dev_priv, PIPE_CSC_PREOFF_HI(pipe), preoff[0]);
-	intel_de_write_fw(dev_priv, PIPE_CSC_PREOFF_ME(pipe), preoff[1]);
-	intel_de_write_fw(dev_priv, PIPE_CSC_PREOFF_LO(pipe), preoff[2]);
+	intel_de_write_fw(i915, PIPE_CSC_PREOFF_HI(pipe), preoff[0]);
+	intel_de_write_fw(i915, PIPE_CSC_PREOFF_ME(pipe), preoff[1]);
+	intel_de_write_fw(i915, PIPE_CSC_PREOFF_LO(pipe), preoff[2]);
 
-	intel_de_write_fw(dev_priv, PIPE_CSC_COEFF_RY_GY(pipe),
+	intel_de_write_fw(i915, PIPE_CSC_COEFF_RY_GY(pipe),
 			  coeff[0] << 16 | coeff[1]);
-	intel_de_write_fw(dev_priv, PIPE_CSC_COEFF_BY(pipe), coeff[2] << 16);
+	intel_de_write_fw(i915, PIPE_CSC_COEFF_BY(pipe), coeff[2] << 16);
 
-	intel_de_write_fw(dev_priv, PIPE_CSC_COEFF_RU_GU(pipe),
+	intel_de_write_fw(i915, PIPE_CSC_COEFF_RU_GU(pipe),
 			  coeff[3] << 16 | coeff[4]);
-	intel_de_write_fw(dev_priv, PIPE_CSC_COEFF_BU(pipe), coeff[5] << 16);
+	intel_de_write_fw(i915, PIPE_CSC_COEFF_BU(pipe), coeff[5] << 16);
 
-	intel_de_write_fw(dev_priv, PIPE_CSC_COEFF_RV_GV(pipe),
+	intel_de_write_fw(i915, PIPE_CSC_COEFF_RV_GV(pipe),
 			  coeff[6] << 16 | coeff[7]);
-	intel_de_write_fw(dev_priv, PIPE_CSC_COEFF_BV(pipe), coeff[8] << 16);
+	intel_de_write_fw(i915, PIPE_CSC_COEFF_BV(pipe), coeff[8] << 16);
 
-	if (DISPLAY_VER(dev_priv) >= 7) {
-		intel_de_write_fw(dev_priv, PIPE_CSC_POSTOFF_HI(pipe),
+	if (DISPLAY_VER(i915) >= 7) {
+		intel_de_write_fw(i915, PIPE_CSC_POSTOFF_HI(pipe),
 				  postoff[0]);
-		intel_de_write_fw(dev_priv, PIPE_CSC_POSTOFF_ME(pipe),
+		intel_de_write_fw(i915, PIPE_CSC_POSTOFF_ME(pipe),
 				  postoff[1]);
-		intel_de_write_fw(dev_priv, PIPE_CSC_POSTOFF_LO(pipe),
+		intel_de_write_fw(i915, PIPE_CSC_POSTOFF_LO(pipe),
 				  postoff[2]);
 	}
 }
@@ -218,44 +218,44 @@ static void icl_update_output_csc(struct intel_crtc *crtc,
 				  const u16 coeff[9],
 				  const u16 postoff[3])
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 
-	intel_de_write_fw(dev_priv, PIPE_CSC_OUTPUT_PREOFF_HI(pipe), preoff[0]);
-	intel_de_write_fw(dev_priv, PIPE_CSC_OUTPUT_PREOFF_ME(pipe), preoff[1]);
-	intel_de_write_fw(dev_priv, PIPE_CSC_OUTPUT_PREOFF_LO(pipe), preoff[2]);
+	intel_de_write_fw(i915, PIPE_CSC_OUTPUT_PREOFF_HI(pipe), preoff[0]);
+	intel_de_write_fw(i915, PIPE_CSC_OUTPUT_PREOFF_ME(pipe), preoff[1]);
+	intel_de_write_fw(i915, PIPE_CSC_OUTPUT_PREOFF_LO(pipe), preoff[2]);
 
-	intel_de_write_fw(dev_priv, PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe),
+	intel_de_write_fw(i915, PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe),
 			  coeff[0] << 16 | coeff[1]);
-	intel_de_write_fw(dev_priv, PIPE_CSC_OUTPUT_COEFF_BY(pipe),
+	intel_de_write_fw(i915, PIPE_CSC_OUTPUT_COEFF_BY(pipe),
 			  coeff[2] << 16);
 
-	intel_de_write_fw(dev_priv, PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe),
+	intel_de_write_fw(i915, PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe),
 			  coeff[3] << 16 | coeff[4]);
-	intel_de_write_fw(dev_priv, PIPE_CSC_OUTPUT_COEFF_BU(pipe),
+	intel_de_write_fw(i915, PIPE_CSC_OUTPUT_COEFF_BU(pipe),
 			  coeff[5] << 16);
 
-	intel_de_write_fw(dev_priv, PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe),
+	intel_de_write_fw(i915, PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe),
 			  coeff[6] << 16 | coeff[7]);
-	intel_de_write_fw(dev_priv, PIPE_CSC_OUTPUT_COEFF_BV(pipe),
+	intel_de_write_fw(i915, PIPE_CSC_OUTPUT_COEFF_BV(pipe),
 			  coeff[8] << 16);
 
-	intel_de_write_fw(dev_priv, PIPE_CSC_OUTPUT_POSTOFF_HI(pipe), postoff[0]);
-	intel_de_write_fw(dev_priv, PIPE_CSC_OUTPUT_POSTOFF_ME(pipe), postoff[1]);
-	intel_de_write_fw(dev_priv, PIPE_CSC_OUTPUT_POSTOFF_LO(pipe), postoff[2]);
+	intel_de_write_fw(i915, PIPE_CSC_OUTPUT_POSTOFF_HI(pipe), postoff[0]);
+	intel_de_write_fw(i915, PIPE_CSC_OUTPUT_POSTOFF_ME(pipe), postoff[1]);
+	intel_de_write_fw(i915, PIPE_CSC_OUTPUT_POSTOFF_LO(pipe), postoff[2]);
 }
 
 static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 
 	/*
 	 * FIXME if there's a gamma LUT after the CSC, we should
 	 * do the range compression using the gamma LUT instead.
 	 */
 	return crtc_state->limited_color_range &&
-		(IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
-		 IS_DISPLAY_VER(dev_priv, 9, 10));
+		(IS_HASWELL(i915) || IS_BROADWELL(i915) ||
+		 IS_DISPLAY_VER(i915, 9, 10));
 }
 
 static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
@@ -313,7 +313,7 @@ static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
 static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 	bool limited_color_range = ilk_csc_limited_range(crtc_state);
 
 	if (crtc_state->hw.ctm) {
@@ -339,7 +339,7 @@ static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
 		 * LUT is needed but CSC is not we need to load an
 		 * identity matrix.
 		 */
-		drm_WARN_ON(&dev_priv->drm, !IS_GEMINILAKE(dev_priv));
+		drm_WARN_ON(&i915->drm, !IS_GEMINILAKE(i915));
 
 		ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
 				    ilk_csc_coeff_identity,
@@ -373,7 +373,7 @@ static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state)
 static void chv_load_cgm_csc(struct intel_crtc *crtc,
 			     const struct drm_property_blob *blob)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 	const struct drm_color_ctm *ctm = blob->data;
 	enum pipe pipe = crtc->pipe;
 	u16 coeffs[9];
@@ -397,15 +397,15 @@ static void chv_load_cgm_csc(struct intel_crtc *crtc,
 		coeffs[i] |= (abs_coeff >> 20) & 0xfff;
 	}
 
-	intel_de_write_fw(dev_priv, CGM_PIPE_CSC_COEFF01(pipe),
+	intel_de_write_fw(i915, CGM_PIPE_CSC_COEFF01(pipe),
 			  coeffs[1] << 16 | coeffs[0]);
-	intel_de_write_fw(dev_priv, CGM_PIPE_CSC_COEFF23(pipe),
+	intel_de_write_fw(i915, CGM_PIPE_CSC_COEFF23(pipe),
 			  coeffs[3] << 16 | coeffs[2]);
-	intel_de_write_fw(dev_priv, CGM_PIPE_CSC_COEFF45(pipe),
+	intel_de_write_fw(i915, CGM_PIPE_CSC_COEFF45(pipe),
 			  coeffs[5] << 16 | coeffs[4]);
-	intel_de_write_fw(dev_priv, CGM_PIPE_CSC_COEFF67(pipe),
+	intel_de_write_fw(i915, CGM_PIPE_CSC_COEFF67(pipe),
 			  coeffs[7] << 16 | coeffs[6]);
-	intel_de_write_fw(dev_priv, CGM_PIPE_CSC_COEFF8(pipe),
+	intel_de_write_fw(i915, CGM_PIPE_CSC_COEFF8(pipe),
 			  coeffs[8]);
 }
 
@@ -511,31 +511,31 @@ static void i9xx_color_commit_arm(const struct intel_crtc_state *crtc_state)
 static void ilk_color_commit_arm(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 
 	/* update PIPECONF GAMMA_MODE */
 	ilk_set_pipeconf(crtc_state);
 
-	intel_de_write_fw(dev_priv, PIPE_CSC_MODE(crtc->pipe),
+	intel_de_write_fw(i915, PIPE_CSC_MODE(crtc->pipe),
 			  crtc_state->csc_mode);
 }
 
 static void hsw_color_commit_arm(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 
-	intel_de_write(dev_priv, GAMMA_MODE(crtc->pipe),
+	intel_de_write(i915, GAMMA_MODE(crtc->pipe),
 		       crtc_state->gamma_mode);
 
-	intel_de_write_fw(dev_priv, PIPE_CSC_MODE(crtc->pipe),
+	intel_de_write_fw(i915, PIPE_CSC_MODE(crtc->pipe),
 			  crtc_state->csc_mode);
 }
 
 static void skl_color_commit_arm(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 	u32 val = 0;
 
@@ -548,12 +548,12 @@ static void skl_color_commit_arm(const struct intel_crtc_state *crtc_state)
 		val |= SKL_BOTTOM_COLOR_GAMMA_ENABLE;
 	if (crtc_state->csc_enable)
 		val |= SKL_BOTTOM_COLOR_CSC_ENABLE;
-	intel_de_write(dev_priv, SKL_BOTTOM_COLOR(pipe), val);
+	intel_de_write(i915, SKL_BOTTOM_COLOR(pipe), val);
 
-	intel_de_write(dev_priv, GAMMA_MODE(crtc->pipe),
+	intel_de_write(i915, GAMMA_MODE(crtc->pipe),
 		       crtc_state->gamma_mode);
 
-	intel_de_write_fw(dev_priv, PIPE_CSC_MODE(crtc->pipe),
+	intel_de_write_fw(i915, PIPE_CSC_MODE(crtc->pipe),
 			  crtc_state->csc_mode);
 }
 
@@ -643,7 +643,7 @@ static void i965_load_luts(const struct intel_crtc_state *crtc_state)
 static void ilk_load_lut_8(struct intel_crtc *crtc,
 			   const struct drm_property_blob *blob)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 	const struct drm_color_lut *lut;
 	enum pipe pipe = crtc->pipe;
 	int i;
@@ -654,20 +654,20 @@ static void ilk_load_lut_8(struct intel_crtc *crtc,
 	lut = blob->data;
 
 	for (i = 0; i < 256; i++)
-		intel_de_write_fw(dev_priv, LGC_PALETTE(pipe, i),
+		intel_de_write_fw(i915, LGC_PALETTE(pipe, i),
 				  i9xx_lut_8(&lut[i]));
 }
 
 static void ilk_load_lut_10(struct intel_crtc *crtc,
 			    const struct drm_property_blob *blob)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 	const struct drm_color_lut *lut = blob->data;
 	int i, lut_size = drm_color_lut_size(blob);
 	enum pipe pipe = crtc->pipe;
 
 	for (i = 0; i < lut_size; i++)
-		intel_de_write_fw(dev_priv, PREC_PALETTE(pipe, i),
+		intel_de_write_fw(i915, PREC_PALETTE(pipe, i),
 				  ilk_lut_10(&lut[i]));
 }
 
@@ -708,7 +708,7 @@ static void ivb_load_lut_10(struct intel_crtc *crtc,
 			    const struct drm_property_blob *blob,
 			    u32 prec_index)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 	int hw_lut_size = ivb_lut_10_size(prec_index);
 	const struct drm_color_lut *lut = blob->data;
 	int i, lut_size = drm_color_lut_size(blob);
@@ -719,8 +719,8 @@ static void ivb_load_lut_10(struct intel_crtc *crtc,
 		const struct drm_color_lut *entry =
 			&lut[i * (lut_size - 1) / (hw_lut_size - 1)];
 
-		intel_de_write_fw(dev_priv, PREC_PAL_INDEX(pipe), prec_index++);
-		intel_de_write_fw(dev_priv, PREC_PAL_DATA(pipe),
+		intel_de_write_fw(i915, PREC_PAL_INDEX(pipe), prec_index++);
+		intel_de_write_fw(i915, PREC_PAL_DATA(pipe),
 				  ilk_lut_10(entry));
 	}
 
@@ -728,7 +728,7 @@ static void ivb_load_lut_10(struct intel_crtc *crtc,
 	 * Reset the index, otherwise it prevents the legacy palette to be
 	 * written properly.
 	 */
-	intel_de_write_fw(dev_priv, PREC_PAL_INDEX(pipe), 0);
+	intel_de_write_fw(i915, PREC_PAL_INDEX(pipe), 0);
 }
 
 /* On BDW+ the index auto increment mode actually works */
@@ -736,13 +736,13 @@ static void bdw_load_lut_10(struct intel_crtc *crtc,
 			    const struct drm_property_blob *blob,
 			    u32 prec_index)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 	int hw_lut_size = ivb_lut_10_size(prec_index);
 	const struct drm_color_lut *lut = blob->data;
 	int i, lut_size = drm_color_lut_size(blob);
 	enum pipe pipe = crtc->pipe;
 
-	intel_de_write_fw(dev_priv, PREC_PAL_INDEX(pipe),
+	intel_de_write_fw(i915, PREC_PAL_INDEX(pipe),
 			  prec_index | PAL_PREC_AUTO_INCREMENT);
 
 	for (i = 0; i < hw_lut_size; i++) {
@@ -750,7 +750,7 @@ static void bdw_load_lut_10(struct intel_crtc *crtc,
 		const struct drm_color_lut *entry =
 			&lut[i * (lut_size - 1) / (hw_lut_size - 1)];
 
-		intel_de_write_fw(dev_priv, PREC_PAL_DATA(pipe),
+		intel_de_write_fw(i915, PREC_PAL_DATA(pipe),
 				  ilk_lut_10(entry));
 	}
 
@@ -758,13 +758,13 @@ static void bdw_load_lut_10(struct intel_crtc *crtc,
 	 * Reset the index, otherwise it prevents the legacy palette to be
 	 * written properly.
 	 */
-	intel_de_write_fw(dev_priv, PREC_PAL_INDEX(pipe), 0);
+	intel_de_write_fw(i915, PREC_PAL_INDEX(pipe), 0);
 }
 
 static void ivb_load_lut_ext_max(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 
 	/* Program the max register to clamp values > 1.0. */
@@ -777,7 +777,7 @@ static void ivb_load_lut_ext_max(const struct intel_crtc_state *crtc_state)
 	 * ToDo: Extend the ABI to be able to program values
 	 * from 3.0 to 7.0
 	 */
-	if (DISPLAY_VER(dev_priv) >= 10) {
+	if (DISPLAY_VER(i915) >= 10) {
 		intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 0),
 				    1 << 16);
 		intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 1),
@@ -858,7 +858,7 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state,
 				 const struct drm_property_blob *blob)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 	const struct drm_color_lut *lut = blob->data;
 	int i, lut_size = drm_color_lut_size(blob);
 	enum pipe pipe = crtc->pipe;
@@ -868,8 +868,8 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state,
 	 * ignore the index bits, so we need to reset it to index 0
 	 * separately.
 	 */
-	intel_de_write_fw(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 0);
-	intel_de_write_fw(dev_priv, PRE_CSC_GAMC_INDEX(pipe),
+	intel_de_write_fw(i915, PRE_CSC_GAMC_INDEX(pipe), 0);
+	intel_de_write_fw(i915, PRE_CSC_GAMC_INDEX(pipe),
 			  PRE_CSC_GAMC_AUTO_INCREMENT);
 
 	for (i = 0; i < lut_size; i++) {
@@ -886,15 +886,15 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state,
 		 * ToDo: Extend to max 7.0. Enable 32 bit input value
 		 * as compared to just 16 to achieve this.
 		 */
-		intel_de_write_fw(dev_priv, PRE_CSC_GAMC_DATA(pipe),
+		intel_de_write_fw(i915, PRE_CSC_GAMC_DATA(pipe),
 				  lut[i].green);
 	}
 
 	/* Clamp values > 1.0. */
-	while (i++ < glk_degamma_lut_size(dev_priv))
-		intel_de_write_fw(dev_priv, PRE_CSC_GAMC_DATA(pipe), 1 << 16);
+	while (i++ < glk_degamma_lut_size(i915))
+		intel_de_write_fw(i915, PRE_CSC_GAMC_DATA(pipe), 1 << 16);
 
-	intel_de_write_fw(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 0);
+	intel_de_write_fw(i915, PRE_CSC_GAMC_INDEX(pipe), 0);
 }
 
 static void glk_load_luts(const struct intel_crtc_state *crtc_state)
@@ -1075,15 +1075,15 @@ static u32 chv_cgm_degamma_udw(const struct drm_color_lut *color)
 static void chv_load_cgm_degamma(struct intel_crtc *crtc,
 				 const struct drm_property_blob *blob)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 	const struct drm_color_lut *lut = blob->data;
 	int i, lut_size = drm_color_lut_size(blob);
 	enum pipe pipe = crtc->pipe;
 
 	for (i = 0; i < lut_size; i++) {
-		intel_de_write_fw(dev_priv, CGM_PIPE_DEGAMMA(pipe, i, 0),
+		intel_de_write_fw(i915, CGM_PIPE_DEGAMMA(pipe, i, 0),
 				  chv_cgm_degamma_ldw(&lut[i]));
-		intel_de_write_fw(dev_priv, CGM_PIPE_DEGAMMA(pipe, i, 1),
+		intel_de_write_fw(i915, CGM_PIPE_DEGAMMA(pipe, i, 1),
 				  chv_cgm_degamma_udw(&lut[i]));
 	}
 }
@@ -1109,15 +1109,15 @@ static void chv_cgm_gamma_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)
 static void chv_load_cgm_gamma(struct intel_crtc *crtc,
 			       const struct drm_property_blob *blob)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 	const struct drm_color_lut *lut = blob->data;
 	int i, lut_size = drm_color_lut_size(blob);
 	enum pipe pipe = crtc->pipe;
 
 	for (i = 0; i < lut_size; i++) {
-		intel_de_write_fw(dev_priv, CGM_PIPE_GAMMA(pipe, i, 0),
+		intel_de_write_fw(i915, CGM_PIPE_GAMMA(pipe, i, 0),
 				  chv_cgm_gamma_ldw(&lut[i]));
-		intel_de_write_fw(dev_priv, CGM_PIPE_GAMMA(pipe, i, 1),
+		intel_de_write_fw(i915, CGM_PIPE_GAMMA(pipe, i, 1),
 				  chv_cgm_gamma_udw(&lut[i]));
 	}
 }
@@ -1125,7 +1125,7 @@ static void chv_load_cgm_gamma(struct intel_crtc *crtc,
 static void chv_load_luts(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 	const struct drm_property_blob *pre_csc_lut = crtc_state->pre_csc_lut;
 	const struct drm_property_blob *post_csc_lut = crtc_state->post_csc_lut;
 	const struct drm_property_blob *ctm = crtc_state->hw.ctm;
@@ -1141,30 +1141,30 @@ static void chv_load_luts(const struct intel_crtc_state *crtc_state)
 	else
 		i965_load_luts(crtc_state);
 
-	intel_de_write_fw(dev_priv, CGM_PIPE_MODE(crtc->pipe),
+	intel_de_write_fw(i915, CGM_PIPE_MODE(crtc->pipe),
 			  crtc_state->cgm_mode);
 }
 
 void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 
-	dev_priv->display.funcs.color->load_luts(crtc_state);
+	i915->display.funcs.color->load_luts(crtc_state);
 }
 
 void intel_color_commit_noarm(const struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 
-	if (dev_priv->display.funcs.color->color_commit_noarm)
-		dev_priv->display.funcs.color->color_commit_noarm(crtc_state);
+	if (i915->display.funcs.color->color_commit_noarm)
+		i915->display.funcs.color->color_commit_noarm(crtc_state);
 }
 
 void intel_color_commit_arm(const struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 
-	dev_priv->display.funcs.color->color_commit_arm(crtc_state);
+	i915->display.funcs.color->color_commit_arm(crtc_state);
 }
 
 static bool intel_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
@@ -1200,23 +1200,23 @@ static bool chv_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
 
 int intel_color_check(struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 
-	return dev_priv->display.funcs.color->color_check(crtc_state);
+	return i915->display.funcs.color->color_check(crtc_state);
 }
 
 void intel_color_get_config(struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 
-	if (dev_priv->display.funcs.color->read_luts)
-		dev_priv->display.funcs.color->read_luts(crtc_state);
+	if (i915->display.funcs.color->read_luts)
+		i915->display.funcs.color->read_luts(crtc_state);
 }
 
 static bool need_plane_update(struct intel_plane *plane,
 			      const struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+	struct drm_i915_private *i915 = to_i915(plane->base.dev);
 
 	/*
 	 * On pre-SKL the pipe gamma enable and pipe csc enable for
@@ -1224,7 +1224,7 @@ static bool need_plane_update(struct intel_plane *plane,
 	 * We have to reconfigure that even if the plane is inactive.
 	 */
 	return crtc_state->active_planes & BIT(plane->id) ||
-		(DISPLAY_VER(dev_priv) < 9 &&
+		(DISPLAY_VER(i915) < 9 &&
 		 plane->id == PLANE_PRIMARY);
 }
 
@@ -1232,7 +1232,7 @@ static int
 intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 	struct intel_atomic_state *state =
 		to_intel_atomic_state(new_crtc_state->uapi.state);
 	const struct intel_crtc_state *old_crtc_state =
@@ -1247,7 +1247,7 @@ intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state)
 	    new_crtc_state->csc_enable == old_crtc_state->csc_enable)
 		return 0;
 
-	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
+	for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
 		struct intel_plane_state *plane_state;
 
 		if (!need_plane_update(plane, new_crtc_state))
@@ -1260,7 +1260,7 @@ intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state)
 		new_crtc_state->update_planes |= BIT(plane->id);
 
 		/* plane control register changes blocked by CxSR */
-		if (HAS_GMCH(dev_priv))
+		if (HAS_GMCH(i915))
 			new_crtc_state->disable_cxsr = true;
 	}
 
@@ -1286,7 +1286,7 @@ static int check_lut_size(const struct drm_property_blob *lut, int expected)
 
 static int check_luts(const struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
 	const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
 	int gamma_length, degamma_length;
@@ -1298,15 +1298,15 @@ static int check_luts(const struct intel_crtc_state *crtc_state)
 
 	/* C8 relies on its palette being stored in the legacy LUT */
 	if (crtc_state->c8_planes) {
-		drm_dbg_kms(&dev_priv->drm,
+		drm_dbg_kms(&i915->drm,
 			    "C8 pixelformat requires the legacy LUT\n");
 		return -EINVAL;
 	}
 
-	degamma_length = INTEL_INFO(dev_priv)->display.color.degamma_lut_size;
-	gamma_length = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;
-	degamma_tests = INTEL_INFO(dev_priv)->display.color.degamma_lut_tests;
-	gamma_tests = INTEL_INFO(dev_priv)->display.color.gamma_lut_tests;
+	degamma_length = INTEL_INFO(i915)->display.color.degamma_lut_size;
+	gamma_length = INTEL_INFO(i915)->display.color.gamma_lut_size;
+	degamma_tests = INTEL_INFO(i915)->display.color.degamma_lut_tests;
+	gamma_tests = INTEL_INFO(i915)->display.color.gamma_lut_tests;
 
 	if (check_lut_size(degamma_lut, degamma_length) ||
 	    check_lut_size(gamma_lut, gamma_length))
@@ -1550,7 +1550,7 @@ static u32 ivb_csc_mode(const struct intel_crtc_state *crtc_state)
 
 static int ivb_color_check(struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 	bool limited_color_range = ilk_csc_limited_range(crtc_state);
 	int ret;
 
@@ -1560,7 +1560,7 @@ static int ivb_color_check(struct intel_crtc_state *crtc_state)
 
 	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB &&
 	    crtc_state->hw.ctm) {
-		drm_dbg_kms(&dev_priv->drm,
+		drm_dbg_kms(&i915->drm,
 			    "YCBCR and CTM together are not possible\n");
 		return -EINVAL;
 	}
@@ -1617,7 +1617,7 @@ static void glk_assign_luts(struct intel_crtc_state *crtc_state)
 
 static int glk_color_check(struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 	int ret;
 
 	ret = check_luts(crtc_state);
@@ -1626,7 +1626,7 @@ static int glk_color_check(struct intel_crtc_state *crtc_state)
 
 	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB &&
 	    crtc_state->hw.ctm) {
-		drm_dbg_kms(&dev_priv->drm,
+		drm_dbg_kms(&i915->drm,
 			    "YCBCR and CTM together are not possible\n");
 		return -EINVAL;
 	}
@@ -1798,19 +1798,19 @@ static int icl_gamma_precision(const struct intel_crtc_state *crtc_state)
 int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 
-	if (HAS_GMCH(dev_priv)) {
-		if (IS_CHERRYVIEW(dev_priv))
+	if (HAS_GMCH(i915)) {
+		if (IS_CHERRYVIEW(i915))
 			return chv_gamma_precision(crtc_state);
 		else
 			return i9xx_gamma_precision(crtc_state);
 	} else {
-		if (DISPLAY_VER(dev_priv) >= 11)
+		if (DISPLAY_VER(i915) >= 11)
 			return icl_gamma_precision(crtc_state);
-		else if (DISPLAY_VER(dev_priv) == 10)
+		else if (DISPLAY_VER(i915) == 10)
 			return glk_gamma_precision(crtc_state);
-		else if (IS_IRONLAKE(dev_priv))
+		else if (IS_IRONLAKE(i915))
 			return ilk_gamma_precision(crtc_state);
 	}
 
@@ -1966,13 +1966,13 @@ static void i965_read_luts(struct intel_crtc_state *crtc_state)
 
 static struct drm_property_blob *chv_read_cgm_gamma(struct intel_crtc *crtc)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	int i, lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+	int i, lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
 	struct drm_color_lut *lut;
 
-	blob = drm_property_create_blob(&dev_priv->drm,
+	blob = drm_property_create_blob(&i915->drm,
 					sizeof(lut[0]) * lut_size,
 					NULL);
 	if (IS_ERR(blob))
@@ -1981,8 +1981,8 @@ static struct drm_property_blob *chv_read_cgm_gamma(struct intel_crtc *crtc)
 	lut = blob->data;
 
 	for (i = 0; i < lut_size; i++) {
-		u32 ldw = intel_de_read_fw(dev_priv, CGM_PIPE_GAMMA(pipe, i, 0));
-		u32 udw = intel_de_read_fw(dev_priv, CGM_PIPE_GAMMA(pipe, i, 1));
+		u32 ldw = intel_de_read_fw(i915, CGM_PIPE_GAMMA(pipe, i, 0));
+		u32 udw = intel_de_read_fw(i915, CGM_PIPE_GAMMA(pipe, i, 1));
 
 		chv_cgm_gamma_pack(&lut[i], ldw, udw);
 	}
@@ -2002,13 +2002,13 @@ static void chv_read_luts(struct intel_crtc_state *crtc_state)
 
 static struct drm_property_blob *ilk_read_lut_8(struct intel_crtc *crtc)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
 	struct drm_color_lut *lut;
 	int i;
 
-	blob = drm_property_create_blob(&dev_priv->drm,
+	blob = drm_property_create_blob(&i915->drm,
 					sizeof(lut[0]) * LEGACY_LUT_LENGTH,
 					NULL);
 	if (IS_ERR(blob))
@@ -2017,7 +2017,7 @@ static struct drm_property_blob *ilk_read_lut_8(struct intel_crtc *crtc)
 	lut = blob->data;
 
 	for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
-		u32 val = intel_de_read_fw(dev_priv, LGC_PALETTE(pipe, i));
+		u32 val = intel_de_read_fw(i915, LGC_PALETTE(pipe, i));
 
 		i9xx_lut_8_pack(&lut[i], val);
 	}
@@ -2027,13 +2027,13 @@ static struct drm_property_blob *ilk_read_lut_8(struct intel_crtc *crtc)
 
 static struct drm_property_blob *ilk_read_lut_10(struct intel_crtc *crtc)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	int i, lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+	int i, lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
 	struct drm_color_lut *lut;
 
-	blob = drm_property_create_blob(&dev_priv->drm,
+	blob = drm_property_create_blob(&i915->drm,
 					sizeof(lut[0]) * lut_size,
 					NULL);
 	if (IS_ERR(blob))
@@ -2042,7 +2042,7 @@ static struct drm_property_blob *ilk_read_lut_10(struct intel_crtc *crtc)
 	lut = blob->data;
 
 	for (i = 0; i < lut_size; i++) {
-		u32 val = intel_de_read_fw(dev_priv, PREC_PALETTE(pipe, i));
+		u32 val = intel_de_read_fw(i915, PREC_PALETTE(pipe, i));
 
 		ilk_lut_10_pack(&lut[i], val);
 	}
@@ -2077,16 +2077,16 @@ static void ilk_read_luts(struct intel_crtc_state *crtc_state)
 static struct drm_property_blob *bdw_read_lut_10(struct intel_crtc *crtc,
 						 u32 prec_index)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 	int i, hw_lut_size = ivb_lut_10_size(prec_index);
-	int lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;
+	int lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
 	struct drm_color_lut *lut;
 
-	drm_WARN_ON(&dev_priv->drm, lut_size != hw_lut_size);
+	drm_WARN_ON(&i915->drm, lut_size != hw_lut_size);
 
-	blob = drm_property_create_blob(&dev_priv->drm,
+	blob = drm_property_create_blob(&i915->drm,
 					sizeof(lut[0]) * lut_size,
 					NULL);
 	if (IS_ERR(blob))
@@ -2094,16 +2094,16 @@ static struct drm_property_blob *bdw_read_lut_10(struct intel_crtc *crtc,
 
 	lut = blob->data;
 
-	intel_de_write_fw(dev_priv, PREC_PAL_INDEX(pipe),
+	intel_de_write_fw(i915, PREC_PAL_INDEX(pipe),
 			  prec_index | PAL_PREC_AUTO_INCREMENT);
 
 	for (i = 0; i < lut_size; i++) {
-		u32 val = intel_de_read_fw(dev_priv, PREC_PAL_DATA(pipe));
+		u32 val = intel_de_read_fw(i915, PREC_PAL_DATA(pipe));
 
 		ilk_lut_10_pack(&lut[i], val);
 	}
 
-	intel_de_write_fw(dev_priv, PREC_PAL_INDEX(pipe), 0);
+	intel_de_write_fw(i915, PREC_PAL_INDEX(pipe), 0);
 
 	return blob;
 }
@@ -2131,13 +2131,13 @@ static void glk_read_luts(struct intel_crtc_state *crtc_state)
 static struct drm_property_blob *
 icl_read_lut_multi_segment(struct intel_crtc *crtc)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	int i, lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+	int i, lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
 	struct drm_color_lut *lut;
 
-	blob = drm_property_create_blob(&dev_priv->drm,
+	blob = drm_property_create_blob(&i915->drm,
 					sizeof(lut[0]) * lut_size,
 					NULL);
 	if (IS_ERR(blob))
@@ -2145,17 +2145,17 @@ icl_read_lut_multi_segment(struct intel_crtc *crtc)
 
 	lut = blob->data;
 
-	intel_de_write_fw(dev_priv, PREC_PAL_MULTI_SEG_INDEX(pipe),
+	intel_de_write_fw(i915, PREC_PAL_MULTI_SEG_INDEX(pipe),
 			  PAL_PREC_AUTO_INCREMENT);
 
 	for (i = 0; i < 9; i++) {
-		u32 ldw = intel_de_read_fw(dev_priv, PREC_PAL_MULTI_SEG_DATA(pipe));
-		u32 udw = intel_de_read_fw(dev_priv, PREC_PAL_MULTI_SEG_DATA(pipe));
+		u32 ldw = intel_de_read_fw(i915, PREC_PAL_MULTI_SEG_DATA(pipe));
+		u32 udw = intel_de_read_fw(i915, PREC_PAL_MULTI_SEG_DATA(pipe));
 
 		icl_lut_multi_seg_pack(&lut[i], ldw, udw);
 	}
 
-	intel_de_write_fw(dev_priv, PREC_PAL_MULTI_SEG_INDEX(pipe), 0);
+	intel_de_write_fw(i915, PREC_PAL_MULTI_SEG_INDEX(pipe), 0);
 
 	/*
 	 * FIXME readouts from PAL_PREC_DATA register aren't giving
@@ -2268,15 +2268,15 @@ static const struct intel_color_funcs ilk_color_funcs = {
 
 void intel_color_crtc_init(struct intel_crtc *crtc)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	bool has_ctm = INTEL_INFO(dev_priv)->display.color.degamma_lut_size != 0;
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+	bool has_ctm = INTEL_INFO(i915)->display.color.degamma_lut_size != 0;
 
 	drm_mode_crtc_set_gamma_size(&crtc->base, 256);
 
 	drm_crtc_enable_color_mgmt(&crtc->base,
-				   INTEL_INFO(dev_priv)->display.color.degamma_lut_size,
+				   INTEL_INFO(i915)->display.color.degamma_lut_size,
 				   has_ctm,
-				   INTEL_INFO(dev_priv)->display.color.gamma_lut_size);
+				   INTEL_INFO(i915)->display.color.gamma_lut_size);
 }
 
 int intel_color_init(struct drm_i915_private *i915)
-- 
2.37.4

[Intel-gfx] [PATCH 04/11] drm/i915: s/icl_load_gcmax/ivb_load_lut_max/

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Unify icl_load_gcmax() with the rest of the function
naming scheme by calling it ivb_load_lut_max() instead.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 415e0a6839a4..e73e6ea6f82f 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -935,8 +935,8 @@ static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color)
 }
 
 static void
-icl_load_gcmax(const struct intel_crtc_state *crtc_state,
-	       const struct drm_color_lut *color)
+ivb_load_lut_max(const struct intel_crtc_state *crtc_state,
+		 const struct drm_color_lut *color)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum pipe pipe = crtc->pipe;
@@ -1028,7 +1028,7 @@ icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)
 
 	/* The last entry in the LUT is to be programmed in GCMAX */
 	entry = &lut[256 * 8 * 128];
-	icl_load_gcmax(crtc_state, entry);
+	ivb_load_lut_max(crtc_state, entry);
 	ivb_load_lut_ext_max(crtc_state);
 }
 
-- 
2.37.4

[Intel-gfx] [PATCH 05/11] drm/i915: Split ivb_load_lut_ext_max() into two parts

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Split the EXT2_MAX register progrmaming into its own funciton.
More in line with the whole "cobble together stuff from small
pieces" approach used in this code.

The EXT(2)_MAX registers are also not really part of the
multi-segment section of the LUT, so hoise the calls to a
higher level, just like we do in other gamma modes as well.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 29 +++++++++++-----------
 1 file changed, 14 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index e73e6ea6f82f..3b78b882e0c0 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -764,27 +764,23 @@ static void bdw_load_lut_10(struct intel_crtc *crtc,
 static void ivb_load_lut_ext_max(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 
 	/* Program the max register to clamp values > 1.0. */
 	intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16);
 	intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16);
 	intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16);
+}
 
-	/*
-	 * Program the gc max 2 register to clamp values > 1.0.
-	 * ToDo: Extend the ABI to be able to program values
-	 * from 3.0 to 7.0
-	 */
-	if (DISPLAY_VER(i915) >= 10) {
-		intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 0),
-				    1 << 16);
-		intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 1),
-				    1 << 16);
-		intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 2),
-				    1 << 16);
-	}
+static void glk_load_lut_ext2_max(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	enum pipe pipe = crtc->pipe;
+
+	/* Program the max register to clamp values > 1.0. */
+	intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 0), 1 << 16);
+	intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 1), 1 << 16);
+	intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 2), 1 << 16);
 }
 
 static void ivb_load_luts(const struct intel_crtc_state *crtc_state)
@@ -913,6 +909,7 @@ static void glk_load_luts(const struct intel_crtc_state *crtc_state)
 	case GAMMA_MODE_MODE_10BIT:
 		bdw_load_lut_10(crtc, post_csc_lut, PAL_PREC_INDEX_VALUE(0));
 		ivb_load_lut_ext_max(crtc_state);
+		glk_load_lut_ext2_max(crtc_state);
 		break;
 	default:
 		MISSING_CASE(crtc_state->gamma_mode);
@@ -1029,7 +1026,6 @@ icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)
 	/* The last entry in the LUT is to be programmed in GCMAX */
 	entry = &lut[256 * 8 * 128];
 	ivb_load_lut_max(crtc_state, entry);
-	ivb_load_lut_ext_max(crtc_state);
 }
 
 static void icl_load_luts(const struct intel_crtc_state *crtc_state)
@@ -1048,10 +1044,13 @@ static void icl_load_luts(const struct intel_crtc_state *crtc_state)
 	case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
 		icl_program_gamma_superfine_segment(crtc_state);
 		icl_program_gamma_multi_segment(crtc_state);
+		ivb_load_lut_ext_max(crtc_state);
+		glk_load_lut_ext2_max(crtc_state);
 		break;
 	case GAMMA_MODE_MODE_10BIT:
 		bdw_load_lut_10(crtc, post_csc_lut, PAL_PREC_INDEX_VALUE(0));
 		ivb_load_lut_ext_max(crtc_state);
+		glk_load_lut_ext2_max(crtc_state);
 		break;
 	default:
 		MISSING_CASE(crtc_state->gamma_mode);
-- 
2.37.4

[Intel-gfx] [PATCH 06/11] drm/i915: Deconfuse the ilk+ 12.4 LUT entry functions

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

s/icl_lut_multi_seg_pack/ilk_lut_12p4_pack/ since that's what it is
and group the corresponding "unpack" functions next to it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 38 +++++++++++-----------
 1 file changed, 19 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 3b78b882e0c0..e881c95ee451 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -482,14 +482,28 @@ static void ilk_lut_10_pack(struct drm_color_lut *entry, u32 val)
 	entry->blue = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_BLUE_MASK, val), 10);
 }
 
-static void icl_lut_multi_seg_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)
+/* ilk+ "12.4" interpolated format (high 10 bits) */
+static u32 ilk_lut_12p4_udw(const struct drm_color_lut *color)
+{
+	return (color->red >> 6) << 20 | (color->green >> 6) << 10 |
+		(color->blue >> 6);
+}
+
+/* ilk+ "12.4" interpolated format (low 6 bits) */
+static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color)
+{
+	return (color->red & 0x3f) << 24 | (color->green & 0x3f) << 14 |
+		(color->blue & 0x3f) << 4;
+}
+
+static void ilk_lut_12p4_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)
 {
 	entry->red = REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK, udw) << 6 |
-				   REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_LDW_MASK, ldw);
+		REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_LDW_MASK, ldw);
 	entry->green = REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, udw) << 6 |
-				     REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, ldw);
+		REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, ldw);
 	entry->blue = REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK, udw) << 6 |
-				    REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, ldw);
+		REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, ldw);
 }
 
 static void icl_color_commit_noarm(const struct intel_crtc_state *crtc_state)
@@ -917,20 +931,6 @@ static void glk_load_luts(const struct intel_crtc_state *crtc_state)
 	}
 }
 
-/* ilk+ "12.4" interpolated format (high 10 bits) */
-static u32 ilk_lut_12p4_udw(const struct drm_color_lut *color)
-{
-	return (color->red >> 6) << 20 | (color->green >> 6) << 10 |
-		(color->blue >> 6);
-}
-
-/* ilk+ "12.4" interpolated format (low 6 bits) */
-static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color)
-{
-	return (color->red & 0x3f) << 24 | (color->green & 0x3f) << 14 |
-		(color->blue & 0x3f) << 4;
-}
-
 static void
 ivb_load_lut_max(const struct intel_crtc_state *crtc_state,
 		 const struct drm_color_lut *color)
@@ -2151,7 +2151,7 @@ icl_read_lut_multi_segment(struct intel_crtc *crtc)
 		u32 ldw = intel_de_read_fw(i915, PREC_PAL_MULTI_SEG_DATA(pipe));
 		u32 udw = intel_de_read_fw(i915, PREC_PAL_MULTI_SEG_DATA(pipe));
 
-		icl_lut_multi_seg_pack(&lut[i], ldw, udw);
+		ilk_lut_12p4_pack(&lut[i], ldw, udw);
 	}
 
 	intel_de_write_fw(i915, PREC_PAL_MULTI_SEG_INDEX(pipe), 0);
-- 
2.37.4

[Intel-gfx] [PATCH 07/11] drm/i915: Pass limited_range explicitly to ilk_csc_convert_ctm()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Since pre-icl vs. icl+ handle the limited range
output stuff a bit differently it's probably
less confusing if we just pass that information
explicitly into ilk_csc_convert_ctm().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index e881c95ee451..946fb767f3e0 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -259,14 +259,14 @@ static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state)
 }
 
 static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
-				u16 coeffs[9])
+				u16 coeffs[9], bool limited_color_range)
 {
 	const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
 	const u64 *input;
 	u64 temp[9];
 	int i;
 
-	if (ilk_csc_limited_range(crtc_state))
+	if (limited_color_range)
 		input = ctm_mult_by_limited(temp, ctm->matrix);
 	else
 		input = ctm->matrix;
@@ -319,7 +319,7 @@ static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
 	if (crtc_state->hw.ctm) {
 		u16 coeff[9];
 
-		ilk_csc_convert_ctm(crtc_state, coeff);
+		ilk_csc_convert_ctm(crtc_state, coeff, limited_color_range);
 		ilk_update_pipe_csc(crtc, ilk_csc_off_zero, coeff,
 				    limited_color_range ?
 				    ilk_csc_postoff_limited_range :
@@ -354,7 +354,7 @@ static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state)
 	if (crtc_state->hw.ctm) {
 		u16 coeff[9];
 
-		ilk_csc_convert_ctm(crtc_state, coeff);
+		ilk_csc_convert_ctm(crtc_state, coeff, false);
 		ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
 				    coeff, ilk_csc_off_zero);
 	}
-- 
2.37.4

[Intel-gfx] [PATCH 08/11] drm/i915: Reuse ilk_gamma_mode() on ivb+

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Apart from the split gamma mode ivb+ LUTs work just like ilk+ LUTs.
So let's handle the special case, and then just fall back to
ilk_gamma_mode() to avoid having to duplicate the same logic.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 10 +++-------
 1 file changed, 3 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 946fb767f3e0..435394cad359 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1521,14 +1521,10 @@ static int ilk_color_check(struct intel_crtc_state *crtc_state)
 
 static u32 ivb_gamma_mode(const struct intel_crtc_state *crtc_state)
 {
-	if (!crtc_state->gamma_enable ||
-	    crtc_state_is_legacy_gamma(crtc_state))
-		return GAMMA_MODE_MODE_8BIT;
-	else if (crtc_state->hw.gamma_lut &&
-		 crtc_state->hw.degamma_lut)
+	if (crtc_state->hw.degamma_lut && crtc_state->hw.gamma_lut)
 		return GAMMA_MODE_MODE_SPLIT;
-	else
-		return GAMMA_MODE_MODE_10BIT;
+
+	return ilk_gamma_mode(crtc_state);
 }
 
 static u32 ivb_csc_mode(const struct intel_crtc_state *crtc_state)
-- 
2.37.4

[Intel-gfx] [PATCH 09/11] drm/i915: Reject YCbCr output with degamma+gamma on pre-icl

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Since the pipe CSC sits between the degamma and gamma LUTs there
is no way to make us it for RGB->YCbCr conversion when both LUTs
are also active. Simply reject such combos.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 18 ++++++++++++++++--
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 435394cad359..926784f266f2 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1556,7 +1556,14 @@ static int ivb_color_check(struct intel_crtc_state *crtc_state)
 	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB &&
 	    crtc_state->hw.ctm) {
 		drm_dbg_kms(&i915->drm,
-			    "YCBCR and CTM together are not possible\n");
+			    "YCbCr and CTM together are not possible\n");
+		return -EINVAL;
+	}
+
+	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB &&
+	    crtc_state->hw.degamma_lut && crtc_state->hw.gamma_lut) {
+		drm_dbg_kms(&i915->drm,
+			    "YCbCr and degamma+gamma together are not possible\n");
 		return -EINVAL;
 	}
 
@@ -1622,7 +1629,14 @@ static int glk_color_check(struct intel_crtc_state *crtc_state)
 	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB &&
 	    crtc_state->hw.ctm) {
 		drm_dbg_kms(&i915->drm,
-			    "YCBCR and CTM together are not possible\n");
+			    "YCbCr and CTM together are not possible\n");
+		return -EINVAL;
+	}
+
+	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB &&
+	    crtc_state->hw.degamma_lut && crtc_state->hw.gamma_lut) {
+		drm_dbg_kms(&i915->drm,
+			    "YCbCr and degamma+gamma together are not possible\n");
 		return -EINVAL;
 	}
 
-- 
2.37.4

[Intel-gfx] [PATCH 10/11] drm/i915: Share {csc, gamma}_enable calculation for ilk/snb vs. ivb+

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

ilk/snb vs. ivb+ hardware is mostly identical except for the addition
of the split gamma mode on ivb. Thus we can share the csc_enable
and gamma_enable calculation for both variants. Pull that stuff
into a few helpers.

Note that this also fills in the missing ctm/degamma stuff into
ilk_color_check() pretty much, so for good measure let's also
add a few extra checks relating to that, although we still don't
expose ctm/degamma to userspace. But now it'll be trivial to do
so if we wish.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 49 ++++++++++++++--------
 1 file changed, 32 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 926784f266f2..33871bfacee7 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1442,6 +1442,20 @@ static int chv_color_check(struct intel_crtc_state *crtc_state)
 	return 0;
 }
 
+static bool ilk_gamma_enable(const struct intel_crtc_state *crtc_state)
+{
+	return (crtc_state->hw.gamma_lut ||
+		crtc_state->hw.degamma_lut) &&
+		!crtc_state->c8_planes;
+}
+
+static bool ilk_csc_enable(const struct intel_crtc_state *crtc_state)
+{
+	return crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
+		ilk_csc_limited_range(crtc_state) ||
+		crtc_state->hw.ctm;
+}
+
 static u32 ilk_gamma_mode(const struct intel_crtc_state *crtc_state)
 {
 	if (!crtc_state->gamma_enable ||
@@ -1487,22 +1501,29 @@ static void ilk_assign_luts(struct intel_crtc_state *crtc_state)
 
 static int ilk_color_check(struct intel_crtc_state *crtc_state)
 {
+	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 	int ret;
 
 	ret = check_luts(crtc_state);
 	if (ret)
 		return ret;
 
-	crtc_state->gamma_enable =
-		crtc_state->hw.gamma_lut &&
-		!crtc_state->c8_planes;
+	if (crtc_state->hw.degamma_lut && crtc_state->hw.gamma_lut) {
+		drm_dbg_kms(&i915->drm,
+			    "Degamma and gamma together are not possible\n");
+		return -EINVAL;
+	}
 
-	/*
-	 * We don't expose the ctm on ilk/snb currently, also RGB
-	 * limited range output is handled by the hw automagically.
-	 */
-	crtc_state->csc_enable =
-		crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB;
+	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB &&
+	    crtc_state->hw.ctm) {
+		drm_dbg_kms(&i915->drm,
+			    "YCbCr and CTM together are not possible\n");
+		return -EINVAL;
+	}
+
+	crtc_state->gamma_enable = ilk_gamma_enable(crtc_state);
+
+	crtc_state->csc_enable = ilk_csc_enable(crtc_state);
 
 	crtc_state->gamma_mode = ilk_gamma_mode(crtc_state);
 
@@ -1546,7 +1567,6 @@ static u32 ivb_csc_mode(const struct intel_crtc_state *crtc_state)
 static int ivb_color_check(struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
-	bool limited_color_range = ilk_csc_limited_range(crtc_state);
 	int ret;
 
 	ret = check_luts(crtc_state);
@@ -1567,14 +1587,9 @@ static int ivb_color_check(struct intel_crtc_state *crtc_state)
 		return -EINVAL;
 	}
 
-	crtc_state->gamma_enable =
-		(crtc_state->hw.gamma_lut ||
-		 crtc_state->hw.degamma_lut) &&
-		!crtc_state->c8_planes;
+	crtc_state->gamma_enable = ilk_gamma_enable(crtc_state);
 
-	crtc_state->csc_enable =
-		crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
-		crtc_state->hw.ctm || limited_color_range;
+	crtc_state->csc_enable = ilk_csc_enable(crtc_state);
 
 	crtc_state->gamma_mode = ivb_gamma_mode(crtc_state);
 
-- 
2.37.4

[Intel-gfx] [PATCH 11/11] drm/i915: Create resized LUTs for ivb+ split gamma mode

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Currently when opeating in split gamma mode we do the
"skip ever other sw LUT entry" trick in the low level
LUT programming/readout functions. That is very annoying
and a big hinderance to revamping the color management
uapi.

Let's get rid of that problem by making half sized copies
of the software LUTs and plugging those into the internal
{pre,post}_csc_lut attachment points (instead of the sticking
the uapi provide sw LUTs there directly).

With this the low level stuff will operate purely in terms
the hardware LUT sizes, and all uapi nonsense is contained
to the atomic check phase. The one thing we do lose is
intel_color_assert_luts() since we no longer have a way to
check that the uapi LUTs were correctly used when generating
the internal copies. But that seems like a price worth paying.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 81 +++++++++++++++++-----
 1 file changed, 64 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 33871bfacee7..d48904f90e3a 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -597,6 +597,30 @@ create_linear_lut(struct drm_i915_private *i915, int lut_size)
 	return blob;
 }
 
+static struct drm_property_blob *
+create_resized_lut(struct drm_i915_private *i915,
+		   const struct drm_property_blob *blob_in, int lut_out_size)
+{
+	int i, lut_in_size = drm_color_lut_size(blob_in);
+	struct drm_property_blob *blob_out;
+	const struct drm_color_lut *lut_in;
+	struct drm_color_lut *lut_out;
+
+	blob_out = drm_property_create_blob(&i915->drm,
+					    sizeof(lut_out[0]) * lut_out_size,
+					    NULL);
+	if (IS_ERR(blob_out))
+		return blob_out;
+
+	lut_in = blob_in->data;
+	lut_out = blob_out->data;
+
+	for (i = 0; i < lut_out_size; i++)
+		lut_out[i] = lut_in[i * (lut_in_size - 1) / (lut_out_size - 1)];
+
+	return blob_out;
+}
+
 static void i9xx_load_lut_8(struct intel_crtc *crtc,
 			    const struct drm_property_blob *blob)
 {
@@ -723,19 +747,14 @@ static void ivb_load_lut_10(struct intel_crtc *crtc,
 			    u32 prec_index)
 {
 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
-	int hw_lut_size = ivb_lut_10_size(prec_index);
 	const struct drm_color_lut *lut = blob->data;
 	int i, lut_size = drm_color_lut_size(blob);
 	enum pipe pipe = crtc->pipe;
 
-	for (i = 0; i < hw_lut_size; i++) {
-		/* We discard half the user entries in split gamma mode */
-		const struct drm_color_lut *entry =
-			&lut[i * (lut_size - 1) / (hw_lut_size - 1)];
-
+	for (i = 0; i < lut_size; i++) {
 		intel_de_write_fw(i915, PREC_PAL_INDEX(pipe), prec_index++);
 		intel_de_write_fw(i915, PREC_PAL_DATA(pipe),
-				  ilk_lut_10(entry));
+				  ilk_lut_10(&lut[i]));
 	}
 
 	/*
@@ -751,7 +770,6 @@ static void bdw_load_lut_10(struct intel_crtc *crtc,
 			    u32 prec_index)
 {
 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
-	int hw_lut_size = ivb_lut_10_size(prec_index);
 	const struct drm_color_lut *lut = blob->data;
 	int i, lut_size = drm_color_lut_size(blob);
 	enum pipe pipe = crtc->pipe;
@@ -759,14 +777,9 @@ static void bdw_load_lut_10(struct intel_crtc *crtc,
 	intel_de_write_fw(i915, PREC_PAL_INDEX(pipe),
 			  prec_index | PAL_PREC_AUTO_INCREMENT);
 
-	for (i = 0; i < hw_lut_size; i++) {
-		/* We discard half the user entries in split gamma mode */
-		const struct drm_color_lut *entry =
-			&lut[i * (lut_size - 1) / (hw_lut_size - 1)];
-
+	for (i = 0; i < lut_size; i++)
 		intel_de_write_fw(i915, PREC_PAL_DATA(pipe),
-				  ilk_lut_10(entry));
-	}
+				  ilk_lut_10(&lut[i]));
 
 	/*
 	 * Reset the index, otherwise it prevents the legacy palette to be
@@ -1343,7 +1356,7 @@ void intel_color_assert_luts(const struct intel_crtc_state *crtc_state)
 			    crtc_state->pre_csc_lut != i915->display.color.glk_linear_degamma_lut);
 		drm_WARN_ON(&i915->drm,
 			    crtc_state->post_csc_lut != crtc_state->hw.gamma_lut);
-	} else {
+	} else if (crtc_state->gamma_mode != GAMMA_MODE_MODE_SPLIT) {
 		drm_WARN_ON(&i915->drm,
 			    crtc_state->pre_csc_lut != crtc_state->hw.degamma_lut &&
 			    crtc_state->pre_csc_lut != crtc_state->hw.gamma_lut);
@@ -1564,6 +1577,38 @@ static u32 ivb_csc_mode(const struct intel_crtc_state *crtc_state)
 	return CSC_POSITION_BEFORE_GAMMA;
 }
 
+static int ivb_assign_luts(struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+	struct drm_property_blob *degamma_lut, *gamma_lut;
+
+	if (crtc_state->gamma_mode != GAMMA_MODE_MODE_SPLIT) {
+		ilk_assign_luts(crtc_state);
+		return 0;
+	}
+
+	drm_WARN_ON(&i915->drm, drm_color_lut_size(crtc_state->hw.degamma_lut) != 1024);
+	drm_WARN_ON(&i915->drm, drm_color_lut_size(crtc_state->hw.gamma_lut) != 1024);
+
+	degamma_lut = create_resized_lut(i915, crtc_state->hw.degamma_lut, 512);
+	if (IS_ERR(degamma_lut))
+		return PTR_ERR(degamma_lut);
+
+	gamma_lut = create_resized_lut(i915, crtc_state->hw.gamma_lut, 512);
+	if (IS_ERR(gamma_lut)) {
+		drm_property_blob_put(degamma_lut);
+		return PTR_ERR(gamma_lut);
+	}
+
+	drm_property_replace_blob(&crtc_state->pre_csc_lut, degamma_lut);
+	drm_property_replace_blob(&crtc_state->post_csc_lut, gamma_lut);
+
+	drm_property_blob_put(degamma_lut);
+	drm_property_blob_put(gamma_lut);
+
+	return 0;
+}
+
 static int ivb_color_check(struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
@@ -1599,7 +1644,9 @@ static int ivb_color_check(struct intel_crtc_state *crtc_state)
 	if (ret)
 		return ret;
 
-	ilk_assign_luts(crtc_state);
+	ret = ivb_assign_luts(crtc_state);
+	if (ret)
+		return ret;
 
 	crtc_state->preload_luts = intel_can_preload_luts(crtc_state);
 
-- 
2.37.4

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: More gamma work

[Patchwork]

== Series Details ==

Series: drm/i915: More gamma work
URL   : https://patchwork.freedesktop.org/series/110168/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: More gamma work

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 7401 bytes --]

== Series Details ==

Series: drm/i915: More gamma work
URL   : https://patchwork.freedesktop.org/series/110168/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12296 -> Patchwork_110168v1
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/index.html

Participating hosts (41 -> 38)
------------------------------

  Missing    (3): fi-kbl-soraka fi-ctg-p8600 bat-atsm-1 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_110168v1:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-dp-3:
    - {bat-dg2-9}:        [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/bat-dg2-9/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-dp-3.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/bat-dg2-9/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-dp-3.html

  
Known issues
------------

  Here are the changes found in Patchwork_110168v1 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_lmem_swapping@basic:
    - fi-apl-guc:         NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613]) +3 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/fi-apl-guc/igt@gem_lmem_swapping@basic.html

  * igt@i915_selftest@live@hangcheck:
    - fi-hsw-4770:        [PASS][4] -> [INCOMPLETE][5] ([i915#4785])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html

  * igt@kms_chamelium@hdmi-crc-fast:
    - fi-apl-guc:         NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/fi-apl-guc/igt@kms_chamelium@hdmi-crc-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size:
    - fi-bsw-kefka:       [PASS][7] -> [FAIL][8] ([i915#6298])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size.html

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-edp-1:
    - fi-skl-6600u:       [PASS][9] -> [FAIL][10] ([fdo#103375])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/fi-skl-6600u/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-edp-1.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/fi-skl-6600u/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-edp-1.html

  * igt@kms_psr@sprite_plane_onoff:
    - fi-apl-guc:         NOTRUN -> [SKIP][11] ([fdo#109271]) +11 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/fi-apl-guc/igt@kms_psr@sprite_plane_onoff.html

  * igt@runner@aborted:
    - fi-hsw-4770:        NOTRUN -> [FAIL][12] ([fdo#109271] / [i915#4312] / [i915#5594])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/fi-hsw-4770/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s0@smem:
    - {bat-adlm-1}:       [DMESG-WARN][13] ([i915#2867]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/bat-adlm-1/igt@gem_exec_suspend@basic-s0@smem.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/bat-adlm-1/igt@gem_exec_suspend@basic-s0@smem.html

  * igt@i915_hangman@error-state-basic:
    - fi-apl-guc:         [DMESG-WARN][15] -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/fi-apl-guc/igt@i915_hangman@error-state-basic.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/fi-apl-guc/igt@i915_hangman@error-state-basic.html

  * igt@i915_selftest@live@gt_pm:
    - {bat-adln-1}:       [DMESG-FAIL][17] ([i915#4258]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/bat-adln-1/igt@i915_selftest@live@gt_pm.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/bat-adln-1/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@reset:
    - {bat-rpls-1}:       [DMESG-FAIL][19] ([i915#4983] / [i915#5828]) -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/bat-rpls-1/igt@i915_selftest@live@reset.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/bat-rpls-1/igt@i915_selftest@live@reset.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
  [i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#5278]: https://gitlab.freedesktop.org/drm/intel/issues/5278
  [i915#5594]: https://gitlab.freedesktop.org/drm/intel/issues/5594
  [i915#5828]: https://gitlab.freedesktop.org/drm/intel/issues/5828
  [i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298
  [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
  [i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997


Build changes
-------------

  * Linux: CI_DRM_12296 -> Patchwork_110168v1

  CI-20190529: 20190529
  CI_DRM_12296: dc5600688adfc13fed8128d9043bab2257066646 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7026: ce0f97e7e0aa54c40049a8365b3d61773c92e588 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_110168v1: dc5600688adfc13fed8128d9043bab2257066646 @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

22a908c96724 drm/i915: Create resized LUTs for ivb+ split gamma mode
637c410fdb44 drm/i915: Share {csc, gamma}_enable calculation for ilk/snb vs. ivb+
c3196fd2be9a drm/i915: Reject YCbCr output with degamma+gamma on pre-icl
54c8a1ec82ae drm/i915: Reuse ilk_gamma_mode() on ivb+
69fbd1cb5687 drm/i915: Pass limited_range explicitly to ilk_csc_convert_ctm()
d99a7abbb293 drm/i915: Deconfuse the ilk+ 12.4 LUT entry functions
865c656d61bd drm/i915: Split ivb_load_lut_ext_max() into two parts
07cdbf833cb0 drm/i915: s/icl_load_gcmax/ivb_load_lut_max/
ad551f5f02e8 drm/i915: s/dev_priv/i915/ in intel_color.c
07d9c13d1d72 drm/i915: Use _MMIO_PIPE() for SKL_BOTTOM_COLOR
c9a68ad447f3 drm/i915: Use sizeof(variable) instead sizeof(type)

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/index.html

[-- Attachment #2: Type: text/html, Size: 8290 bytes --]

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: More gamma work

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 41049 bytes --]

== Series Details ==

Series: drm/i915: More gamma work
URL   : https://patchwork.freedesktop.org/series/110168/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12296_full -> Patchwork_110168v1_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (9 -> 11)
------------------------------

  Additional (2): shard-rkl shard-dg1 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_110168v1_full:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_suspend@basic-s3-without-i915:
    - {shard-rkl}:        NOTRUN -> [INCOMPLETE][1] +1 similar issue
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-rkl-5/igt@i915_suspend@basic-s3-without-i915.html

  * igt@sysfs_timeslice_duration@idempotent@vcs0:
    - {shard-dg1}:        NOTRUN -> [FAIL][2] +9 similar issues
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-dg1-18/igt@sysfs_timeslice_duration@idempotent@vcs0.html

  
Known issues
------------

  Here are the changes found in Patchwork_110168v1_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@drm_mm@all:
    - shard-iclb:         NOTRUN -> [SKIP][3] ([i915#6433])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-iclb2/igt@drm_mm@all.html

  * igt@feature_discovery@display-3x:
    - shard-iclb:         NOTRUN -> [SKIP][4] ([i915#1839])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-iclb2/igt@feature_discovery@display-3x.html

  * igt@gem_ccs@suspend-resume:
    - shard-tglb:         NOTRUN -> [SKIP][5] ([i915#5325])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-tglb3/igt@gem_ccs@suspend-resume.html

  * igt@gem_ctx_exec@basic-nohangcheck:
    - shard-tglb:         [PASS][6] -> [FAIL][7] ([i915#6268])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-tglb6/igt@gem_ctx_exec@basic-nohangcheck.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-tglb2/igt@gem_ctx_exec@basic-nohangcheck.html

  * igt@gem_ctx_persistence@many-contexts:
    - shard-tglb:         [PASS][8] -> [FAIL][9] ([i915#2410])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-tglb6/igt@gem_ctx_persistence@many-contexts.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-tglb1/igt@gem_ctx_persistence@many-contexts.html

  * igt@gem_exec_fair@basic-pace@bcs0:
    - shard-tglb:         [PASS][10] -> [FAIL][11] ([i915#2842]) +1 similar issue
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-tglb6/igt@gem_exec_fair@basic-pace@bcs0.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-tglb2/igt@gem_exec_fair@basic-pace@bcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
    - shard-iclb:         NOTRUN -> [FAIL][12] ([i915#2842])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-iclb2/igt@gem_exec_fair@basic-throttle@rcs0.html

  * igt@gem_exec_params@no-vebox:
    - shard-iclb:         NOTRUN -> [SKIP][13] ([fdo#109283])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-iclb2/igt@gem_exec_params@no-vebox.html

  * igt@gem_exec_whisper@basic-fds-priority:
    - shard-skl:          [PASS][14] -> [DMESG-WARN][15] ([i915#1982])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-skl1/igt@gem_exec_whisper@basic-fds-priority.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-skl6/igt@gem_exec_whisper@basic-fds-priority.html

  * igt@gem_pxp@create-regular-context-1:
    - shard-iclb:         NOTRUN -> [SKIP][16] ([i915#4270])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-iclb2/igt@gem_pxp@create-regular-context-1.html

  * igt@gem_userptr_blits@input-checking:
    - shard-skl:          NOTRUN -> [DMESG-WARN][17] ([i915#4991])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-skl10/igt@gem_userptr_blits@input-checking.html

  * igt@gen7_exec_parse@load-register-reg:
    - shard-iclb:         NOTRUN -> [SKIP][18] ([fdo#109289])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-iclb2/igt@gen7_exec_parse@load-register-reg.html

  * igt@gen7_exec_parse@oacontrol-tracking:
    - shard-apl:          NOTRUN -> [SKIP][19] ([fdo#109271]) +36 similar issues
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-apl8/igt@gen7_exec_parse@oacontrol-tracking.html

  * igt@gen9_exec_parse@allowed-single:
    - shard-apl:          [PASS][20] -> [DMESG-WARN][21] ([i915#5566] / [i915#716])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-apl2/igt@gen9_exec_parse@allowed-single.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-apl2/igt@gen9_exec_parse@allowed-single.html

  * igt@gen9_exec_parse@bb-large:
    - shard-iclb:         NOTRUN -> [SKIP][22] ([i915#2856])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-iclb2/igt@gen9_exec_parse@bb-large.html

  * igt@i915_pm_dc@dc6-dpms:
    - shard-iclb:         [PASS][23] -> [FAIL][24] ([i915#3989] / [i915#454])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-iclb7/igt@i915_pm_dc@dc6-dpms.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html

  * igt@i915_pm_dc@dc9-dpms:
    - shard-iclb:         [PASS][25] -> [SKIP][26] ([i915#4281])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-iclb7/igt@i915_pm_dc@dc9-dpms.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-iclb3/igt@i915_pm_dc@dc9-dpms.html

  * igt@i915_pm_rc6_residency@rc6-idle@vcs0:
    - shard-iclb:         NOTRUN -> [WARN][27] ([i915#2684]) +3 similar issues
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-iclb2/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
    - shard-skl:          [PASS][28] -> [WARN][29] ([i915#1804])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-skl9/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-skl1/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html

  * igt@i915_pm_rps@engine-order:
    - shard-apl:          [PASS][30] -> [FAIL][31] ([i915#6537])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-apl6/igt@i915_pm_rps@engine-order.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-apl7/igt@i915_pm_rps@engine-order.html

  * igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1:
    - shard-skl:          [PASS][32] -> [FAIL][33] ([i915#2521])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-skl10/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-skl9/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html

  * igt@kms_atomic@atomic_plane_damage:
    - shard-iclb:         NOTRUN -> [SKIP][34] ([i915#4765])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-iclb2/igt@kms_atomic@atomic_plane_damage.html

  * igt@kms_big_fb@4-tiled-16bpp-rotate-180:
    - shard-iclb:         NOTRUN -> [SKIP][35] ([i915#5286])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-iclb2/igt@kms_big_fb@4-tiled-16bpp-rotate-180.html

  * igt@kms_big_fb@4-tiled-32bpp-rotate-180:
    - shard-tglb:         NOTRUN -> [SKIP][36] ([i915#5286])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-tglb3/igt@kms_big_fb@4-tiled-32bpp-rotate-180.html

  * igt@kms_big_fb@linear-16bpp-rotate-270:
    - shard-tglb:         NOTRUN -> [SKIP][37] ([fdo#111614])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-tglb3/igt@kms_big_fb@linear-16bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-32bpp-rotate-180:
    - shard-glk:          [PASS][38] -> [DMESG-FAIL][39] ([i915#118] / [i915#5138])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-glk3/igt@kms_big_fb@y-tiled-32bpp-rotate-180.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-glk5/igt@kms_big_fb@y-tiled-32bpp-rotate-180.html

  * igt@kms_big_fb@yf-tiled-16bpp-rotate-180:
    - shard-tglb:         NOTRUN -> [SKIP][40] ([fdo#111615]) +1 similar issue
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-tglb3/igt@kms_big_fb@yf-tiled-16bpp-rotate-180.html

  * igt@kms_big_joiner@2x-modeset:
    - shard-iclb:         NOTRUN -> [SKIP][41] ([i915#2705])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-iclb2/igt@kms_big_joiner@2x-modeset.html

  * igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs:
    - shard-iclb:         NOTRUN -> [SKIP][42] ([fdo#109278]) +3 similar issues
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-iclb2/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs.html

  * igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
    - shard-skl:          NOTRUN -> [SKIP][43] ([fdo#109271] / [i915#3886]) +2 similar issues
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-skl5/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][44] ([i915#3689] / [i915#3886]) +1 similar issue
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-tglb3/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
    - shard-iclb:         NOTRUN -> [SKIP][45] ([fdo#109278] / [i915#3886]) +2 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-iclb2/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-b-crc-sprite-planes-basic-4_tiled_dg2_rc_ccs_cc:
    - shard-tglb:         NOTRUN -> [SKIP][46] ([i915#3689] / [i915#6095])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-tglb3/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-4_tiled_dg2_rc_ccs_cc.html

  * igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
    - shard-apl:          NOTRUN -> [SKIP][47] ([fdo#109271] / [i915#3886])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-apl8/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-c-ccs-on-another-bo-yf_tiled_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][48] ([fdo#111615] / [i915#3689])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-tglb3/igt@kms_ccs@pipe-c-ccs-on-another-bo-yf_tiled_ccs.html

  * igt@kms_ccs@pipe-d-crc-primary-rotation-180-4_tiled_dg2_mc_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][49] ([i915#3689])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-tglb3/igt@kms_ccs@pipe-d-crc-primary-rotation-180-4_tiled_dg2_mc_ccs.html

  * igt@kms_chamelium@dp-hpd-for-each-pipe:
    - shard-iclb:         NOTRUN -> [SKIP][50] ([fdo#109284] / [fdo#111827]) +1 similar issue
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-iclb2/igt@kms_chamelium@dp-hpd-for-each-pipe.html

  * igt@kms_chamelium@hdmi-hpd-storm:
    - shard-skl:          NOTRUN -> [SKIP][51] ([fdo#109271] / [fdo#111827]) +1 similar issue
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-skl5/igt@kms_chamelium@hdmi-hpd-storm.html

  * igt@kms_color_chamelium@ctm-blue-to-red:
    - shard-apl:          NOTRUN -> [SKIP][52] ([fdo#109271] / [fdo#111827]) +1 similar issue
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-apl8/igt@kms_color_chamelium@ctm-blue-to-red.html

  * igt@kms_content_protection@uevent:
    - shard-tglb:         NOTRUN -> [SKIP][53] ([i915#6944] / [i915#7118])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-tglb3/igt@kms_content_protection@uevent.html

  * igt@kms_cursor_crc@cursor-random-512x170:
    - shard-tglb:         NOTRUN -> [SKIP][54] ([i915#3359])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-tglb3/igt@kms_cursor_crc@cursor-random-512x170.html

  * igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic:
    - shard-tglb:         NOTRUN -> [SKIP][55] ([fdo#109274] / [fdo#111825]) +1 similar issue
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-tglb3/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html

  * igt@kms_dsc@dsc-with-bpc-formats:
    - shard-skl:          NOTRUN -> [SKIP][56] ([fdo#109271] / [i915#7205])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-skl5/igt@kms_dsc@dsc-with-bpc-formats.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-apl:          [PASS][57] -> [FAIL][58] ([i915#4767])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-apl7/igt@kms_fbcon_fbt@fbc-suspend.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-apl6/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_flip@2x-flip-vs-expired-vblank:
    - shard-iclb:         NOTRUN -> [SKIP][59] ([fdo#109274]) +2 similar issues
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-iclb2/igt@kms_flip@2x-flip-vs-expired-vblank.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
    - shard-skl:          NOTRUN -> [SKIP][60] ([fdo#109271]) +53 similar issues
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-skl5/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
    - shard-apl:          [PASS][61] -> [DMESG-WARN][62] ([i915#180])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-apl7/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-default-mode:
    - shard-iclb:         NOTRUN -> [SKIP][63] ([i915#2672]) +2 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-valid-mode:
    - shard-iclb:         NOTRUN -> [SKIP][64] ([i915#2587] / [i915#2672]) +2 similar issues
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-iclb1/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling@pipe-a-valid-mode:
    - shard-glk:          NOTRUN -> [SKIP][65] ([fdo#109271]) +1 similar issue
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-glk2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode:
    - shard-tglb:         NOTRUN -> [SKIP][66] ([i915#2587] / [i915#2672])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-tglb3/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-pgflip-blt:
    - shard-tglb:         NOTRUN -> [SKIP][67] ([i915#6497]) +1 similar issue
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-move:
    - shard-iclb:         NOTRUN -> [SKIP][68] ([fdo#109280]) +4 similar issues
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-iclb2/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-onoff:
    - shard-tglb:         NOTRUN -> [SKIP][69] ([fdo#109280] / [fdo#111825]) +3 similar issues
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-tglb3/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-onoff.html

  * igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-5@pipe-c-edp-1:
    - shard-iclb:         NOTRUN -> [SKIP][70] ([i915#5176]) +2 similar issues
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-iclb2/igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-5@pipe-c-edp-1.html

  * igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-c-edp-1:
    - shard-tglb:         NOTRUN -> [SKIP][71] ([i915#5176]) +3 similar issues
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-tglb3/igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-c-edp-1.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-c-edp-1:
    - shard-tglb:         NOTRUN -> [SKIP][72] ([i915#5235]) +3 similar issues
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-tglb3/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-c-edp-1.html

  * igt@kms_psr2_sf@overlay-plane-update-continuous-sf:
    - shard-tglb:         NOTRUN -> [SKIP][73] ([i915#2920])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-tglb3/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb:
    - shard-apl:          NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#658])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-apl8/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html

  * igt@kms_psr@psr2_cursor_mmap_gtt:
    - shard-iclb:         [PASS][75] -> [SKIP][76] ([fdo#109441]) +1 similar issue
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_gtt.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-iclb7/igt@kms_psr@psr2_cursor_mmap_gtt.html

  * igt@kms_psr@psr2_primary_page_flip:
    - shard-tglb:         NOTRUN -> [FAIL][77] ([i915#132] / [i915#3467]) +1 similar issue
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-tglb3/igt@kms_psr@psr2_primary_page_flip.html

  * igt@kms_rotation_crc@primary-4-tiled-reflect-x-0:
    - shard-tglb:         NOTRUN -> [SKIP][78] ([i915#5289])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-tglb3/igt@kms_rotation_crc@primary-4-tiled-reflect-x-0.html

  * igt@kms_setmode@clone-exclusive-crtc:
    - shard-iclb:         NOTRUN -> [SKIP][79] ([i915#3555])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-iclb2/igt@kms_setmode@clone-exclusive-crtc.html

  * igt@kms_writeback@writeback-pixel-formats:
    - shard-apl:          NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#2437])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-apl8/igt@kms_writeback@writeback-pixel-formats.html

  * igt@perf@polling-parameterized:
    - shard-glk:          [PASS][81] -> [FAIL][82] ([i915#5639])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-glk8/igt@perf@polling-parameterized.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-glk1/igt@perf@polling-parameterized.html

  * igt@sysfs_clients@create:
    - shard-skl:          NOTRUN -> [SKIP][83] ([fdo#109271] / [i915#2994])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-skl5/igt@sysfs_clients@create.html

  
#### Possible fixes ####

  * igt@gem_ctx_isolation@preservation-s3@vcs0:
    - shard-apl:          [DMESG-WARN][84] ([i915#180]) -> [PASS][85]
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-apl8/igt@gem_ctx_isolation@preservation-s3@vcs0.html
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-apl8/igt@gem_ctx_isolation@preservation-s3@vcs0.html

  * igt@gem_ctx_persistence@many-contexts:
    - shard-iclb:         [INCOMPLETE][86] -> [PASS][87]
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-iclb6/igt@gem_ctx_persistence@many-contexts.html
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-iclb2/igt@gem_ctx_persistence@many-contexts.html

  * igt@gem_exec_fair@basic-flow@rcs0:
    - shard-tglb:         [FAIL][88] ([i915#2842]) -> [PASS][89]
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-tglb7/igt@gem_exec_fair@basic-flow@rcs0.html
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-tglb8/igt@gem_exec_fair@basic-flow@rcs0.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
    - shard-apl:          [FAIL][90] ([i915#2842]) -> [PASS][91] +1 similar issue
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-apl1/igt@gem_exec_fair@basic-none-solo@rcs0.html
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-apl1/igt@gem_exec_fair@basic-none-solo@rcs0.html

  * igt@i915_selftest@live@reset:
    - shard-skl:          [INCOMPLETE][92] -> [PASS][93]
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-skl7/igt@i915_selftest@live@reset.html
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-skl1/igt@i915_selftest@live@reset.html

  * igt@kms_async_flips@alternate-sync-async-flip@pipe-c-edp-1:
    - shard-skl:          [FAIL][94] ([i915#2521]) -> [PASS][95]
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-skl10/igt@kms_async_flips@alternate-sync-async-flip@pipe-c-edp-1.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-skl9/igt@kms_async_flips@alternate-sync-async-flip@pipe-c-edp-1.html

  * igt@kms_big_fb@yf-tiled-32bpp-rotate-90:
    - shard-glk:          [DMESG-FAIL][96] ([i915#118] / [i915#5138]) -> [PASS][97]
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-glk5/igt@kms_big_fb@yf-tiled-32bpp-rotate-90.html
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-glk8/igt@kms_big_fb@yf-tiled-32bpp-rotate-90.html

  * igt@kms_cursor_legacy@basic-flip-before-cursor@atomic-transitions-varying-size:
    - shard-skl:          [FAIL][98] ([i915#3927]) -> [PASS][99]
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-skl3/igt@kms_cursor_legacy@basic-flip-before-cursor@atomic-transitions-varying-size.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-skl4/igt@kms_cursor_legacy@basic-flip-before-cursor@atomic-transitions-varying-size.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
    - shard-skl:          [FAIL][100] ([i915#79]) -> [PASS][101]
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html

  * igt@kms_flip@plain-flip-fb-recreate@a-edp1:
    - shard-skl:          [FAIL][102] ([i915#2122]) -> [PASS][103] +2 similar issues
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-skl3/igt@kms_flip@plain-flip-fb-recreate@a-edp1.html
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-skl4/igt@kms_flip@plain-flip-fb-recreate@a-edp1.html

  * igt@kms_flip@wf_vblank-ts-check@c-edp1:
    - shard-tglb:         [INCOMPLETE][104] -> [PASS][105]
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-tglb3/igt@kms_flip@wf_vblank-ts-check@c-edp1.html
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-tglb3/igt@kms_flip@wf_vblank-ts-check@c-edp1.html

  * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b-edp-1:
    - shard-iclb:         [SKIP][106] ([i915#5176]) -> [PASS][107] +1 similar issue
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-iclb3/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b-edp-1.html
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-iclb6/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b-edp-1.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b-edp-1:
    - shard-iclb:         [SKIP][108] ([i915#5235]) -> [PASS][109] +2 similar issues
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-iclb2/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b-edp-1.html
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-iclb7/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b-edp-1.html

  * igt@kms_psr@psr2_sprite_blt:
    - shard-iclb:         [SKIP][110] ([fdo#109441]) -> [PASS][111]
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-iclb6/igt@kms_psr@psr2_sprite_blt.html
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html

  
#### Warnings ####

  * igt@gem_exec_fair@basic-pace@rcs0:
    - shard-tglb:         [SKIP][112] ([i915#2848]) -> [FAIL][113] ([i915#2842])
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-tglb6/igt@gem_exec_fair@basic-pace@rcs0.html
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-tglb2/igt@gem_exec_fair@basic-pace@rcs0.html

  * igt@gem_pwrite@basic-exhaustion:
    - shard-tglb:         [WARN][114] ([i915#2658]) -> [INCOMPLETE][115] ([i915#7248])
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-tglb7/igt@gem_pwrite@basic-exhaustion.html
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-tglb8/igt@gem_pwrite@basic-exhaustion.html
    - shard-glk:          [FAIL][116] -> [INCOMPLETE][117] ([i915#7248])
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-glk5/igt@gem_pwrite@basic-exhaustion.html
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-glk2/igt@gem_pwrite@basic-exhaustion.html

  * igt@runner@aborted:
    - shard-apl:          ([FAIL][118], [FAIL][119], [FAIL][120], [FAIL][121], [FAIL][122], [FAIL][123]) ([i915#180] / [i915#3002] / [i915#4312]) -> ([FAIL][124], [FAIL][125], [FAIL][126], [FAIL][127], [FAIL][128], [FAIL][129], [FAIL][130]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312])
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-apl8/igt@runner@aborted.html
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-apl6/igt@runner@aborted.html
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-apl8/igt@runner@aborted.html
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-apl6/igt@runner@aborted.html
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-apl6/igt@runner@aborted.html
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12296/shard-apl6/igt@runner@aborted.html
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-apl2/igt@runner@aborted.html
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-apl2/igt@runner@aborted.html
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-apl2/igt@runner@aborted.html
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-apl3/igt@runner@aborted.html
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-apl1/igt@runner@aborted.html
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-apl8/igt@runner@aborted.html
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/shard-apl6/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
  [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
  [fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
  [fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
  [fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
  [fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
  [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
  [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
  [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
  [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
  [i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
  [i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
  [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
  [i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
  [i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
  [i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804
  [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
  [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410
  [i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
  [i915#2435]: https://gitlab.freedesktop.org/drm/intel/issues/2435
  [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
  [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
  [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
  [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
  [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
  [i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684
  [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
  [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
  [i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2848]: https://gitlab.freedesktop.org/drm/intel/issues/2848
  [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
  [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
  [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
  [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
  [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
  [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
  [i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
  [i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
  [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
  [i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
  [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
  [i915#3467]: https://gitlab.freedesktop.org/drm/intel/issues/3467
  [i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
  [i915#3528]: https://gitlab.freedesktop.org/drm/intel/issues/3528
  [i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536
  [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
  [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
  [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
  [i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
  [i915#3810]: https://gitlab.freedesktop.org/drm/intel/issues/3810
  [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
  [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
  [i915#3927]: https://gitlab.freedesktop.org/drm/intel/issues/3927
  [i915#3936]: https://gitlab.freedesktop.org/drm/intel/issues/3936
  [i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952
  [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
  [i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
  [i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036
  [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
  [i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
  [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
  [i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433
  [i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
  [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
  [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
  [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
  [i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4765]: https://gitlab.freedesktop.org/drm/intel/issues/4765
  [i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
  [i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
  [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
  [i915#4818]: https://gitlab.freedesktop.org/drm/intel/issues/4818
  [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
  [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
  [i915#4854]: https://gitlab.freedesktop.org/drm/intel/issues/4854
  [i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
  [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
  [i915#4874]: https://gitlab.freedesktop.org/drm/intel/issues/4874
  [i915#4877]: https://gitlab.freedesktop.org/drm/intel/issues/4877
  [i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
  [i915#4884]: https://gitlab.freedesktop.org/drm/intel/issues/4884
  [i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885
  [i915#4958]: https://gitlab.freedesktop.org/drm/intel/issues/4958
  [i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
  [i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
  [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
  [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
  [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
  [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
  [i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
  [i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
  [i915#5639]: https://gitlab.freedesktop.org/drm/intel/issues/5639
  [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
  [i915#6032]: https://gitlab.freedesktop.org/drm/intel/issues/6032
  [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
  [i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
  [i915#6251]: https://gitlab.freedesktop.org/drm/intel/issues/6251
  [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
  [i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
  [i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
  [i915#6412]: https://gitlab.freedesktop.org/drm/intel/issues/6412
  [i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
  [i915#6463]: https://gitlab.freedesktop.org/drm/intel/issues/6463
  [i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
  [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
  [i915#6537]: https://gitlab.freedesktop.org/drm/intel/issues/6537
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#6778]: https://gitlab.freedesktop.org/drm/intel/issues/6778
  [i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
  [i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
  [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
  [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
  [i915#7142]: https://gitlab.freedesktop.org/drm/intel/issues/7142
  [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
  [i915#7178]: https://gitlab.freedesktop.org/drm/intel/issues/7178
  [i915#7205]: https://gitlab.freedesktop.org/drm/intel/issues/7205
  [i915#7247]: https://gitlab.freedesktop.org/drm/intel/issues/7247
  [i915#7248]: https://gitlab.freedesktop.org/drm/intel/issues/7248
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79


Build changes
-------------

  * Linux: CI_DRM_12296 -> Patchwork_110168v1

  CI-20190529: 20190529
  CI_DRM_12296: dc5600688adfc13fed8128d9043bab2257066646 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7026: ce0f97e7e0aa54c40049a8365b3d61773c92e588 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_110168v1: dc5600688adfc13fed8128d9043bab2257066646 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110168v1/index.html

[-- Attachment #2: Type: text/html, Size: 39842 bytes --]

Re: [Intel-gfx] [PATCH 01/11] drm/i915: Use sizeof(variable) instead sizeof(type)

[Nautiyal, Ankit K]

Looks good to me.

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

On 10/26/2022 5:08 PM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Use sizeof(variable) instead of sizeof(type) in the hopes of
> less chance of screwing things up.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_color.c | 16 ++++++++--------
>   1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index 4bb113c39f4b..92cc43d5bad6 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -565,7 +565,7 @@ create_linear_lut(struct drm_i915_private *i915, int lut_size)
>   	int i;
>   
>   	blob = drm_property_create_blob(&i915->drm,
> -					sizeof(struct drm_color_lut) * lut_size,
> +					sizeof(lut[0]) * lut_size,
>   					NULL);
>   	if (IS_ERR(blob))
>   		return blob;
> @@ -1895,7 +1895,7 @@ static struct drm_property_blob *i9xx_read_lut_8(struct intel_crtc *crtc)
>   	int i;
>   
>   	blob = drm_property_create_blob(&dev_priv->drm,
> -					sizeof(struct drm_color_lut) * LEGACY_LUT_LENGTH,
> +					sizeof(lut[0]) * LEGACY_LUT_LENGTH,
>   					NULL);
>   	if (IS_ERR(blob))
>   		return NULL;
> @@ -1930,7 +1930,7 @@ static struct drm_property_blob *i965_read_lut_10p6(struct intel_crtc *crtc)
>   	struct drm_color_lut *lut;
>   
>   	blob = drm_property_create_blob(&dev_priv->drm,
> -					sizeof(struct drm_color_lut) * lut_size,
> +					sizeof(lut[0]) * lut_size,
>   					NULL);
>   	if (IS_ERR(blob))
>   		return NULL;
> @@ -1973,7 +1973,7 @@ static struct drm_property_blob *chv_read_cgm_gamma(struct intel_crtc *crtc)
>   	struct drm_color_lut *lut;
>   
>   	blob = drm_property_create_blob(&dev_priv->drm,
> -					sizeof(struct drm_color_lut) * lut_size,
> +					sizeof(lut[0]) * lut_size,
>   					NULL);
>   	if (IS_ERR(blob))
>   		return NULL;
> @@ -2009,7 +2009,7 @@ static struct drm_property_blob *ilk_read_lut_8(struct intel_crtc *crtc)
>   	int i;
>   
>   	blob = drm_property_create_blob(&dev_priv->drm,
> -					sizeof(struct drm_color_lut) * LEGACY_LUT_LENGTH,
> +					sizeof(lut[0]) * LEGACY_LUT_LENGTH,
>   					NULL);
>   	if (IS_ERR(blob))
>   		return NULL;
> @@ -2034,7 +2034,7 @@ static struct drm_property_blob *ilk_read_lut_10(struct intel_crtc *crtc)
>   	struct drm_color_lut *lut;
>   
>   	blob = drm_property_create_blob(&dev_priv->drm,
> -					sizeof(struct drm_color_lut) * lut_size,
> +					sizeof(lut[0]) * lut_size,
>   					NULL);
>   	if (IS_ERR(blob))
>   		return NULL;
> @@ -2087,7 +2087,7 @@ static struct drm_property_blob *bdw_read_lut_10(struct intel_crtc *crtc,
>   	drm_WARN_ON(&dev_priv->drm, lut_size != hw_lut_size);
>   
>   	blob = drm_property_create_blob(&dev_priv->drm,
> -					sizeof(struct drm_color_lut) * lut_size,
> +					sizeof(lut[0]) * lut_size,
>   					NULL);
>   	if (IS_ERR(blob))
>   		return NULL;
> @@ -2138,7 +2138,7 @@ icl_read_lut_multi_segment(struct intel_crtc *crtc)
>   	struct drm_color_lut *lut;
>   
>   	blob = drm_property_create_blob(&dev_priv->drm,
> -					sizeof(struct drm_color_lut) * lut_size,
> +					sizeof(lut[0]) * lut_size,
>   					NULL);
>   	if (IS_ERR(blob))
>   		return NULL;

Re: [Intel-gfx] [PATCH 02/11] drm/i915: Use _MMIO_PIPE() for SKL_BOTTOM_COLOR

[Nautiyal, Ankit K]

Makes sense.

LGTM.

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

On 10/26/2022 5:08 PM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> No need to use _MMIO_PIPE2() for SKL_BOTTOM_COLOR
> since all pipe registers are evenly spread on skl+.
> Switch to _MMIO_PIPE() and thus avoid the hidden dev_priv.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 99a853519395..89ad893bbf07 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3758,9 +3758,10 @@
>   
>   /* Skylake+ pipe bottom (background) color */
>   #define _SKL_BOTTOM_COLOR_A		0x70034
> +#define _SKL_BOTTOM_COLOR_B		0x71034
>   #define   SKL_BOTTOM_COLOR_GAMMA_ENABLE		REG_BIT(31)
>   #define   SKL_BOTTOM_COLOR_CSC_ENABLE		REG_BIT(30)
> -#define SKL_BOTTOM_COLOR(pipe)		_MMIO_PIPE2(pipe, _SKL_BOTTOM_COLOR_A)
> +#define SKL_BOTTOM_COLOR(pipe)		_MMIO_PIPE(pipe, _SKL_BOTTOM_COLOR_A, _SKL_BOTTOM_COLOR_B)
>   
>   #define _ICL_PIPE_A_STATUS			0x70058
>   #define ICL_PIPESTATUS(pipe)			_MMIO_PIPE2(pipe, _ICL_PIPE_A_STATUS)

Re: [Intel-gfx] [PATCH 03/11] drm/i915: s/dev_priv/i915/ in intel_color.c

[Nautiyal, Ankit K]

Looks Good to me.

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

On 10/26/2022 5:08 PM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Switch intel_color.c over to the modern 'i915' variable
> naming scehme. The only exceptions are the i9xx LUT access
> functions which still need the magic 'dev_priv' for the
> register macros.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_color.c | 278 ++++++++++-----------
>   1 file changed, 139 insertions(+), 139 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index 92cc43d5bad6..415e0a6839a4 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -184,31 +184,31 @@ static void ilk_update_pipe_csc(struct intel_crtc *crtc,
>   				const u16 coeff[9],
>   				const u16 postoff[3])
>   {
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>   	enum pipe pipe = crtc->pipe;
>   
> -	intel_de_write_fw(dev_priv, PIPE_CSC_PREOFF_HI(pipe), preoff[0]);
> -	intel_de_write_fw(dev_priv, PIPE_CSC_PREOFF_ME(pipe), preoff[1]);
> -	intel_de_write_fw(dev_priv, PIPE_CSC_PREOFF_LO(pipe), preoff[2]);
> +	intel_de_write_fw(i915, PIPE_CSC_PREOFF_HI(pipe), preoff[0]);
> +	intel_de_write_fw(i915, PIPE_CSC_PREOFF_ME(pipe), preoff[1]);
> +	intel_de_write_fw(i915, PIPE_CSC_PREOFF_LO(pipe), preoff[2]);
>   
> -	intel_de_write_fw(dev_priv, PIPE_CSC_COEFF_RY_GY(pipe),
> +	intel_de_write_fw(i915, PIPE_CSC_COEFF_RY_GY(pipe),
>   			  coeff[0] << 16 | coeff[1]);
> -	intel_de_write_fw(dev_priv, PIPE_CSC_COEFF_BY(pipe), coeff[2] << 16);
> +	intel_de_write_fw(i915, PIPE_CSC_COEFF_BY(pipe), coeff[2] << 16);
>   
> -	intel_de_write_fw(dev_priv, PIPE_CSC_COEFF_RU_GU(pipe),
> +	intel_de_write_fw(i915, PIPE_CSC_COEFF_RU_GU(pipe),
>   			  coeff[3] << 16 | coeff[4]);
> -	intel_de_write_fw(dev_priv, PIPE_CSC_COEFF_BU(pipe), coeff[5] << 16);
> +	intel_de_write_fw(i915, PIPE_CSC_COEFF_BU(pipe), coeff[5] << 16);
>   
> -	intel_de_write_fw(dev_priv, PIPE_CSC_COEFF_RV_GV(pipe),
> +	intel_de_write_fw(i915, PIPE_CSC_COEFF_RV_GV(pipe),
>   			  coeff[6] << 16 | coeff[7]);
> -	intel_de_write_fw(dev_priv, PIPE_CSC_COEFF_BV(pipe), coeff[8] << 16);
> +	intel_de_write_fw(i915, PIPE_CSC_COEFF_BV(pipe), coeff[8] << 16);
>   
> -	if (DISPLAY_VER(dev_priv) >= 7) {
> -		intel_de_write_fw(dev_priv, PIPE_CSC_POSTOFF_HI(pipe),
> +	if (DISPLAY_VER(i915) >= 7) {
> +		intel_de_write_fw(i915, PIPE_CSC_POSTOFF_HI(pipe),
>   				  postoff[0]);
> -		intel_de_write_fw(dev_priv, PIPE_CSC_POSTOFF_ME(pipe),
> +		intel_de_write_fw(i915, PIPE_CSC_POSTOFF_ME(pipe),
>   				  postoff[1]);
> -		intel_de_write_fw(dev_priv, PIPE_CSC_POSTOFF_LO(pipe),
> +		intel_de_write_fw(i915, PIPE_CSC_POSTOFF_LO(pipe),
>   				  postoff[2]);
>   	}
>   }
> @@ -218,44 +218,44 @@ static void icl_update_output_csc(struct intel_crtc *crtc,
>   				  const u16 coeff[9],
>   				  const u16 postoff[3])
>   {
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>   	enum pipe pipe = crtc->pipe;
>   
> -	intel_de_write_fw(dev_priv, PIPE_CSC_OUTPUT_PREOFF_HI(pipe), preoff[0]);
> -	intel_de_write_fw(dev_priv, PIPE_CSC_OUTPUT_PREOFF_ME(pipe), preoff[1]);
> -	intel_de_write_fw(dev_priv, PIPE_CSC_OUTPUT_PREOFF_LO(pipe), preoff[2]);
> +	intel_de_write_fw(i915, PIPE_CSC_OUTPUT_PREOFF_HI(pipe), preoff[0]);
> +	intel_de_write_fw(i915, PIPE_CSC_OUTPUT_PREOFF_ME(pipe), preoff[1]);
> +	intel_de_write_fw(i915, PIPE_CSC_OUTPUT_PREOFF_LO(pipe), preoff[2]);
>   
> -	intel_de_write_fw(dev_priv, PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe),
> +	intel_de_write_fw(i915, PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe),
>   			  coeff[0] << 16 | coeff[1]);
> -	intel_de_write_fw(dev_priv, PIPE_CSC_OUTPUT_COEFF_BY(pipe),
> +	intel_de_write_fw(i915, PIPE_CSC_OUTPUT_COEFF_BY(pipe),
>   			  coeff[2] << 16);
>   
> -	intel_de_write_fw(dev_priv, PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe),
> +	intel_de_write_fw(i915, PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe),
>   			  coeff[3] << 16 | coeff[4]);
> -	intel_de_write_fw(dev_priv, PIPE_CSC_OUTPUT_COEFF_BU(pipe),
> +	intel_de_write_fw(i915, PIPE_CSC_OUTPUT_COEFF_BU(pipe),
>   			  coeff[5] << 16);
>   
> -	intel_de_write_fw(dev_priv, PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe),
> +	intel_de_write_fw(i915, PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe),
>   			  coeff[6] << 16 | coeff[7]);
> -	intel_de_write_fw(dev_priv, PIPE_CSC_OUTPUT_COEFF_BV(pipe),
> +	intel_de_write_fw(i915, PIPE_CSC_OUTPUT_COEFF_BV(pipe),
>   			  coeff[8] << 16);
>   
> -	intel_de_write_fw(dev_priv, PIPE_CSC_OUTPUT_POSTOFF_HI(pipe), postoff[0]);
> -	intel_de_write_fw(dev_priv, PIPE_CSC_OUTPUT_POSTOFF_ME(pipe), postoff[1]);
> -	intel_de_write_fw(dev_priv, PIPE_CSC_OUTPUT_POSTOFF_LO(pipe), postoff[2]);
> +	intel_de_write_fw(i915, PIPE_CSC_OUTPUT_POSTOFF_HI(pipe), postoff[0]);
> +	intel_de_write_fw(i915, PIPE_CSC_OUTPUT_POSTOFF_ME(pipe), postoff[1]);
> +	intel_de_write_fw(i915, PIPE_CSC_OUTPUT_POSTOFF_LO(pipe), postoff[2]);
>   }
>   
>   static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state)
>   {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> +	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
>   
>   	/*
>   	 * FIXME if there's a gamma LUT after the CSC, we should
>   	 * do the range compression using the gamma LUT instead.
>   	 */
>   	return crtc_state->limited_color_range &&
> -		(IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
> -		 IS_DISPLAY_VER(dev_priv, 9, 10));
> +		(IS_HASWELL(i915) || IS_BROADWELL(i915) ||
> +		 IS_DISPLAY_VER(i915, 9, 10));
>   }
>   
>   static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
> @@ -313,7 +313,7 @@ static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
>   static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
>   {
>   	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>   	bool limited_color_range = ilk_csc_limited_range(crtc_state);
>   
>   	if (crtc_state->hw.ctm) {
> @@ -339,7 +339,7 @@ static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
>   		 * LUT is needed but CSC is not we need to load an
>   		 * identity matrix.
>   		 */
> -		drm_WARN_ON(&dev_priv->drm, !IS_GEMINILAKE(dev_priv));
> +		drm_WARN_ON(&i915->drm, !IS_GEMINILAKE(i915));
>   
>   		ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
>   				    ilk_csc_coeff_identity,
> @@ -373,7 +373,7 @@ static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state)
>   static void chv_load_cgm_csc(struct intel_crtc *crtc,
>   			     const struct drm_property_blob *blob)
>   {
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>   	const struct drm_color_ctm *ctm = blob->data;
>   	enum pipe pipe = crtc->pipe;
>   	u16 coeffs[9];
> @@ -397,15 +397,15 @@ static void chv_load_cgm_csc(struct intel_crtc *crtc,
>   		coeffs[i] |= (abs_coeff >> 20) & 0xfff;
>   	}
>   
> -	intel_de_write_fw(dev_priv, CGM_PIPE_CSC_COEFF01(pipe),
> +	intel_de_write_fw(i915, CGM_PIPE_CSC_COEFF01(pipe),
>   			  coeffs[1] << 16 | coeffs[0]);
> -	intel_de_write_fw(dev_priv, CGM_PIPE_CSC_COEFF23(pipe),
> +	intel_de_write_fw(i915, CGM_PIPE_CSC_COEFF23(pipe),
>   			  coeffs[3] << 16 | coeffs[2]);
> -	intel_de_write_fw(dev_priv, CGM_PIPE_CSC_COEFF45(pipe),
> +	intel_de_write_fw(i915, CGM_PIPE_CSC_COEFF45(pipe),
>   			  coeffs[5] << 16 | coeffs[4]);
> -	intel_de_write_fw(dev_priv, CGM_PIPE_CSC_COEFF67(pipe),
> +	intel_de_write_fw(i915, CGM_PIPE_CSC_COEFF67(pipe),
>   			  coeffs[7] << 16 | coeffs[6]);
> -	intel_de_write_fw(dev_priv, CGM_PIPE_CSC_COEFF8(pipe),
> +	intel_de_write_fw(i915, CGM_PIPE_CSC_COEFF8(pipe),
>   			  coeffs[8]);
>   }
>   
> @@ -511,31 +511,31 @@ static void i9xx_color_commit_arm(const struct intel_crtc_state *crtc_state)
>   static void ilk_color_commit_arm(const struct intel_crtc_state *crtc_state)
>   {
>   	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>   
>   	/* update PIPECONF GAMMA_MODE */
>   	ilk_set_pipeconf(crtc_state);
>   
> -	intel_de_write_fw(dev_priv, PIPE_CSC_MODE(crtc->pipe),
> +	intel_de_write_fw(i915, PIPE_CSC_MODE(crtc->pipe),
>   			  crtc_state->csc_mode);
>   }
>   
>   static void hsw_color_commit_arm(const struct intel_crtc_state *crtc_state)
>   {
>   	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>   
> -	intel_de_write(dev_priv, GAMMA_MODE(crtc->pipe),
> +	intel_de_write(i915, GAMMA_MODE(crtc->pipe),
>   		       crtc_state->gamma_mode);
>   
> -	intel_de_write_fw(dev_priv, PIPE_CSC_MODE(crtc->pipe),
> +	intel_de_write_fw(i915, PIPE_CSC_MODE(crtc->pipe),
>   			  crtc_state->csc_mode);
>   }
>   
>   static void skl_color_commit_arm(const struct intel_crtc_state *crtc_state)
>   {
>   	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>   	enum pipe pipe = crtc->pipe;
>   	u32 val = 0;
>   
> @@ -548,12 +548,12 @@ static void skl_color_commit_arm(const struct intel_crtc_state *crtc_state)
>   		val |= SKL_BOTTOM_COLOR_GAMMA_ENABLE;
>   	if (crtc_state->csc_enable)
>   		val |= SKL_BOTTOM_COLOR_CSC_ENABLE;
> -	intel_de_write(dev_priv, SKL_BOTTOM_COLOR(pipe), val);
> +	intel_de_write(i915, SKL_BOTTOM_COLOR(pipe), val);
>   
> -	intel_de_write(dev_priv, GAMMA_MODE(crtc->pipe),
> +	intel_de_write(i915, GAMMA_MODE(crtc->pipe),
>   		       crtc_state->gamma_mode);
>   
> -	intel_de_write_fw(dev_priv, PIPE_CSC_MODE(crtc->pipe),
> +	intel_de_write_fw(i915, PIPE_CSC_MODE(crtc->pipe),
>   			  crtc_state->csc_mode);
>   }
>   
> @@ -643,7 +643,7 @@ static void i965_load_luts(const struct intel_crtc_state *crtc_state)
>   static void ilk_load_lut_8(struct intel_crtc *crtc,
>   			   const struct drm_property_blob *blob)
>   {
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>   	const struct drm_color_lut *lut;
>   	enum pipe pipe = crtc->pipe;
>   	int i;
> @@ -654,20 +654,20 @@ static void ilk_load_lut_8(struct intel_crtc *crtc,
>   	lut = blob->data;
>   
>   	for (i = 0; i < 256; i++)
> -		intel_de_write_fw(dev_priv, LGC_PALETTE(pipe, i),
> +		intel_de_write_fw(i915, LGC_PALETTE(pipe, i),
>   				  i9xx_lut_8(&lut[i]));
>   }
>   
>   static void ilk_load_lut_10(struct intel_crtc *crtc,
>   			    const struct drm_property_blob *blob)
>   {
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>   	const struct drm_color_lut *lut = blob->data;
>   	int i, lut_size = drm_color_lut_size(blob);
>   	enum pipe pipe = crtc->pipe;
>   
>   	for (i = 0; i < lut_size; i++)
> -		intel_de_write_fw(dev_priv, PREC_PALETTE(pipe, i),
> +		intel_de_write_fw(i915, PREC_PALETTE(pipe, i),
>   				  ilk_lut_10(&lut[i]));
>   }
>   
> @@ -708,7 +708,7 @@ static void ivb_load_lut_10(struct intel_crtc *crtc,
>   			    const struct drm_property_blob *blob,
>   			    u32 prec_index)
>   {
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>   	int hw_lut_size = ivb_lut_10_size(prec_index);
>   	const struct drm_color_lut *lut = blob->data;
>   	int i, lut_size = drm_color_lut_size(blob);
> @@ -719,8 +719,8 @@ static void ivb_load_lut_10(struct intel_crtc *crtc,
>   		const struct drm_color_lut *entry =
>   			&lut[i * (lut_size - 1) / (hw_lut_size - 1)];
>   
> -		intel_de_write_fw(dev_priv, PREC_PAL_INDEX(pipe), prec_index++);
> -		intel_de_write_fw(dev_priv, PREC_PAL_DATA(pipe),
> +		intel_de_write_fw(i915, PREC_PAL_INDEX(pipe), prec_index++);
> +		intel_de_write_fw(i915, PREC_PAL_DATA(pipe),
>   				  ilk_lut_10(entry));
>   	}
>   
> @@ -728,7 +728,7 @@ static void ivb_load_lut_10(struct intel_crtc *crtc,
>   	 * Reset the index, otherwise it prevents the legacy palette to be
>   	 * written properly.
>   	 */
> -	intel_de_write_fw(dev_priv, PREC_PAL_INDEX(pipe), 0);
> +	intel_de_write_fw(i915, PREC_PAL_INDEX(pipe), 0);
>   }
>   
>   /* On BDW+ the index auto increment mode actually works */
> @@ -736,13 +736,13 @@ static void bdw_load_lut_10(struct intel_crtc *crtc,
>   			    const struct drm_property_blob *blob,
>   			    u32 prec_index)
>   {
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>   	int hw_lut_size = ivb_lut_10_size(prec_index);
>   	const struct drm_color_lut *lut = blob->data;
>   	int i, lut_size = drm_color_lut_size(blob);
>   	enum pipe pipe = crtc->pipe;
>   
> -	intel_de_write_fw(dev_priv, PREC_PAL_INDEX(pipe),
> +	intel_de_write_fw(i915, PREC_PAL_INDEX(pipe),
>   			  prec_index | PAL_PREC_AUTO_INCREMENT);
>   
>   	for (i = 0; i < hw_lut_size; i++) {
> @@ -750,7 +750,7 @@ static void bdw_load_lut_10(struct intel_crtc *crtc,
>   		const struct drm_color_lut *entry =
>   			&lut[i * (lut_size - 1) / (hw_lut_size - 1)];
>   
> -		intel_de_write_fw(dev_priv, PREC_PAL_DATA(pipe),
> +		intel_de_write_fw(i915, PREC_PAL_DATA(pipe),
>   				  ilk_lut_10(entry));
>   	}
>   
> @@ -758,13 +758,13 @@ static void bdw_load_lut_10(struct intel_crtc *crtc,
>   	 * Reset the index, otherwise it prevents the legacy palette to be
>   	 * written properly.
>   	 */
> -	intel_de_write_fw(dev_priv, PREC_PAL_INDEX(pipe), 0);
> +	intel_de_write_fw(i915, PREC_PAL_INDEX(pipe), 0);
>   }
>   
>   static void ivb_load_lut_ext_max(const struct intel_crtc_state *crtc_state)
>   {
>   	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>   	enum pipe pipe = crtc->pipe;
>   
>   	/* Program the max register to clamp values > 1.0. */
> @@ -777,7 +777,7 @@ static void ivb_load_lut_ext_max(const struct intel_crtc_state *crtc_state)
>   	 * ToDo: Extend the ABI to be able to program values
>   	 * from 3.0 to 7.0
>   	 */
> -	if (DISPLAY_VER(dev_priv) >= 10) {
> +	if (DISPLAY_VER(i915) >= 10) {
>   		intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 0),
>   				    1 << 16);
>   		intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 1),
> @@ -858,7 +858,7 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state,
>   				 const struct drm_property_blob *blob)
>   {
>   	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>   	const struct drm_color_lut *lut = blob->data;
>   	int i, lut_size = drm_color_lut_size(blob);
>   	enum pipe pipe = crtc->pipe;
> @@ -868,8 +868,8 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state,
>   	 * ignore the index bits, so we need to reset it to index 0
>   	 * separately.
>   	 */
> -	intel_de_write_fw(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 0);
> -	intel_de_write_fw(dev_priv, PRE_CSC_GAMC_INDEX(pipe),
> +	intel_de_write_fw(i915, PRE_CSC_GAMC_INDEX(pipe), 0);
> +	intel_de_write_fw(i915, PRE_CSC_GAMC_INDEX(pipe),
>   			  PRE_CSC_GAMC_AUTO_INCREMENT);
>   
>   	for (i = 0; i < lut_size; i++) {
> @@ -886,15 +886,15 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state,
>   		 * ToDo: Extend to max 7.0. Enable 32 bit input value
>   		 * as compared to just 16 to achieve this.
>   		 */
> -		intel_de_write_fw(dev_priv, PRE_CSC_GAMC_DATA(pipe),
> +		intel_de_write_fw(i915, PRE_CSC_GAMC_DATA(pipe),
>   				  lut[i].green);
>   	}
>   
>   	/* Clamp values > 1.0. */
> -	while (i++ < glk_degamma_lut_size(dev_priv))
> -		intel_de_write_fw(dev_priv, PRE_CSC_GAMC_DATA(pipe), 1 << 16);
> +	while (i++ < glk_degamma_lut_size(i915))
> +		intel_de_write_fw(i915, PRE_CSC_GAMC_DATA(pipe), 1 << 16);
>   
> -	intel_de_write_fw(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 0);
> +	intel_de_write_fw(i915, PRE_CSC_GAMC_INDEX(pipe), 0);
>   }
>   
>   static void glk_load_luts(const struct intel_crtc_state *crtc_state)
> @@ -1075,15 +1075,15 @@ static u32 chv_cgm_degamma_udw(const struct drm_color_lut *color)
>   static void chv_load_cgm_degamma(struct intel_crtc *crtc,
>   				 const struct drm_property_blob *blob)
>   {
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>   	const struct drm_color_lut *lut = blob->data;
>   	int i, lut_size = drm_color_lut_size(blob);
>   	enum pipe pipe = crtc->pipe;
>   
>   	for (i = 0; i < lut_size; i++) {
> -		intel_de_write_fw(dev_priv, CGM_PIPE_DEGAMMA(pipe, i, 0),
> +		intel_de_write_fw(i915, CGM_PIPE_DEGAMMA(pipe, i, 0),
>   				  chv_cgm_degamma_ldw(&lut[i]));
> -		intel_de_write_fw(dev_priv, CGM_PIPE_DEGAMMA(pipe, i, 1),
> +		intel_de_write_fw(i915, CGM_PIPE_DEGAMMA(pipe, i, 1),
>   				  chv_cgm_degamma_udw(&lut[i]));
>   	}
>   }
> @@ -1109,15 +1109,15 @@ static void chv_cgm_gamma_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)
>   static void chv_load_cgm_gamma(struct intel_crtc *crtc,
>   			       const struct drm_property_blob *blob)
>   {
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>   	const struct drm_color_lut *lut = blob->data;
>   	int i, lut_size = drm_color_lut_size(blob);
>   	enum pipe pipe = crtc->pipe;
>   
>   	for (i = 0; i < lut_size; i++) {
> -		intel_de_write_fw(dev_priv, CGM_PIPE_GAMMA(pipe, i, 0),
> +		intel_de_write_fw(i915, CGM_PIPE_GAMMA(pipe, i, 0),
>   				  chv_cgm_gamma_ldw(&lut[i]));
> -		intel_de_write_fw(dev_priv, CGM_PIPE_GAMMA(pipe, i, 1),
> +		intel_de_write_fw(i915, CGM_PIPE_GAMMA(pipe, i, 1),
>   				  chv_cgm_gamma_udw(&lut[i]));
>   	}
>   }
> @@ -1125,7 +1125,7 @@ static void chv_load_cgm_gamma(struct intel_crtc *crtc,
>   static void chv_load_luts(const struct intel_crtc_state *crtc_state)
>   {
>   	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>   	const struct drm_property_blob *pre_csc_lut = crtc_state->pre_csc_lut;
>   	const struct drm_property_blob *post_csc_lut = crtc_state->post_csc_lut;
>   	const struct drm_property_blob *ctm = crtc_state->hw.ctm;
> @@ -1141,30 +1141,30 @@ static void chv_load_luts(const struct intel_crtc_state *crtc_state)
>   	else
>   		i965_load_luts(crtc_state);
>   
> -	intel_de_write_fw(dev_priv, CGM_PIPE_MODE(crtc->pipe),
> +	intel_de_write_fw(i915, CGM_PIPE_MODE(crtc->pipe),
>   			  crtc_state->cgm_mode);
>   }
>   
>   void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
>   {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> +	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
>   
> -	dev_priv->display.funcs.color->load_luts(crtc_state);
> +	i915->display.funcs.color->load_luts(crtc_state);
>   }
>   
>   void intel_color_commit_noarm(const struct intel_crtc_state *crtc_state)
>   {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> +	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
>   
> -	if (dev_priv->display.funcs.color->color_commit_noarm)
> -		dev_priv->display.funcs.color->color_commit_noarm(crtc_state);
> +	if (i915->display.funcs.color->color_commit_noarm)
> +		i915->display.funcs.color->color_commit_noarm(crtc_state);
>   }
>   
>   void intel_color_commit_arm(const struct intel_crtc_state *crtc_state)
>   {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> +	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
>   
> -	dev_priv->display.funcs.color->color_commit_arm(crtc_state);
> +	i915->display.funcs.color->color_commit_arm(crtc_state);
>   }
>   
>   static bool intel_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
> @@ -1200,23 +1200,23 @@ static bool chv_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
>   
>   int intel_color_check(struct intel_crtc_state *crtc_state)
>   {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> +	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
>   
> -	return dev_priv->display.funcs.color->color_check(crtc_state);
> +	return i915->display.funcs.color->color_check(crtc_state);
>   }
>   
>   void intel_color_get_config(struct intel_crtc_state *crtc_state)
>   {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> +	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
>   
> -	if (dev_priv->display.funcs.color->read_luts)
> -		dev_priv->display.funcs.color->read_luts(crtc_state);
> +	if (i915->display.funcs.color->read_luts)
> +		i915->display.funcs.color->read_luts(crtc_state);
>   }
>   
>   static bool need_plane_update(struct intel_plane *plane,
>   			      const struct intel_crtc_state *crtc_state)
>   {
> -	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> +	struct drm_i915_private *i915 = to_i915(plane->base.dev);
>   
>   	/*
>   	 * On pre-SKL the pipe gamma enable and pipe csc enable for
> @@ -1224,7 +1224,7 @@ static bool need_plane_update(struct intel_plane *plane,
>   	 * We have to reconfigure that even if the plane is inactive.
>   	 */
>   	return crtc_state->active_planes & BIT(plane->id) ||
> -		(DISPLAY_VER(dev_priv) < 9 &&
> +		(DISPLAY_VER(i915) < 9 &&
>   		 plane->id == PLANE_PRIMARY);
>   }
>   
> @@ -1232,7 +1232,7 @@ static int
>   intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state)
>   {
>   	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>   	struct intel_atomic_state *state =
>   		to_intel_atomic_state(new_crtc_state->uapi.state);
>   	const struct intel_crtc_state *old_crtc_state =
> @@ -1247,7 +1247,7 @@ intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state)
>   	    new_crtc_state->csc_enable == old_crtc_state->csc_enable)
>   		return 0;
>   
> -	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
> +	for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
>   		struct intel_plane_state *plane_state;
>   
>   		if (!need_plane_update(plane, new_crtc_state))
> @@ -1260,7 +1260,7 @@ intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state)
>   		new_crtc_state->update_planes |= BIT(plane->id);
>   
>   		/* plane control register changes blocked by CxSR */
> -		if (HAS_GMCH(dev_priv))
> +		if (HAS_GMCH(i915))
>   			new_crtc_state->disable_cxsr = true;
>   	}
>   
> @@ -1286,7 +1286,7 @@ static int check_lut_size(const struct drm_property_blob *lut, int expected)
>   
>   static int check_luts(const struct intel_crtc_state *crtc_state)
>   {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> +	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
>   	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
>   	const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
>   	int gamma_length, degamma_length;
> @@ -1298,15 +1298,15 @@ static int check_luts(const struct intel_crtc_state *crtc_state)
>   
>   	/* C8 relies on its palette being stored in the legacy LUT */
>   	if (crtc_state->c8_planes) {
> -		drm_dbg_kms(&dev_priv->drm,
> +		drm_dbg_kms(&i915->drm,
>   			    "C8 pixelformat requires the legacy LUT\n");
>   		return -EINVAL;
>   	}
>   
> -	degamma_length = INTEL_INFO(dev_priv)->display.color.degamma_lut_size;
> -	gamma_length = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;
> -	degamma_tests = INTEL_INFO(dev_priv)->display.color.degamma_lut_tests;
> -	gamma_tests = INTEL_INFO(dev_priv)->display.color.gamma_lut_tests;
> +	degamma_length = INTEL_INFO(i915)->display.color.degamma_lut_size;
> +	gamma_length = INTEL_INFO(i915)->display.color.gamma_lut_size;
> +	degamma_tests = INTEL_INFO(i915)->display.color.degamma_lut_tests;
> +	gamma_tests = INTEL_INFO(i915)->display.color.gamma_lut_tests;
>   
>   	if (check_lut_size(degamma_lut, degamma_length) ||
>   	    check_lut_size(gamma_lut, gamma_length))
> @@ -1550,7 +1550,7 @@ static u32 ivb_csc_mode(const struct intel_crtc_state *crtc_state)
>   
>   static int ivb_color_check(struct intel_crtc_state *crtc_state)
>   {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> +	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
>   	bool limited_color_range = ilk_csc_limited_range(crtc_state);
>   	int ret;
>   
> @@ -1560,7 +1560,7 @@ static int ivb_color_check(struct intel_crtc_state *crtc_state)
>   
>   	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB &&
>   	    crtc_state->hw.ctm) {
> -		drm_dbg_kms(&dev_priv->drm,
> +		drm_dbg_kms(&i915->drm,
>   			    "YCBCR and CTM together are not possible\n");
>   		return -EINVAL;
>   	}
> @@ -1617,7 +1617,7 @@ static void glk_assign_luts(struct intel_crtc_state *crtc_state)
>   
>   static int glk_color_check(struct intel_crtc_state *crtc_state)
>   {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> +	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
>   	int ret;
>   
>   	ret = check_luts(crtc_state);
> @@ -1626,7 +1626,7 @@ static int glk_color_check(struct intel_crtc_state *crtc_state)
>   
>   	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB &&
>   	    crtc_state->hw.ctm) {
> -		drm_dbg_kms(&dev_priv->drm,
> +		drm_dbg_kms(&i915->drm,
>   			    "YCBCR and CTM together are not possible\n");
>   		return -EINVAL;
>   	}
> @@ -1798,19 +1798,19 @@ static int icl_gamma_precision(const struct intel_crtc_state *crtc_state)
>   int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_state)
>   {
>   	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>   
> -	if (HAS_GMCH(dev_priv)) {
> -		if (IS_CHERRYVIEW(dev_priv))
> +	if (HAS_GMCH(i915)) {
> +		if (IS_CHERRYVIEW(i915))
>   			return chv_gamma_precision(crtc_state);
>   		else
>   			return i9xx_gamma_precision(crtc_state);
>   	} else {
> -		if (DISPLAY_VER(dev_priv) >= 11)
> +		if (DISPLAY_VER(i915) >= 11)
>   			return icl_gamma_precision(crtc_state);
> -		else if (DISPLAY_VER(dev_priv) == 10)
> +		else if (DISPLAY_VER(i915) == 10)
>   			return glk_gamma_precision(crtc_state);
> -		else if (IS_IRONLAKE(dev_priv))
> +		else if (IS_IRONLAKE(i915))
>   			return ilk_gamma_precision(crtc_state);
>   	}
>   
> @@ -1966,13 +1966,13 @@ static void i965_read_luts(struct intel_crtc_state *crtc_state)
>   
>   static struct drm_property_blob *chv_read_cgm_gamma(struct intel_crtc *crtc)
>   {
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -	int i, lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;
> +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> +	int i, lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size;
>   	enum pipe pipe = crtc->pipe;
>   	struct drm_property_blob *blob;
>   	struct drm_color_lut *lut;
>   
> -	blob = drm_property_create_blob(&dev_priv->drm,
> +	blob = drm_property_create_blob(&i915->drm,
>   					sizeof(lut[0]) * lut_size,
>   					NULL);
>   	if (IS_ERR(blob))
> @@ -1981,8 +1981,8 @@ static struct drm_property_blob *chv_read_cgm_gamma(struct intel_crtc *crtc)
>   	lut = blob->data;
>   
>   	for (i = 0; i < lut_size; i++) {
> -		u32 ldw = intel_de_read_fw(dev_priv, CGM_PIPE_GAMMA(pipe, i, 0));
> -		u32 udw = intel_de_read_fw(dev_priv, CGM_PIPE_GAMMA(pipe, i, 1));
> +		u32 ldw = intel_de_read_fw(i915, CGM_PIPE_GAMMA(pipe, i, 0));
> +		u32 udw = intel_de_read_fw(i915, CGM_PIPE_GAMMA(pipe, i, 1));
>   
>   		chv_cgm_gamma_pack(&lut[i], ldw, udw);
>   	}
> @@ -2002,13 +2002,13 @@ static void chv_read_luts(struct intel_crtc_state *crtc_state)
>   
>   static struct drm_property_blob *ilk_read_lut_8(struct intel_crtc *crtc)
>   {
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>   	enum pipe pipe = crtc->pipe;
>   	struct drm_property_blob *blob;
>   	struct drm_color_lut *lut;
>   	int i;
>   
> -	blob = drm_property_create_blob(&dev_priv->drm,
> +	blob = drm_property_create_blob(&i915->drm,
>   					sizeof(lut[0]) * LEGACY_LUT_LENGTH,
>   					NULL);
>   	if (IS_ERR(blob))
> @@ -2017,7 +2017,7 @@ static struct drm_property_blob *ilk_read_lut_8(struct intel_crtc *crtc)
>   	lut = blob->data;
>   
>   	for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
> -		u32 val = intel_de_read_fw(dev_priv, LGC_PALETTE(pipe, i));
> +		u32 val = intel_de_read_fw(i915, LGC_PALETTE(pipe, i));
>   
>   		i9xx_lut_8_pack(&lut[i], val);
>   	}
> @@ -2027,13 +2027,13 @@ static struct drm_property_blob *ilk_read_lut_8(struct intel_crtc *crtc)
>   
>   static struct drm_property_blob *ilk_read_lut_10(struct intel_crtc *crtc)
>   {
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -	int i, lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;
> +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> +	int i, lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size;
>   	enum pipe pipe = crtc->pipe;
>   	struct drm_property_blob *blob;
>   	struct drm_color_lut *lut;
>   
> -	blob = drm_property_create_blob(&dev_priv->drm,
> +	blob = drm_property_create_blob(&i915->drm,
>   					sizeof(lut[0]) * lut_size,
>   					NULL);
>   	if (IS_ERR(blob))
> @@ -2042,7 +2042,7 @@ static struct drm_property_blob *ilk_read_lut_10(struct intel_crtc *crtc)
>   	lut = blob->data;
>   
>   	for (i = 0; i < lut_size; i++) {
> -		u32 val = intel_de_read_fw(dev_priv, PREC_PALETTE(pipe, i));
> +		u32 val = intel_de_read_fw(i915, PREC_PALETTE(pipe, i));
>   
>   		ilk_lut_10_pack(&lut[i], val);
>   	}
> @@ -2077,16 +2077,16 @@ static void ilk_read_luts(struct intel_crtc_state *crtc_state)
>   static struct drm_property_blob *bdw_read_lut_10(struct intel_crtc *crtc,
>   						 u32 prec_index)
>   {
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>   	int i, hw_lut_size = ivb_lut_10_size(prec_index);
> -	int lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;
> +	int lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size;
>   	enum pipe pipe = crtc->pipe;
>   	struct drm_property_blob *blob;
>   	struct drm_color_lut *lut;
>   
> -	drm_WARN_ON(&dev_priv->drm, lut_size != hw_lut_size);
> +	drm_WARN_ON(&i915->drm, lut_size != hw_lut_size);
>   
> -	blob = drm_property_create_blob(&dev_priv->drm,
> +	blob = drm_property_create_blob(&i915->drm,
>   					sizeof(lut[0]) * lut_size,
>   					NULL);
>   	if (IS_ERR(blob))
> @@ -2094,16 +2094,16 @@ static struct drm_property_blob *bdw_read_lut_10(struct intel_crtc *crtc,
>   
>   	lut = blob->data;
>   
> -	intel_de_write_fw(dev_priv, PREC_PAL_INDEX(pipe),
> +	intel_de_write_fw(i915, PREC_PAL_INDEX(pipe),
>   			  prec_index | PAL_PREC_AUTO_INCREMENT);
>   
>   	for (i = 0; i < lut_size; i++) {
> -		u32 val = intel_de_read_fw(dev_priv, PREC_PAL_DATA(pipe));
> +		u32 val = intel_de_read_fw(i915, PREC_PAL_DATA(pipe));
>   
>   		ilk_lut_10_pack(&lut[i], val);
>   	}
>   
> -	intel_de_write_fw(dev_priv, PREC_PAL_INDEX(pipe), 0);
> +	intel_de_write_fw(i915, PREC_PAL_INDEX(pipe), 0);
>   
>   	return blob;
>   }
> @@ -2131,13 +2131,13 @@ static void glk_read_luts(struct intel_crtc_state *crtc_state)
>   static struct drm_property_blob *
>   icl_read_lut_multi_segment(struct intel_crtc *crtc)
>   {
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -	int i, lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;
> +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> +	int i, lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size;
>   	enum pipe pipe = crtc->pipe;
>   	struct drm_property_blob *blob;
>   	struct drm_color_lut *lut;
>   
> -	blob = drm_property_create_blob(&dev_priv->drm,
> +	blob = drm_property_create_blob(&i915->drm,
>   					sizeof(lut[0]) * lut_size,
>   					NULL);
>   	if (IS_ERR(blob))
> @@ -2145,17 +2145,17 @@ icl_read_lut_multi_segment(struct intel_crtc *crtc)
>   
>   	lut = blob->data;
>   
> -	intel_de_write_fw(dev_priv, PREC_PAL_MULTI_SEG_INDEX(pipe),
> +	intel_de_write_fw(i915, PREC_PAL_MULTI_SEG_INDEX(pipe),
>   			  PAL_PREC_AUTO_INCREMENT);
>   
>   	for (i = 0; i < 9; i++) {
> -		u32 ldw = intel_de_read_fw(dev_priv, PREC_PAL_MULTI_SEG_DATA(pipe));
> -		u32 udw = intel_de_read_fw(dev_priv, PREC_PAL_MULTI_SEG_DATA(pipe));
> +		u32 ldw = intel_de_read_fw(i915, PREC_PAL_MULTI_SEG_DATA(pipe));
> +		u32 udw = intel_de_read_fw(i915, PREC_PAL_MULTI_SEG_DATA(pipe));
>   
>   		icl_lut_multi_seg_pack(&lut[i], ldw, udw);
>   	}
>   
> -	intel_de_write_fw(dev_priv, PREC_PAL_MULTI_SEG_INDEX(pipe), 0);
> +	intel_de_write_fw(i915, PREC_PAL_MULTI_SEG_INDEX(pipe), 0);
>   
>   	/*
>   	 * FIXME readouts from PAL_PREC_DATA register aren't giving
> @@ -2268,15 +2268,15 @@ static const struct intel_color_funcs ilk_color_funcs = {
>   
>   void intel_color_crtc_init(struct intel_crtc *crtc)
>   {
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -	bool has_ctm = INTEL_INFO(dev_priv)->display.color.degamma_lut_size != 0;
> +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> +	bool has_ctm = INTEL_INFO(i915)->display.color.degamma_lut_size != 0;
>   
>   	drm_mode_crtc_set_gamma_size(&crtc->base, 256);
>   
>   	drm_crtc_enable_color_mgmt(&crtc->base,
> -				   INTEL_INFO(dev_priv)->display.color.degamma_lut_size,
> +				   INTEL_INFO(i915)->display.color.degamma_lut_size,
>   				   has_ctm,
> -				   INTEL_INFO(dev_priv)->display.color.gamma_lut_size);
> +				   INTEL_INFO(i915)->display.color.gamma_lut_size);
>   }
>   
>   int intel_color_init(struct drm_i915_private *i915)

Re: [Intel-gfx] [PATCH 04/11] drm/i915: s/icl_load_gcmax/ivb_load_lut_max/

[Nautiyal, Ankit K]

Seems the offset is same since IVB.

The Gamma correction max seem to be defined since IVB, but this doesnt 
seem to be used during ivb_load_luts, but only for multi-segmented gamma.

Is it that the default value of 1.0 is sufficient for other platforms?

Regards,

Ankit

On 10/26/2022 5:08 PM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Unify icl_load_gcmax() with the rest of the function
> naming scheme by calling it ivb_load_lut_max() instead.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_color.c | 6 +++---
>   1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index 415e0a6839a4..e73e6ea6f82f 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -935,8 +935,8 @@ static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color)
>   }
>   
>   static void
> -icl_load_gcmax(const struct intel_crtc_state *crtc_state,
> -	       const struct drm_color_lut *color)
> +ivb_load_lut_max(const struct intel_crtc_state *crtc_state,
> +		 const struct drm_color_lut *color)
>   {
>   	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>   	enum pipe pipe = crtc->pipe;
> @@ -1028,7 +1028,7 @@ icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)
>   
>   	/* The last entry in the LUT is to be programmed in GCMAX */
>   	entry = &lut[256 * 8 * 128];
> -	icl_load_gcmax(crtc_state, entry);
> +	ivb_load_lut_max(crtc_state, entry);
>   	ivb_load_lut_ext_max(crtc_state);
>   }
>   

Re: [Intel-gfx] [PATCH 05/11] drm/i915: Split ivb_load_lut_ext_max() into two parts

[Nautiyal, Ankit K]

Small typos in commit message (inline below)

Otherwise the change looks good to me

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>


On 10/26/2022 5:09 PM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Split the EXT2_MAX register progrmaming into its own funciton.

nitpick : 'programming' , 'function' typos.

Regards,

Ankit


> More in line with the whole "cobble together stuff from small
> pieces" approach used in this code.
>
> The EXT(2)_MAX registers are also not really part of the
> multi-segment section of the LUT, so hoise the calls to a
> higher level, just like we do in other gamma modes as well.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_color.c | 29 +++++++++++-----------
>   1 file changed, 14 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index e73e6ea6f82f..3b78b882e0c0 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -764,27 +764,23 @@ static void bdw_load_lut_10(struct intel_crtc *crtc,
>   static void ivb_load_lut_ext_max(const struct intel_crtc_state *crtc_state)
>   {
>   	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> -	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>   	enum pipe pipe = crtc->pipe;
>   
>   	/* Program the max register to clamp values > 1.0. */
>   	intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16);
>   	intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16);
>   	intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16);
> +}
>   
> -	/*
> -	 * Program the gc max 2 register to clamp values > 1.0.
> -	 * ToDo: Extend the ABI to be able to program values
> -	 * from 3.0 to 7.0
> -	 */
> -	if (DISPLAY_VER(i915) >= 10) {
> -		intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 0),
> -				    1 << 16);
> -		intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 1),
> -				    1 << 16);
> -		intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 2),
> -				    1 << 16);
> -	}
> +static void glk_load_lut_ext2_max(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	enum pipe pipe = crtc->pipe;
> +
> +	/* Program the max register to clamp values > 1.0. */	
> +	intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 0), 1 << 16);
> +	intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 1), 1 << 16);
> +	intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 2), 1 << 16);
>   }
>   
>   static void ivb_load_luts(const struct intel_crtc_state *crtc_state)
> @@ -913,6 +909,7 @@ static void glk_load_luts(const struct intel_crtc_state *crtc_state)
>   	case GAMMA_MODE_MODE_10BIT:
>   		bdw_load_lut_10(crtc, post_csc_lut, PAL_PREC_INDEX_VALUE(0));
>   		ivb_load_lut_ext_max(crtc_state);
> +		glk_load_lut_ext2_max(crtc_state);
>   		break;
>   	default:
>   		MISSING_CASE(crtc_state->gamma_mode);
> @@ -1029,7 +1026,6 @@ icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)
>   	/* The last entry in the LUT is to be programmed in GCMAX */
>   	entry = &lut[256 * 8 * 128];
>   	ivb_load_lut_max(crtc_state, entry);
> -	ivb_load_lut_ext_max(crtc_state);
>   }
>   
>   static void icl_load_luts(const struct intel_crtc_state *crtc_state)
> @@ -1048,10 +1044,13 @@ static void icl_load_luts(const struct intel_crtc_state *crtc_state)
>   	case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
>   		icl_program_gamma_superfine_segment(crtc_state);
>   		icl_program_gamma_multi_segment(crtc_state);
> +		ivb_load_lut_ext_max(crtc_state);
> +		glk_load_lut_ext2_max(crtc_state);
>   		break;
>   	case GAMMA_MODE_MODE_10BIT:
>   		bdw_load_lut_10(crtc, post_csc_lut, PAL_PREC_INDEX_VALUE(0));
>   		ivb_load_lut_ext_max(crtc_state);
> +		glk_load_lut_ext2_max(crtc_state);
>   		break;
>   	default:
>   		MISSING_CASE(crtc_state->gamma_mode);

Re: [Intel-gfx] [PATCH 06/11] drm/i915: Deconfuse the ilk+ 12.4 LUT entry functions

[Nautiyal, Ankit K]

LGTM.

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

On 10/26/2022 5:09 PM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> s/icl_lut_multi_seg_pack/ilk_lut_12p4_pack/ since that's what it is
> and group the corresponding "unpack" functions next to it.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_color.c | 38 +++++++++++-----------
>   1 file changed, 19 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index 3b78b882e0c0..e881c95ee451 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -482,14 +482,28 @@ static void ilk_lut_10_pack(struct drm_color_lut *entry, u32 val)
>   	entry->blue = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_BLUE_MASK, val), 10);
>   }
>   
> -static void icl_lut_multi_seg_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)
> +/* ilk+ "12.4" interpolated format (high 10 bits) */
> +static u32 ilk_lut_12p4_udw(const struct drm_color_lut *color)
> +{
> +	return (color->red >> 6) << 20 | (color->green >> 6) << 10 |
> +		(color->blue >> 6);
> +}
> +
> +/* ilk+ "12.4" interpolated format (low 6 bits) */
> +static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color)
> +{
> +	return (color->red & 0x3f) << 24 | (color->green & 0x3f) << 14 |
> +		(color->blue & 0x3f) << 4;
> +}
> +
> +static void ilk_lut_12p4_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)
>   {
>   	entry->red = REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK, udw) << 6 |
> -				   REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_LDW_MASK, ldw);
> +		REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_LDW_MASK, ldw);
>   	entry->green = REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, udw) << 6 |
> -				     REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, ldw);
> +		REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, ldw);
>   	entry->blue = REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK, udw) << 6 |
> -				    REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, ldw);
> +		REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, ldw);
>   }
>   
>   static void icl_color_commit_noarm(const struct intel_crtc_state *crtc_state)
> @@ -917,20 +931,6 @@ static void glk_load_luts(const struct intel_crtc_state *crtc_state)
>   	}
>   }
>   
> -/* ilk+ "12.4" interpolated format (high 10 bits) */
> -static u32 ilk_lut_12p4_udw(const struct drm_color_lut *color)
> -{
> -	return (color->red >> 6) << 20 | (color->green >> 6) << 10 |
> -		(color->blue >> 6);
> -}
> -
> -/* ilk+ "12.4" interpolated format (low 6 bits) */
> -static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color)
> -{
> -	return (color->red & 0x3f) << 24 | (color->green & 0x3f) << 14 |
> -		(color->blue & 0x3f) << 4;
> -}
> -
>   static void
>   ivb_load_lut_max(const struct intel_crtc_state *crtc_state,
>   		 const struct drm_color_lut *color)
> @@ -2151,7 +2151,7 @@ icl_read_lut_multi_segment(struct intel_crtc *crtc)
>   		u32 ldw = intel_de_read_fw(i915, PREC_PAL_MULTI_SEG_DATA(pipe));
>   		u32 udw = intel_de_read_fw(i915, PREC_PAL_MULTI_SEG_DATA(pipe));
>   
> -		icl_lut_multi_seg_pack(&lut[i], ldw, udw);
> +		ilk_lut_12p4_pack(&lut[i], ldw, udw);
>   	}
>   
>   	intel_de_write_fw(i915, PREC_PAL_MULTI_SEG_INDEX(pipe), 0);

Re: [Intel-gfx] [PATCH 04/11] drm/i915: s/icl_load_gcmax/ivb_load_lut_max/

[Ville Syrjälä]

On Thu, Nov 03, 2022 at 11:49:20AM +0530, Nautiyal, Ankit K wrote:
> Seems the offset is same since IVB.
> 
> The Gamma correction max seem to be defined since IVB, but this doesnt 
> seem to be used during ivb_load_luts, but only for multi-segmented gamma.

It would be used for the 12.4 interpolated gamma mode on
earlier platforms, but we don't expose that currently.

> 
> Is it that the default value of 1.0 is sufficient for other platforms?

Since it's not used in any of the gamma modes we do expose
it doesn't matter what we leave there atm.

> 
> Regards,
> 
> Ankit
> 
> On 10/26/2022 5:08 PM, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Unify icl_load_gcmax() with the rest of the function
> > naming scheme by calling it ivb_load_lut_max() instead.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >   drivers/gpu/drm/i915/display/intel_color.c | 6 +++---
> >   1 file changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> > index 415e0a6839a4..e73e6ea6f82f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_color.c
> > +++ b/drivers/gpu/drm/i915/display/intel_color.c
> > @@ -935,8 +935,8 @@ static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color)
> >   }
> >   
> >   static void
> > -icl_load_gcmax(const struct intel_crtc_state *crtc_state,
> > -	       const struct drm_color_lut *color)
> > +ivb_load_lut_max(const struct intel_crtc_state *crtc_state,
> > +		 const struct drm_color_lut *color)
> >   {
> >   	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >   	enum pipe pipe = crtc->pipe;
> > @@ -1028,7 +1028,7 @@ icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)
> >   
> >   	/* The last entry in the LUT is to be programmed in GCMAX */
> >   	entry = &lut[256 * 8 * 128];
> > -	icl_load_gcmax(crtc_state, entry);
> > +	ivb_load_lut_max(crtc_state, entry);
> >   	ivb_load_lut_ext_max(crtc_state);
> >   }
> >   

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH 06/11] drm/i915: Deconfuse the ilk+ 12.4 LUT entry functions

[Ville Syrjälä]

On Wed, Oct 26, 2022 at 02:39:01PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> s/icl_lut_multi_seg_pack/ilk_lut_12p4_pack/ since that's what it is
> and group the corresponding "unpack" functions next to it.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_color.c | 38 +++++++++++-----------
>  1 file changed, 19 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index 3b78b882e0c0..e881c95ee451 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -482,14 +482,28 @@ static void ilk_lut_10_pack(struct drm_color_lut *entry, u32 val)
>  	entry->blue = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_BLUE_MASK, val), 10);
>  }
>  
> -static void icl_lut_multi_seg_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)
> +/* ilk+ "12.4" interpolated format (high 10 bits) */
> +static u32 ilk_lut_12p4_udw(const struct drm_color_lut *color)
> +{
> +	return (color->red >> 6) << 20 | (color->green >> 6) << 10 |
> +		(color->blue >> 6);
> +}
> +
> +/* ilk+ "12.4" interpolated format (low 6 bits) */
> +static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color)
> +{
> +	return (color->red & 0x3f) << 24 | (color->green & 0x3f) << 14 |
> +		(color->blue & 0x3f) << 4;
> +}
> +
> +static void ilk_lut_12p4_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)
>  {
>  	entry->red = REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK, udw) << 6 |
> -				   REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_LDW_MASK, ldw);
> +		REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_LDW_MASK, ldw);
>  	entry->green = REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, udw) << 6 |
> -				     REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, ldw);
> +		REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, ldw);
>  	entry->blue = REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK, udw) << 6 |
> -				    REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, ldw);
> +		REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, ldw);

I just realized I had a patch somewhere to fix up the bit names as well.
But I can send that out in the next batch, assuming I can still find
it...

>  }
>  
>  static void icl_color_commit_noarm(const struct intel_crtc_state *crtc_state)
> @@ -917,20 +931,6 @@ static void glk_load_luts(const struct intel_crtc_state *crtc_state)
>  	}
>  }
>  
> -/* ilk+ "12.4" interpolated format (high 10 bits) */
> -static u32 ilk_lut_12p4_udw(const struct drm_color_lut *color)
> -{
> -	return (color->red >> 6) << 20 | (color->green >> 6) << 10 |
> -		(color->blue >> 6);
> -}
> -
> -/* ilk+ "12.4" interpolated format (low 6 bits) */
> -static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color)
> -{
> -	return (color->red & 0x3f) << 24 | (color->green & 0x3f) << 14 |
> -		(color->blue & 0x3f) << 4;
> -}
> -
>  static void
>  ivb_load_lut_max(const struct intel_crtc_state *crtc_state,
>  		 const struct drm_color_lut *color)
> @@ -2151,7 +2151,7 @@ icl_read_lut_multi_segment(struct intel_crtc *crtc)
>  		u32 ldw = intel_de_read_fw(i915, PREC_PAL_MULTI_SEG_DATA(pipe));
>  		u32 udw = intel_de_read_fw(i915, PREC_PAL_MULTI_SEG_DATA(pipe));
>  
> -		icl_lut_multi_seg_pack(&lut[i], ldw, udw);
> +		ilk_lut_12p4_pack(&lut[i], ldw, udw);
>  	}
>  
>  	intel_de_write_fw(i915, PREC_PAL_MULTI_SEG_INDEX(pipe), 0);
> -- 
> 2.37.4

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH 07/11] drm/i915: Pass limited_range explicitly to ilk_csc_convert_ctm()

[Nautiyal, Ankit K]

Looks good to me.

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

On 10/26/2022 5:09 PM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Since pre-icl vs. icl+ handle the limited range
> output stuff a bit differently it's probably
> less confusing if we just pass that information
> explicitly into ilk_csc_convert_ctm().
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_color.c | 8 ++++----
>   1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index e881c95ee451..946fb767f3e0 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -259,14 +259,14 @@ static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state)
>   }
>   
>   static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
> -				u16 coeffs[9])
> +				u16 coeffs[9], bool limited_color_range)
>   {
>   	const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
>   	const u64 *input;
>   	u64 temp[9];
>   	int i;
>   
> -	if (ilk_csc_limited_range(crtc_state))
> +	if (limited_color_range)
>   		input = ctm_mult_by_limited(temp, ctm->matrix);
>   	else
>   		input = ctm->matrix;
> @@ -319,7 +319,7 @@ static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
>   	if (crtc_state->hw.ctm) {
>   		u16 coeff[9];
>   
> -		ilk_csc_convert_ctm(crtc_state, coeff);
> +		ilk_csc_convert_ctm(crtc_state, coeff, limited_color_range);
>   		ilk_update_pipe_csc(crtc, ilk_csc_off_zero, coeff,
>   				    limited_color_range ?
>   				    ilk_csc_postoff_limited_range :
> @@ -354,7 +354,7 @@ static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state)
>   	if (crtc_state->hw.ctm) {
>   		u16 coeff[9];
>   
> -		ilk_csc_convert_ctm(crtc_state, coeff);
> +		ilk_csc_convert_ctm(crtc_state, coeff, false);

>   		ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
>   				    coeff, ilk_csc_off_zero);
>   	}

Re: [Intel-gfx] [PATCH 08/11] drm/i915: Reuse ilk_gamma_mode() on ivb+

[Nautiyal, Ankit K]

Makes sense. LGTM.

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

On 10/26/2022 5:09 PM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Apart from the split gamma mode ivb+ LUTs work just like ilk+ LUTs.
> So let's handle the special case, and then just fall back to
> ilk_gamma_mode() to avoid having to duplicate the same logic.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_color.c | 10 +++-------
>   1 file changed, 3 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index 946fb767f3e0..435394cad359 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1521,14 +1521,10 @@ static int ilk_color_check(struct intel_crtc_state *crtc_state)
>   
>   static u32 ivb_gamma_mode(const struct intel_crtc_state *crtc_state)
>   {
> -	if (!crtc_state->gamma_enable ||
> -	    crtc_state_is_legacy_gamma(crtc_state))
> -		return GAMMA_MODE_MODE_8BIT;
> -	else if (crtc_state->hw.gamma_lut &&
> -		 crtc_state->hw.degamma_lut)
> +	if (crtc_state->hw.degamma_lut && crtc_state->hw.gamma_lut)
>   		return GAMMA_MODE_MODE_SPLIT;
> -	else
> -		return GAMMA_MODE_MODE_10BIT;
> +
> +	return ilk_gamma_mode(crtc_state);
>   }
>   
>   static u32 ivb_csc_mode(const struct intel_crtc_state *crtc_state)

Re: [Intel-gfx] [PATCH 09/11] drm/i915: Reject YCbCr output with degamma+gamma on pre-icl

[Nautiyal, Ankit K]

LGTM.

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

On 10/26/2022 5:09 PM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Since the pipe CSC sits between the degamma and gamma LUTs there
> is no way to make us it for RGB->YCbCr conversion when both LUTs
> are also active. Simply reject such combos.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_color.c | 18 ++++++++++++++++--
>   1 file changed, 16 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index 435394cad359..926784f266f2 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1556,7 +1556,14 @@ static int ivb_color_check(struct intel_crtc_state *crtc_state)
>   	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB &&
>   	    crtc_state->hw.ctm) {
>   		drm_dbg_kms(&i915->drm,
> -			    "YCBCR and CTM together are not possible\n");
> +			    "YCbCr and CTM together are not possible\n");
> +		return -EINVAL;
> +	}
> +
> +	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB &&
> +	    crtc_state->hw.degamma_lut && crtc_state->hw.gamma_lut) {
> +		drm_dbg_kms(&i915->drm,
> +			    "YCbCr and degamma+gamma together are not possible\n");
>   		return -EINVAL;
>   	}
>   
> @@ -1622,7 +1629,14 @@ static int glk_color_check(struct intel_crtc_state *crtc_state)
>   	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB &&
>   	    crtc_state->hw.ctm) {
>   		drm_dbg_kms(&i915->drm,
> -			    "YCBCR and CTM together are not possible\n");
> +			    "YCbCr and CTM together are not possible\n");
> +		return -EINVAL;
> +	}
> +
> +	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB &&
> +	    crtc_state->hw.degamma_lut && crtc_state->hw.gamma_lut) {
> +		drm_dbg_kms(&i915->drm,
> +			    "YCbCr and degamma+gamma together are not possible\n");
>   		return -EINVAL;
>   	}
>   

Re: [Intel-gfx] [PATCH 10/11] drm/i915: Share {csc, gamma}_enable calculation for ilk/snb vs. ivb+

[Nautiyal, Ankit K]

LGTM.

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

On 10/26/2022 5:09 PM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> ilk/snb vs. ivb+ hardware is mostly identical except for the addition
> of the split gamma mode on ivb. Thus we can share the csc_enable
> and gamma_enable calculation for both variants. Pull that stuff
> into a few helpers.
>
> Note that this also fills in the missing ctm/degamma stuff into
> ilk_color_check() pretty much, so for good measure let's also
> add a few extra checks relating to that, although we still don't
> expose ctm/degamma to userspace. But now it'll be trivial to do
> so if we wish.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_color.c | 49 ++++++++++++++--------
>   1 file changed, 32 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index 926784f266f2..33871bfacee7 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1442,6 +1442,20 @@ static int chv_color_check(struct intel_crtc_state *crtc_state)
>   	return 0;
>   }
>   
> +static bool ilk_gamma_enable(const struct intel_crtc_state *crtc_state)
> +{
> +	return (crtc_state->hw.gamma_lut ||
> +		crtc_state->hw.degamma_lut) &&
> +		!crtc_state->c8_planes;
> +}
> +
> +static bool ilk_csc_enable(const struct intel_crtc_state *crtc_state)
> +{
> +	return crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
> +		ilk_csc_limited_range(crtc_state) ||
> +		crtc_state->hw.ctm;
> +}
> +
>   static u32 ilk_gamma_mode(const struct intel_crtc_state *crtc_state)
>   {
>   	if (!crtc_state->gamma_enable ||
> @@ -1487,22 +1501,29 @@ static void ilk_assign_luts(struct intel_crtc_state *crtc_state)
>   
>   static int ilk_color_check(struct intel_crtc_state *crtc_state)
>   {
> +	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
>   	int ret;
>   
>   	ret = check_luts(crtc_state);
>   	if (ret)
>   		return ret;
>   
> -	crtc_state->gamma_enable =
> -		crtc_state->hw.gamma_lut &&
> -		!crtc_state->c8_planes;
> +	if (crtc_state->hw.degamma_lut && crtc_state->hw.gamma_lut) {
> +		drm_dbg_kms(&i915->drm,
> +			    "Degamma and gamma together are not possible\n");
> +		return -EINVAL;
> +	}
>   
> -	/*
> -	 * We don't expose the ctm on ilk/snb currently, also RGB
> -	 * limited range output is handled by the hw automagically.
> -	 */
> -	crtc_state->csc_enable =
> -		crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB;
> +	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB &&
> +	    crtc_state->hw.ctm) {
> +		drm_dbg_kms(&i915->drm,
> +			    "YCbCr and CTM together are not possible\n");
> +		return -EINVAL;
> +	}
> +
> +	crtc_state->gamma_enable = ilk_gamma_enable(crtc_state);
> +
> +	crtc_state->csc_enable = ilk_csc_enable(crtc_state);
>   
>   	crtc_state->gamma_mode = ilk_gamma_mode(crtc_state);
>   
> @@ -1546,7 +1567,6 @@ static u32 ivb_csc_mode(const struct intel_crtc_state *crtc_state)
>   static int ivb_color_check(struct intel_crtc_state *crtc_state)
>   {
>   	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> -	bool limited_color_range = ilk_csc_limited_range(crtc_state);
>   	int ret;
>   
>   	ret = check_luts(crtc_state);
> @@ -1567,14 +1587,9 @@ static int ivb_color_check(struct intel_crtc_state *crtc_state)
>   		return -EINVAL;
>   	}
>   
> -	crtc_state->gamma_enable =
> -		(crtc_state->hw.gamma_lut ||
> -		 crtc_state->hw.degamma_lut) &&
> -		!crtc_state->c8_planes;
> +	crtc_state->gamma_enable = ilk_gamma_enable(crtc_state);
>   
> -	crtc_state->csc_enable =
> -		crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
> -		crtc_state->hw.ctm || limited_color_range;
> +	crtc_state->csc_enable = ilk_csc_enable(crtc_state);
>   
>   	crtc_state->gamma_mode = ivb_gamma_mode(crtc_state);
>   

Re: [Intel-gfx] [PATCH 04/11] drm/i915: s/icl_load_gcmax/ivb_load_lut_max/

[Nautiyal, Ankit K]

On 11/3/2022 3:04 PM, Ville Syrjälä wrote:
> On Thu, Nov 03, 2022 at 11:49:20AM +0530, Nautiyal, Ankit K wrote:
>> Seems the offset is same since IVB.
>>
>> The Gamma correction max seem to be defined since IVB, but this doesnt
>> seem to be used during ivb_load_luts, but only for multi-segmented gamma.
> It would be used for the 12.4 interpolated gamma mode on
> earlier platforms, but we don't expose that currently.
>
>> Is it that the default value of 1.0 is sufficient for other platforms?
> Since it's not used in any of the gamma modes we do expose
> it doesn't matter what we leave there atm.


Fair enough.

LGTM.

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>


>
>> Regards,
>>
>> Ankit
>>
>> On 10/26/2022 5:08 PM, Ville Syrjala wrote:
>>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>>
>>> Unify icl_load_gcmax() with the rest of the function
>>> naming scheme by calling it ivb_load_lut_max() instead.
>>>
>>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>> ---
>>>    drivers/gpu/drm/i915/display/intel_color.c | 6 +++---
>>>    1 file changed, 3 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
>>> index 415e0a6839a4..e73e6ea6f82f 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_color.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_color.c
>>> @@ -935,8 +935,8 @@ static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color)
>>>    }
>>>    
>>>    static void
>>> -icl_load_gcmax(const struct intel_crtc_state *crtc_state,
>>> -	       const struct drm_color_lut *color)
>>> +ivb_load_lut_max(const struct intel_crtc_state *crtc_state,
>>> +		 const struct drm_color_lut *color)
>>>    {
>>>    	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>>>    	enum pipe pipe = crtc->pipe;
>>> @@ -1028,7 +1028,7 @@ icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)
>>>    
>>>    	/* The last entry in the LUT is to be programmed in GCMAX */
>>>    	entry = &lut[256 * 8 * 128];
>>> -	icl_load_gcmax(crtc_state, entry);
>>> +	ivb_load_lut_max(crtc_state, entry);
>>>    	ivb_load_lut_ext_max(crtc_state);
>>>    }
>>>    

Re: [Intel-gfx] [PATCH 11/11] drm/i915: Create resized LUTs for ivb+ split gamma mode

[Nautiyal, Ankit K]

Patch looks good to me.

Minor suggestions inline:

On 10/26/2022 5:09 PM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Currently when opeating in split gamma mode we do the
nitpick: 'operating' typo.
> "skip ever other sw LUT entry" trick in the low level
> LUT programming/readout functions. That is very annoying
> and a big hinderance to revamping the color management
> uapi.
>
> Let's get rid of that problem by making half sized copies
> of the software LUTs and plugging those into the internal
> {pre,post}_csc_lut attachment points (instead of the sticking
> the uapi provide sw LUTs there directly).
>
> With this the low level stuff will operate purely in terms
> the hardware LUT sizes, and all uapi nonsense is contained
> to the atomic check phase. The one thing we do lose is
> intel_color_assert_luts() since we no longer have a way to
> check that the uapi LUTs were correctly used when generating
> the internal copies. But that seems like a price worth paying.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_color.c | 81 +++++++++++++++++-----
>   1 file changed, 64 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index 33871bfacee7..d48904f90e3a 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -597,6 +597,30 @@ create_linear_lut(struct drm_i915_private *i915, int lut_size)
>   	return blob;
>   }
>   
> +static struct drm_property_blob *
> +create_resized_lut(struct drm_i915_private *i915,
> +		   const struct drm_property_blob *blob_in, int lut_out_size)
> +{
> +	int i, lut_in_size = drm_color_lut_size(blob_in);
> +	struct drm_property_blob *blob_out;
> +	const struct drm_color_lut *lut_in;
> +	struct drm_color_lut *lut_out;
> +
> +	blob_out = drm_property_create_blob(&i915->drm,
> +					    sizeof(lut_out[0]) * lut_out_size,
> +					    NULL);
> +	if (IS_ERR(blob_out))
> +		return blob_out;
> +
> +	lut_in = blob_in->data;
> +	lut_out = blob_out->data;
> +
> +	for (i = 0; i < lut_out_size; i++)
> +		lut_out[i] = lut_in[i * (lut_in_size - 1) / (lut_out_size - 1)];
> +
> +	return blob_out;
> +}
> +
>   static void i9xx_load_lut_8(struct intel_crtc *crtc,
>   			    const struct drm_property_blob *blob)
>   {
> @@ -723,19 +747,14 @@ static void ivb_load_lut_10(struct intel_crtc *crtc,
>   			    u32 prec_index)
>   {
>   	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> -	int hw_lut_size = ivb_lut_10_size(prec_index);
>   	const struct drm_color_lut *lut = blob->data;
>   	int i, lut_size = drm_color_lut_size(blob);
>   	enum pipe pipe = crtc->pipe;
>   
> -	for (i = 0; i < hw_lut_size; i++) {
> -		/* We discard half the user entries in split gamma mode */
> -		const struct drm_color_lut *entry =
> -			&lut[i * (lut_size - 1) / (hw_lut_size - 1)];
> -
> +	for (i = 0; i < lut_size; i++) {
>   		intel_de_write_fw(i915, PREC_PAL_INDEX(pipe), prec_index++);
>   		intel_de_write_fw(i915, PREC_PAL_DATA(pipe),
> -				  ilk_lut_10(entry));
> +				  ilk_lut_10(&lut[i]));
>   	}
>   
>   	/*
> @@ -751,7 +770,6 @@ static void bdw_load_lut_10(struct intel_crtc *crtc,
>   			    u32 prec_index)
>   {
>   	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> -	int hw_lut_size = ivb_lut_10_size(prec_index);
>   	const struct drm_color_lut *lut = blob->data;
>   	int i, lut_size = drm_color_lut_size(blob);
>   	enum pipe pipe = crtc->pipe;
> @@ -759,14 +777,9 @@ static void bdw_load_lut_10(struct intel_crtc *crtc,
>   	intel_de_write_fw(i915, PREC_PAL_INDEX(pipe),
>   			  prec_index | PAL_PREC_AUTO_INCREMENT);
>   
> -	for (i = 0; i < hw_lut_size; i++) {
> -		/* We discard half the user entries in split gamma mode */
> -		const struct drm_color_lut *entry =
> -			&lut[i * (lut_size - 1) / (hw_lut_size - 1)];
> -
> +	for (i = 0; i < lut_size; i++)
>   		intel_de_write_fw(i915, PREC_PAL_DATA(pipe),
> -				  ilk_lut_10(entry));
> -	}
> +				  ilk_lut_10(&lut[i]));
>   
>   	/*
>   	 * Reset the index, otherwise it prevents the legacy palette to be
> @@ -1343,7 +1356,7 @@ void intel_color_assert_luts(const struct intel_crtc_state *crtc_state)
>   			    crtc_state->pre_csc_lut != i915->display.color.glk_linear_degamma_lut);
>   		drm_WARN_ON(&i915->drm,
>   			    crtc_state->post_csc_lut != crtc_state->hw.gamma_lut);
> -	} else {
> +	} else if (crtc_state->gamma_mode != GAMMA_MODE_MODE_SPLIT) {
>   		drm_WARN_ON(&i915->drm,
>   			    crtc_state->pre_csc_lut != crtc_state->hw.degamma_lut &&
>   			    crtc_state->pre_csc_lut != crtc_state->hw.gamma_lut);
> @@ -1564,6 +1577,38 @@ static u32 ivb_csc_mode(const struct intel_crtc_state *crtc_state)
>   	return CSC_POSITION_BEFORE_GAMMA;
>   }
>   
> +static int ivb_assign_luts(struct intel_crtc_state *crtc_state)
> +{
> +	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> +	struct drm_property_blob *degamma_lut, *gamma_lut;
> +
> +	if (crtc_state->gamma_mode != GAMMA_MODE_MODE_SPLIT) {
> +		ilk_assign_luts(crtc_state);
> +		return 0;
> +	}
> +
> +	drm_WARN_ON(&i915->drm, drm_color_lut_size(crtc_state->hw.degamma_lut) != 1024);
> +	drm_WARN_ON(&i915->drm, drm_color_lut_size(crtc_state->hw.gamma_lut) != 1024);

Does it make sense to use some macro for LUT size for split gamma case 
and regular case?

Same thing perhaps can be used in ivb_lut_10_size?


Regards,

Ankit


> +
> +	degamma_lut = create_resized_lut(i915, crtc_state->hw.degamma_lut, 512);
> +	if (IS_ERR(degamma_lut))
> +		return PTR_ERR(degamma_lut);
> +
> +	gamma_lut = create_resized_lut(i915, crtc_state->hw.gamma_lut, 512);
> +	if (IS_ERR(gamma_lut)) {
> +		drm_property_blob_put(degamma_lut);
> +		return PTR_ERR(gamma_lut);
> +	}
> +
> +	drm_property_replace_blob(&crtc_state->pre_csc_lut, degamma_lut);
> +	drm_property_replace_blob(&crtc_state->post_csc_lut, gamma_lut);
> +
> +	drm_property_blob_put(degamma_lut);
> +	drm_property_blob_put(gamma_lut);
> +
> +	return 0;
> +}
> +
>   static int ivb_color_check(struct intel_crtc_state *crtc_state)
>   {
>   	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> @@ -1599,7 +1644,9 @@ static int ivb_color_check(struct intel_crtc_state *crtc_state)
>   	if (ret)
>   		return ret;
>   
> -	ilk_assign_luts(crtc_state);
> +	ret = ivb_assign_luts(crtc_state);
> +	if (ret)
> +		return ret;
>   
>   	crtc_state->preload_luts = intel_can_preload_luts(crtc_state);
>   

Re: [Intel-gfx] [PATCH 11/11] drm/i915: Create resized LUTs for ivb+ split gamma mode

[Ville Syrjälä]

On Fri, Nov 04, 2022 at 10:49:39AM +0530, Nautiyal, Ankit K wrote:
> Patch looks good to me.
> 
> Minor suggestions inline:
> 
> On 10/26/2022 5:09 PM, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Currently when opeating in split gamma mode we do the
> nitpick: 'operating' typo.
> > "skip ever other sw LUT entry" trick in the low level
> > LUT programming/readout functions. That is very annoying
> > and a big hinderance to revamping the color management
> > uapi.
> >
> > Let's get rid of that problem by making half sized copies
> > of the software LUTs and plugging those into the internal
> > {pre,post}_csc_lut attachment points (instead of the sticking
> > the uapi provide sw LUTs there directly).
> >
> > With this the low level stuff will operate purely in terms
> > the hardware LUT sizes, and all uapi nonsense is contained
> > to the atomic check phase. The one thing we do lose is
> > intel_color_assert_luts() since we no longer have a way to
> > check that the uapi LUTs were correctly used when generating
> > the internal copies. But that seems like a price worth paying.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >   drivers/gpu/drm/i915/display/intel_color.c | 81 +++++++++++++++++-----
> >   1 file changed, 64 insertions(+), 17 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> > index 33871bfacee7..d48904f90e3a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_color.c
> > +++ b/drivers/gpu/drm/i915/display/intel_color.c
> > @@ -597,6 +597,30 @@ create_linear_lut(struct drm_i915_private *i915, int lut_size)
> >   	return blob;
> >   }
> >   
> > +static struct drm_property_blob *
> > +create_resized_lut(struct drm_i915_private *i915,
> > +		   const struct drm_property_blob *blob_in, int lut_out_size)
> > +{
> > +	int i, lut_in_size = drm_color_lut_size(blob_in);
> > +	struct drm_property_blob *blob_out;
> > +	const struct drm_color_lut *lut_in;
> > +	struct drm_color_lut *lut_out;
> > +
> > +	blob_out = drm_property_create_blob(&i915->drm,
> > +					    sizeof(lut_out[0]) * lut_out_size,
> > +					    NULL);
> > +	if (IS_ERR(blob_out))
> > +		return blob_out;
> > +
> > +	lut_in = blob_in->data;
> > +	lut_out = blob_out->data;
> > +
> > +	for (i = 0; i < lut_out_size; i++)
> > +		lut_out[i] = lut_in[i * (lut_in_size - 1) / (lut_out_size - 1)];
> > +
> > +	return blob_out;
> > +}
> > +
> >   static void i9xx_load_lut_8(struct intel_crtc *crtc,
> >   			    const struct drm_property_blob *blob)
> >   {
> > @@ -723,19 +747,14 @@ static void ivb_load_lut_10(struct intel_crtc *crtc,
> >   			    u32 prec_index)
> >   {
> >   	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> > -	int hw_lut_size = ivb_lut_10_size(prec_index);
> >   	const struct drm_color_lut *lut = blob->data;
> >   	int i, lut_size = drm_color_lut_size(blob);
> >   	enum pipe pipe = crtc->pipe;
> >   
> > -	for (i = 0; i < hw_lut_size; i++) {
> > -		/* We discard half the user entries in split gamma mode */
> > -		const struct drm_color_lut *entry =
> > -			&lut[i * (lut_size - 1) / (hw_lut_size - 1)];
> > -
> > +	for (i = 0; i < lut_size; i++) {
> >   		intel_de_write_fw(i915, PREC_PAL_INDEX(pipe), prec_index++);
> >   		intel_de_write_fw(i915, PREC_PAL_DATA(pipe),
> > -				  ilk_lut_10(entry));
> > +				  ilk_lut_10(&lut[i]));
> >   	}
> >   
> >   	/*
> > @@ -751,7 +770,6 @@ static void bdw_load_lut_10(struct intel_crtc *crtc,
> >   			    u32 prec_index)
> >   {
> >   	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> > -	int hw_lut_size = ivb_lut_10_size(prec_index);
> >   	const struct drm_color_lut *lut = blob->data;
> >   	int i, lut_size = drm_color_lut_size(blob);
> >   	enum pipe pipe = crtc->pipe;
> > @@ -759,14 +777,9 @@ static void bdw_load_lut_10(struct intel_crtc *crtc,
> >   	intel_de_write_fw(i915, PREC_PAL_INDEX(pipe),
> >   			  prec_index | PAL_PREC_AUTO_INCREMENT);
> >   
> > -	for (i = 0; i < hw_lut_size; i++) {
> > -		/* We discard half the user entries in split gamma mode */
> > -		const struct drm_color_lut *entry =
> > -			&lut[i * (lut_size - 1) / (hw_lut_size - 1)];
> > -
> > +	for (i = 0; i < lut_size; i++)
> >   		intel_de_write_fw(i915, PREC_PAL_DATA(pipe),
> > -				  ilk_lut_10(entry));
> > -	}
> > +				  ilk_lut_10(&lut[i]));
> >   
> >   	/*
> >   	 * Reset the index, otherwise it prevents the legacy palette to be
> > @@ -1343,7 +1356,7 @@ void intel_color_assert_luts(const struct intel_crtc_state *crtc_state)
> >   			    crtc_state->pre_csc_lut != i915->display.color.glk_linear_degamma_lut);
> >   		drm_WARN_ON(&i915->drm,
> >   			    crtc_state->post_csc_lut != crtc_state->hw.gamma_lut);
> > -	} else {
> > +	} else if (crtc_state->gamma_mode != GAMMA_MODE_MODE_SPLIT) {
> >   		drm_WARN_ON(&i915->drm,
> >   			    crtc_state->pre_csc_lut != crtc_state->hw.degamma_lut &&
> >   			    crtc_state->pre_csc_lut != crtc_state->hw.gamma_lut);
> > @@ -1564,6 +1577,38 @@ static u32 ivb_csc_mode(const struct intel_crtc_state *crtc_state)
> >   	return CSC_POSITION_BEFORE_GAMMA;
> >   }
> >   
> > +static int ivb_assign_luts(struct intel_crtc_state *crtc_state)
> > +{
> > +	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> > +	struct drm_property_blob *degamma_lut, *gamma_lut;
> > +
> > +	if (crtc_state->gamma_mode != GAMMA_MODE_MODE_SPLIT) {
> > +		ilk_assign_luts(crtc_state);
> > +		return 0;
> > +	}
> > +
> > +	drm_WARN_ON(&i915->drm, drm_color_lut_size(crtc_state->hw.degamma_lut) != 1024);
> > +	drm_WARN_ON(&i915->drm, drm_color_lut_size(crtc_state->hw.gamma_lut) != 1024);
> 
> Does it make sense to use some macro for LUT size for split gamma case 
> and regular case?
> 
> Same thing perhaps can be used in ivb_lut_10_size?

I don't think macros would be really helpful. I guess I 
could have used ivb_lut_10_size() for the create_resized_lut()
calls below. And these WARNs I guess could have just used
device info stuff instead. Or I could just drop them entirely
since they aren't really checking anything super important, and
the create_resized_lut() would work with any input LUT size anyway.

Thinking a bit further we could certainly consider extending
the ivb_lut_10_size()/glk_degamma_lut_size() approach to cover
all the gamma modes. Though I think it would probably make sense
to implement that as some kind of struct based approach where we
describe each LUT format in a struct. Would also be more in line
with what we've been thinking for the uapi revamp.

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH 11/11] drm/i915: Create resized LUTs for ivb+ split gamma mode

[Nautiyal, Ankit K]

On 11/4/2022 3:12 PM, Ville Syrjälä wrote:
> On Fri, Nov 04, 2022 at 10:49:39AM +0530, Nautiyal, Ankit K wrote:
>> Patch looks good to me.
>>
>> Minor suggestions inline:
>>
>> On 10/26/2022 5:09 PM, Ville Syrjala wrote:
>>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>>
>>> Currently when opeating in split gamma mode we do the
>> nitpick: 'operating' typo.
>>> "skip ever other sw LUT entry" trick in the low level
>>> LUT programming/readout functions. That is very annoying
>>> and a big hinderance to revamping the color management
>>> uapi.
>>>
>>> Let's get rid of that problem by making half sized copies
>>> of the software LUTs and plugging those into the internal
>>> {pre,post}_csc_lut attachment points (instead of the sticking
>>> the uapi provide sw LUTs there directly).
>>>
>>> With this the low level stuff will operate purely in terms
>>> the hardware LUT sizes, and all uapi nonsense is contained
>>> to the atomic check phase. The one thing we do lose is
>>> intel_color_assert_luts() since we no longer have a way to
>>> check that the uapi LUTs were correctly used when generating
>>> the internal copies. But that seems like a price worth paying.
>>>
>>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>> ---
>>>    drivers/gpu/drm/i915/display/intel_color.c | 81 +++++++++++++++++-----
>>>    1 file changed, 64 insertions(+), 17 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
>>> index 33871bfacee7..d48904f90e3a 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_color.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_color.c
>>> @@ -597,6 +597,30 @@ create_linear_lut(struct drm_i915_private *i915, int lut_size)
>>>    	return blob;
>>>    }
>>>    
>>> +static struct drm_property_blob *
>>> +create_resized_lut(struct drm_i915_private *i915,
>>> +		   const struct drm_property_blob *blob_in, int lut_out_size)
>>> +{
>>> +	int i, lut_in_size = drm_color_lut_size(blob_in);
>>> +	struct drm_property_blob *blob_out;
>>> +	const struct drm_color_lut *lut_in;
>>> +	struct drm_color_lut *lut_out;
>>> +
>>> +	blob_out = drm_property_create_blob(&i915->drm,
>>> +					    sizeof(lut_out[0]) * lut_out_size,
>>> +					    NULL);
>>> +	if (IS_ERR(blob_out))
>>> +		return blob_out;
>>> +
>>> +	lut_in = blob_in->data;
>>> +	lut_out = blob_out->data;
>>> +
>>> +	for (i = 0; i < lut_out_size; i++)
>>> +		lut_out[i] = lut_in[i * (lut_in_size - 1) / (lut_out_size - 1)];
>>> +
>>> +	return blob_out;
>>> +}
>>> +
>>>    static void i9xx_load_lut_8(struct intel_crtc *crtc,
>>>    			    const struct drm_property_blob *blob)
>>>    {
>>> @@ -723,19 +747,14 @@ static void ivb_load_lut_10(struct intel_crtc *crtc,
>>>    			    u32 prec_index)
>>>    {
>>>    	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>>> -	int hw_lut_size = ivb_lut_10_size(prec_index);
>>>    	const struct drm_color_lut *lut = blob->data;
>>>    	int i, lut_size = drm_color_lut_size(blob);
>>>    	enum pipe pipe = crtc->pipe;
>>>    
>>> -	for (i = 0; i < hw_lut_size; i++) {
>>> -		/* We discard half the user entries in split gamma mode */
>>> -		const struct drm_color_lut *entry =
>>> -			&lut[i * (lut_size - 1) / (hw_lut_size - 1)];
>>> -
>>> +	for (i = 0; i < lut_size; i++) {
>>>    		intel_de_write_fw(i915, PREC_PAL_INDEX(pipe), prec_index++);
>>>    		intel_de_write_fw(i915, PREC_PAL_DATA(pipe),
>>> -				  ilk_lut_10(entry));
>>> +				  ilk_lut_10(&lut[i]));
>>>    	}
>>>    
>>>    	/*
>>> @@ -751,7 +770,6 @@ static void bdw_load_lut_10(struct intel_crtc *crtc,
>>>    			    u32 prec_index)
>>>    {
>>>    	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>>> -	int hw_lut_size = ivb_lut_10_size(prec_index);
>>>    	const struct drm_color_lut *lut = blob->data;
>>>    	int i, lut_size = drm_color_lut_size(blob);
>>>    	enum pipe pipe = crtc->pipe;
>>> @@ -759,14 +777,9 @@ static void bdw_load_lut_10(struct intel_crtc *crtc,
>>>    	intel_de_write_fw(i915, PREC_PAL_INDEX(pipe),
>>>    			  prec_index | PAL_PREC_AUTO_INCREMENT);
>>>    
>>> -	for (i = 0; i < hw_lut_size; i++) {
>>> -		/* We discard half the user entries in split gamma mode */
>>> -		const struct drm_color_lut *entry =
>>> -			&lut[i * (lut_size - 1) / (hw_lut_size - 1)];
>>> -
>>> +	for (i = 0; i < lut_size; i++)
>>>    		intel_de_write_fw(i915, PREC_PAL_DATA(pipe),
>>> -				  ilk_lut_10(entry));
>>> -	}
>>> +				  ilk_lut_10(&lut[i]));
>>>    
>>>    	/*
>>>    	 * Reset the index, otherwise it prevents the legacy palette to be
>>> @@ -1343,7 +1356,7 @@ void intel_color_assert_luts(const struct intel_crtc_state *crtc_state)
>>>    			    crtc_state->pre_csc_lut != i915->display.color.glk_linear_degamma_lut);
>>>    		drm_WARN_ON(&i915->drm,
>>>    			    crtc_state->post_csc_lut != crtc_state->hw.gamma_lut);
>>> -	} else {
>>> +	} else if (crtc_state->gamma_mode != GAMMA_MODE_MODE_SPLIT) {
>>>    		drm_WARN_ON(&i915->drm,
>>>    			    crtc_state->pre_csc_lut != crtc_state->hw.degamma_lut &&
>>>    			    crtc_state->pre_csc_lut != crtc_state->hw.gamma_lut);
>>> @@ -1564,6 +1577,38 @@ static u32 ivb_csc_mode(const struct intel_crtc_state *crtc_state)
>>>    	return CSC_POSITION_BEFORE_GAMMA;
>>>    }
>>>    
>>> +static int ivb_assign_luts(struct intel_crtc_state *crtc_state)
>>> +{
>>> +	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
>>> +	struct drm_property_blob *degamma_lut, *gamma_lut;
>>> +
>>> +	if (crtc_state->gamma_mode != GAMMA_MODE_MODE_SPLIT) {
>>> +		ilk_assign_luts(crtc_state);
>>> +		return 0;
>>> +	}
>>> +
>>> +	drm_WARN_ON(&i915->drm, drm_color_lut_size(crtc_state->hw.degamma_lut) != 1024);
>>> +	drm_WARN_ON(&i915->drm, drm_color_lut_size(crtc_state->hw.gamma_lut) != 1024);
>> Does it make sense to use some macro for LUT size for split gamma case
>> and regular case?
>>
>> Same thing perhaps can be used in ivb_lut_10_size?
> I don't think macros would be really helpful. I guess I
> could have used ivb_lut_10_size() for the create_resized_lut()
> calls below. And these WARNs I guess could have just used
> device info stuff instead.

Using ivb_lut_10_size() should be good enough, I think.

In any case, this is a just a minor suggestion. Patch looks good to me.

With the small typo fixed in commit message:

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>


Regards,

Ankit


> Or I could just drop them entirely
> since they aren't really checking anything super important, and
> the create_resized_lut() would work with any input LUT size anyway.
>
> Thinking a bit further we could certainly consider extending
> the ivb_lut_10_size()/glk_degamma_lut_size() approach to cover
> all the gamma modes. Though I think it would probably make sense
> to implement that as some kind of struct based approach where we
> describe each LUT format in a struct. Would also be more in line
> with what we've been thinking for the uapi revamp.
>

Re: [Intel-gfx] [PATCH 11/11] drm/i915: Create resized LUTs for ivb+ split gamma mode

[Ville Syrjälä]

On Thu, Nov 10, 2022 at 09:35:28AM +0530, Nautiyal, Ankit K wrote:
> 
> On 11/4/2022 3:12 PM, Ville Syrjälä wrote:
> > On Fri, Nov 04, 2022 at 10:49:39AM +0530, Nautiyal, Ankit K wrote:
> >> Patch looks good to me.
> >>
> >> Minor suggestions inline:
> >>
> >> On 10/26/2022 5:09 PM, Ville Syrjala wrote:
> >>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >>>
> >>> Currently when opeating in split gamma mode we do the
> >> nitpick: 'operating' typo.
> >>> "skip ever other sw LUT entry" trick in the low level
> >>> LUT programming/readout functions. That is very annoying
> >>> and a big hinderance to revamping the color management
> >>> uapi.
> >>>
> >>> Let's get rid of that problem by making half sized copies
> >>> of the software LUTs and plugging those into the internal
> >>> {pre,post}_csc_lut attachment points (instead of the sticking
> >>> the uapi provide sw LUTs there directly).
> >>>
> >>> With this the low level stuff will operate purely in terms
> >>> the hardware LUT sizes, and all uapi nonsense is contained
> >>> to the atomic check phase. The one thing we do lose is
> >>> intel_color_assert_luts() since we no longer have a way to
> >>> check that the uapi LUTs were correctly used when generating
> >>> the internal copies. But that seems like a price worth paying.
> >>>
> >>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >>> ---
> >>>    drivers/gpu/drm/i915/display/intel_color.c | 81 +++++++++++++++++-----
> >>>    1 file changed, 64 insertions(+), 17 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> >>> index 33871bfacee7..d48904f90e3a 100644
> >>> --- a/drivers/gpu/drm/i915/display/intel_color.c
> >>> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> >>> @@ -597,6 +597,30 @@ create_linear_lut(struct drm_i915_private *i915, int lut_size)
> >>>    	return blob;
> >>>    }
> >>>    
> >>> +static struct drm_property_blob *
> >>> +create_resized_lut(struct drm_i915_private *i915,
> >>> +		   const struct drm_property_blob *blob_in, int lut_out_size)
> >>> +{
> >>> +	int i, lut_in_size = drm_color_lut_size(blob_in);
> >>> +	struct drm_property_blob *blob_out;
> >>> +	const struct drm_color_lut *lut_in;
> >>> +	struct drm_color_lut *lut_out;
> >>> +
> >>> +	blob_out = drm_property_create_blob(&i915->drm,
> >>> +					    sizeof(lut_out[0]) * lut_out_size,
> >>> +					    NULL);
> >>> +	if (IS_ERR(blob_out))
> >>> +		return blob_out;
> >>> +
> >>> +	lut_in = blob_in->data;
> >>> +	lut_out = blob_out->data;
> >>> +
> >>> +	for (i = 0; i < lut_out_size; i++)
> >>> +		lut_out[i] = lut_in[i * (lut_in_size - 1) / (lut_out_size - 1)];
> >>> +
> >>> +	return blob_out;
> >>> +}
> >>> +
> >>>    static void i9xx_load_lut_8(struct intel_crtc *crtc,
> >>>    			    const struct drm_property_blob *blob)
> >>>    {
> >>> @@ -723,19 +747,14 @@ static void ivb_load_lut_10(struct intel_crtc *crtc,
> >>>    			    u32 prec_index)
> >>>    {
> >>>    	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> >>> -	int hw_lut_size = ivb_lut_10_size(prec_index);
> >>>    	const struct drm_color_lut *lut = blob->data;
> >>>    	int i, lut_size = drm_color_lut_size(blob);
> >>>    	enum pipe pipe = crtc->pipe;
> >>>    
> >>> -	for (i = 0; i < hw_lut_size; i++) {
> >>> -		/* We discard half the user entries in split gamma mode */
> >>> -		const struct drm_color_lut *entry =
> >>> -			&lut[i * (lut_size - 1) / (hw_lut_size - 1)];
> >>> -
> >>> +	for (i = 0; i < lut_size; i++) {
> >>>    		intel_de_write_fw(i915, PREC_PAL_INDEX(pipe), prec_index++);
> >>>    		intel_de_write_fw(i915, PREC_PAL_DATA(pipe),
> >>> -				  ilk_lut_10(entry));
> >>> +				  ilk_lut_10(&lut[i]));
> >>>    	}
> >>>    
> >>>    	/*
> >>> @@ -751,7 +770,6 @@ static void bdw_load_lut_10(struct intel_crtc *crtc,
> >>>    			    u32 prec_index)
> >>>    {
> >>>    	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> >>> -	int hw_lut_size = ivb_lut_10_size(prec_index);
> >>>    	const struct drm_color_lut *lut = blob->data;
> >>>    	int i, lut_size = drm_color_lut_size(blob);
> >>>    	enum pipe pipe = crtc->pipe;
> >>> @@ -759,14 +777,9 @@ static void bdw_load_lut_10(struct intel_crtc *crtc,
> >>>    	intel_de_write_fw(i915, PREC_PAL_INDEX(pipe),
> >>>    			  prec_index | PAL_PREC_AUTO_INCREMENT);
> >>>    
> >>> -	for (i = 0; i < hw_lut_size; i++) {
> >>> -		/* We discard half the user entries in split gamma mode */
> >>> -		const struct drm_color_lut *entry =
> >>> -			&lut[i * (lut_size - 1) / (hw_lut_size - 1)];
> >>> -
> >>> +	for (i = 0; i < lut_size; i++)
> >>>    		intel_de_write_fw(i915, PREC_PAL_DATA(pipe),
> >>> -				  ilk_lut_10(entry));
> >>> -	}
> >>> +				  ilk_lut_10(&lut[i]));
> >>>    
> >>>    	/*
> >>>    	 * Reset the index, otherwise it prevents the legacy palette to be
> >>> @@ -1343,7 +1356,7 @@ void intel_color_assert_luts(const struct intel_crtc_state *crtc_state)
> >>>    			    crtc_state->pre_csc_lut != i915->display.color.glk_linear_degamma_lut);
> >>>    		drm_WARN_ON(&i915->drm,
> >>>    			    crtc_state->post_csc_lut != crtc_state->hw.gamma_lut);
> >>> -	} else {
> >>> +	} else if (crtc_state->gamma_mode != GAMMA_MODE_MODE_SPLIT) {
> >>>    		drm_WARN_ON(&i915->drm,
> >>>    			    crtc_state->pre_csc_lut != crtc_state->hw.degamma_lut &&
> >>>    			    crtc_state->pre_csc_lut != crtc_state->hw.gamma_lut);
> >>> @@ -1564,6 +1577,38 @@ static u32 ivb_csc_mode(const struct intel_crtc_state *crtc_state)
> >>>    	return CSC_POSITION_BEFORE_GAMMA;
> >>>    }
> >>>    
> >>> +static int ivb_assign_luts(struct intel_crtc_state *crtc_state)
> >>> +{
> >>> +	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> >>> +	struct drm_property_blob *degamma_lut, *gamma_lut;
> >>> +
> >>> +	if (crtc_state->gamma_mode != GAMMA_MODE_MODE_SPLIT) {
> >>> +		ilk_assign_luts(crtc_state);
> >>> +		return 0;
> >>> +	}
> >>> +
> >>> +	drm_WARN_ON(&i915->drm, drm_color_lut_size(crtc_state->hw.degamma_lut) != 1024);
> >>> +	drm_WARN_ON(&i915->drm, drm_color_lut_size(crtc_state->hw.gamma_lut) != 1024);
> >> Does it make sense to use some macro for LUT size for split gamma case
> >> and regular case?
> >>
> >> Same thing perhaps can be used in ivb_lut_10_size?
> > I don't think macros would be really helpful. I guess I
> > could have used ivb_lut_10_size() for the create_resized_lut()
> > calls below. And these WARNs I guess could have just used
> > device info stuff instead.
> 
> Using ivb_lut_10_size() should be good enough, I think.
> 
> In any case, this is a just a minor suggestion. Patch looks good to me.

I've left it as is for now. We can certainly improve this
when we return to topic of the color uapi redesign.

> 
> With the small typo fixed in commit message:

Doh. Accidentally pulled the trigger before fixing the typo.
Oh well.

> 
> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Thanks for the reviews. Entire series merged now.

-- 
Ville Syrjälä
Intel