From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36696C433FE for ; Wed, 26 Oct 2022 17:54:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233703AbiJZRyq (ORCPT ); Wed, 26 Oct 2022 13:54:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59280 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233538AbiJZRyo (ORCPT ); Wed, 26 Oct 2022 13:54:44 -0400 Received: from mail-ot1-f51.google.com (mail-ot1-f51.google.com [209.85.210.51]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 937E16399; Wed, 26 Oct 2022 10:54:40 -0700 (PDT) Received: by mail-ot1-f51.google.com with SMTP id 16-20020a9d0490000000b0066938311495so2087314otm.4; Wed, 26 Oct 2022 10:54:40 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=zmbqUT3CmVbU0HzMpVAJyOgaDhVx3i4wGwXhoedlXNs=; b=xRBLKsdXdOUu5CKFUhSceEQcNAZIrgHWHRzFWOqLTtyGZglh1RiKq7dv8tS80LmO8s cf50hFlvo0L/y8qKPJBAUMH8mW9rFuMdwSji4SH1TcZyRQPPeR9+ViV0Em4EABW7ISbZ 6SOT4GGTHTMPiTkP1AwIEnH76fTCeYsGYRGQd+06/prlAAD2BIrvZhPn/4w9nnFCG0gb ndS5B5pAMKEL/C3y/Cyczf6h+xBa5TNd517f19+9CufH8YlVig2JArfRzinwNAwp7Aoa WoYUblYLSkCN5Du3h33x5PFsKUuMZnAop9A5+buzTKD0YhX9413QR8RSzeKrBXZQnbI6 Crcg== X-Gm-Message-State: ACrzQf34tJDUQ1Xw/Y+iqtCck4OMYEXlE7qNlT4ysO25aRXoKt3XiL4u jckV6RygiPOa+mU0001HZQ== X-Google-Smtp-Source: AMsMyM7u/5xsmyjQ88MnSABwibsj9ORVBkFwkQ3aUNkf/hBMroiSAacuWdQE9wICk8HxIgRsWTUPqg== X-Received: by 2002:a05:6830:d02:b0:661:9466:dfc3 with SMTP id bu2-20020a0568300d0200b006619466dfc3mr22434647otb.333.1666806880150; Wed, 26 Oct 2022 10:54:40 -0700 (PDT) Received: from robh_at_kernel.org (66-90-144-107.dyn.grandenetworks.net. [66.90.144.107]) by smtp.gmail.com with ESMTPSA id n44-20020a056870972c00b0011f22e74d5fsm3405812oaq.20.2022.10.26.10.54.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Oct 2022 10:54:39 -0700 (PDT) Received: (nullmailer pid 820018 invoked by uid 1000); Wed, 26 Oct 2022 17:54:41 -0000 Date: Wed, 26 Oct 2022 12:54:41 -0500 From: Rob Herring To: Bjorn Andersson Cc: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Kuogee Hsieh , Sankeerth Billakanti , Johan Hovold , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 01/12] dt-bindings: display/msm: Add binding for SC8280XP MDSS Message-ID: <20221026175441.GA812056-robh@kernel.org> References: <20221026032624.30871-1-quic_bjorande@quicinc.com> <20221026032624.30871-2-quic_bjorande@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20221026032624.30871-2-quic_bjorande@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Tue, Oct 25, 2022 at 08:26:13PM -0700, Bjorn Andersson wrote: > From: Bjorn Andersson > > Add binding for the display subsystem and display processing unit in the > Qualcomm SC8280XP platform. > > Signed-off-by: Bjorn Andersson > Signed-off-by: Bjorn Andersson > --- > > Changes since v2: > - Cleaned up description and interconnect definitions > - Added opp-table > > .../bindings/display/msm/dpu-sc8280xp.yaml | 287 ++++++++++++++++++ > 1 file changed, 287 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/msm/dpu-sc8280xp.yaml Doesn't this need to be reworked to match Dmitry's restructuring? > > diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sc8280xp.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sc8280xp.yaml > new file mode 100644 > index 000000000000..24e7a1562fe7 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/msm/dpu-sc8280xp.yaml > @@ -0,0 +1,287 @@ > +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/msm/dpu-sc8280xp.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm Display Processing Unit for SC8280XP > + > +maintainers: > + - Bjorn Andersson > + > +description: > + Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates > + sub-blocks like DPU display controller, DSI and DP interfaces etc. > + > +properties: > + compatible: > + const: qcom,sc8280xp-mdss > + > + reg: > + maxItems: 1 > + > + reg-names: > + const: mdss > + > + power-domains: > + maxItems: 1 > + > + clocks: > + items: > + - description: Display AHB clock from gcc > + - description: Display AHB clock from dispcc > + - description: Display core clock > + > + clock-names: > + items: > + - const: iface > + - const: ahb > + - const: core > + > + interrupts: > + maxItems: 1 > + > + interrupt-controller: true > + > + "#address-cells": true > + > + "#size-cells": true enum: [ 1, 2 ] (Nothing else sets that) Rob From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 83B8DC38A2D for ; Wed, 26 Oct 2022 17:54:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C58E110E66B; Wed, 26 Oct 2022 17:54:44 +0000 (UTC) Received: from mail-ot1-f41.google.com (mail-ot1-f41.google.com [209.85.210.41]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1B17C10E66D; Wed, 26 Oct 2022 17:54:41 +0000 (UTC) Received: by mail-ot1-f41.google.com with SMTP id m5-20020a9d73c5000000b0066738ce4f12so3266096otk.12; Wed, 26 Oct 2022 10:54:41 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=zmbqUT3CmVbU0HzMpVAJyOgaDhVx3i4wGwXhoedlXNs=; b=gX5EYFmEKPAY9RYM3az+TEekQif5KQItcwE1QS7SsEQjozCKqEm38Y26O0wp4iK0ve k4ojfOViD0mf4NoRPv23vsy6zBQEp11Wesx9Xzgan4QlwfTSUwOIgad/RAxM7PtXzTDn Lj+3jvn3CrDPHoAtStptcGc74d4v8IKinXqmikUrrJzwSI5Q31tnSKj0UdsL6LkLKr// i851YvtHZojBaNQ6v6xkbmNi2lmU6SX5hCN8sgTomWyAuN3KGl19ZYfVCYMZhMYmNqa3 BlCfwd+3Qsir1q58VG+srGgQpg4HQbqg7PYuES0PISroqQJOet8bF1jjVNDrWS6x1nxE xrqQ== X-Gm-Message-State: ACrzQf03DrDCNFEfsNkNa3h2yTOWmlFVEA5uPmS3G5omuZrRxchR/QWJ corMO4rk5JDCRHid8UtmqQ== X-Google-Smtp-Source: AMsMyM7u/5xsmyjQ88MnSABwibsj9ORVBkFwkQ3aUNkf/hBMroiSAacuWdQE9wICk8HxIgRsWTUPqg== X-Received: by 2002:a05:6830:d02:b0:661:9466:dfc3 with SMTP id bu2-20020a0568300d0200b006619466dfc3mr22434647otb.333.1666806880150; Wed, 26 Oct 2022 10:54:40 -0700 (PDT) Received: from robh_at_kernel.org (66-90-144-107.dyn.grandenetworks.net. [66.90.144.107]) by smtp.gmail.com with ESMTPSA id n44-20020a056870972c00b0011f22e74d5fsm3405812oaq.20.2022.10.26.10.54.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Oct 2022 10:54:39 -0700 (PDT) Received: (nullmailer pid 820018 invoked by uid 1000); Wed, 26 Oct 2022 17:54:41 -0000 Date: Wed, 26 Oct 2022 12:54:41 -0500 From: Rob Herring To: Bjorn Andersson Subject: Re: [PATCH v3 01/12] dt-bindings: display/msm: Add binding for SC8280XP MDSS Message-ID: <20221026175441.GA812056-robh@kernel.org> References: <20221026032624.30871-1-quic_bjorande@quicinc.com> <20221026032624.30871-2-quic_bjorande@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20221026032624.30871-2-quic_bjorande@quicinc.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: freedreno@lists.freedesktop.org, Sankeerth Billakanti , Krzysztof Kozlowski , devicetree@vger.kernel.org, Sean Paul , Bjorn Andersson , Konrad Dybcio , Abhinav Kumar , dri-devel@lists.freedesktop.org, Kuogee Hsieh , linux-arm-msm@vger.kernel.org, Dmitry Baryshkov , Johan Hovold , linux-kernel@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Tue, Oct 25, 2022 at 08:26:13PM -0700, Bjorn Andersson wrote: > From: Bjorn Andersson > > Add binding for the display subsystem and display processing unit in the > Qualcomm SC8280XP platform. > > Signed-off-by: Bjorn Andersson > Signed-off-by: Bjorn Andersson > --- > > Changes since v2: > - Cleaned up description and interconnect definitions > - Added opp-table > > .../bindings/display/msm/dpu-sc8280xp.yaml | 287 ++++++++++++++++++ > 1 file changed, 287 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/msm/dpu-sc8280xp.yaml Doesn't this need to be reworked to match Dmitry's restructuring? > > diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sc8280xp.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sc8280xp.yaml > new file mode 100644 > index 000000000000..24e7a1562fe7 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/msm/dpu-sc8280xp.yaml > @@ -0,0 +1,287 @@ > +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/msm/dpu-sc8280xp.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm Display Processing Unit for SC8280XP > + > +maintainers: > + - Bjorn Andersson > + > +description: > + Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates > + sub-blocks like DPU display controller, DSI and DP interfaces etc. > + > +properties: > + compatible: > + const: qcom,sc8280xp-mdss > + > + reg: > + maxItems: 1 > + > + reg-names: > + const: mdss > + > + power-domains: > + maxItems: 1 > + > + clocks: > + items: > + - description: Display AHB clock from gcc > + - description: Display AHB clock from dispcc > + - description: Display core clock > + > + clock-names: > + items: > + - const: iface > + - const: ahb > + - const: core > + > + interrupts: > + maxItems: 1 > + > + interrupt-controller: true > + > + "#address-cells": true > + > + "#size-cells": true enum: [ 1, 2 ] (Nothing else sets that) Rob