* [PATCH v2 0/7] arm64: sunxi: h616: Add USB support
@ 2022-10-31 11:13 ` Andre Przywara
0 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-10-31 11:13 UTC (permalink / raw)
To: Jernej Skrabec, Samuel Holland, Chen-Yu Tsai,
Kishon Vijay Abraham I, Vinod Koul
Cc: Rob Herring, Krzysztof Kozlowski, Greg Kroah-Hartman, linux-phy,
linux-usb, devicetree, linux-arm-kernel, linux-sunxi,
Karl Kurbjun, Icenowy Zheng
This is a fixed and rebased update of the previous version, with only
the DT binding and one DT seeing changes, triggered by Krzysztof's
comments. For a changelog see below.
Thanks to Karl for testing this on the OrangePi Zero 2!
------------------------
The USB IP used in the Allwinner H616 SoC is very similar to the one
used in the H3 chip: it contains four USB 2.0 host controllers and four
PHYs, where the first PHY is shared with a separate USB-OTG controller.
But out of the four ports, only port 2 works out of the box, the other
ports require some resources and registers of port 2 to be enabled as
well.
Implement the required workaround in the Allwinner USB PHY driver, and
key this off the respective compatible string. This core code is
contained in patch 3/7. The first two patches add the respective DT
binding documentation, whereas patch 4/7 encodes all the configuration
options for the H616 USB PHY into the driver.
The last three patches add the respective devicetree nodes, to the H616
.dtsi, but also to the DTs of the two supported boards.
This allows USB to be used on any H616 based machine. This was tested on
the X96 Mate box.
The patches in this series were originally contained in the initial H616
support series, but where dropped there to speed up mainlining of the
basic support.
It is now based on v6.1-rc3 and is also available here:
https://github.com/apritzel/linux/commits/h616-usb-v2
Please have a look and test on your hardware, especically on all ports
exposed on header pins of the OrangePi Zero2 board.
Cheers,
Andre
Changelog v1 .. v2:
- Add Krzysztof's ACK
- wrap If: clause in allOf: (patch 2/7)
- limit old (H3) PHYs to 4 clocks (else clause, patch 2/7)
- change subsystem to phy: in subject (patch 2/7)
- use "regulator-" prefix for DT node name (patch 6/7)
- drop unneeded status property in regulator node (patch 6/7)
Andre Przywara (7):
dt-bindings: usb: Add H616 compatible string
dt-bindings: phy: Add special clock for Allwinner H616 PHY
phy: sun4i-usb: Introduce port2 SIDDQ quirk
phy: sun4i-usb: Add support for the H616 USB PHY
arm64: dts: allwinner: h616: Add USB nodes
arm64: dts: allwinner: h616: OrangePi Zero 2: Add USB nodes
arm64: dts: allwinner: h616: X96 Mate: Add USB nodes
.../phy/allwinner,sun8i-h3-usb-phy.yaml | 26 +++
.../devicetree/bindings/usb/generic-ehci.yaml | 1 +
.../devicetree/bindings/usb/generic-ohci.yaml | 1 +
.../allwinner/sun50i-h616-orangepi-zero2.dts | 41 +++++
.../dts/allwinner/sun50i-h616-x96-mate.dts | 25 +++
.../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 160 ++++++++++++++++++
drivers/phy/allwinner/phy-sun4i-usb.c | 71 ++++++++
7 files changed, 325 insertions(+)
--
2.25.1
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH v2 0/7] arm64: sunxi: h616: Add USB support
@ 2022-10-31 11:13 ` Andre Przywara
0 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-10-31 11:13 UTC (permalink / raw)
To: Jernej Skrabec, Samuel Holland, Chen-Yu Tsai,
Kishon Vijay Abraham I, Vinod Koul
Cc: Rob Herring, Krzysztof Kozlowski, Greg Kroah-Hartman, linux-phy,
linux-usb, devicetree, linux-arm-kernel, linux-sunxi,
Karl Kurbjun, Icenowy Zheng
This is a fixed and rebased update of the previous version, with only
the DT binding and one DT seeing changes, triggered by Krzysztof's
comments. For a changelog see below.
Thanks to Karl for testing this on the OrangePi Zero 2!
------------------------
The USB IP used in the Allwinner H616 SoC is very similar to the one
used in the H3 chip: it contains four USB 2.0 host controllers and four
PHYs, where the first PHY is shared with a separate USB-OTG controller.
But out of the four ports, only port 2 works out of the box, the other
ports require some resources and registers of port 2 to be enabled as
well.
Implement the required workaround in the Allwinner USB PHY driver, and
key this off the respective compatible string. This core code is
contained in patch 3/7. The first two patches add the respective DT
binding documentation, whereas patch 4/7 encodes all the configuration
options for the H616 USB PHY into the driver.
The last three patches add the respective devicetree nodes, to the H616
.dtsi, but also to the DTs of the two supported boards.
This allows USB to be used on any H616 based machine. This was tested on
the X96 Mate box.
The patches in this series were originally contained in the initial H616
support series, but where dropped there to speed up mainlining of the
basic support.
It is now based on v6.1-rc3 and is also available here:
https://github.com/apritzel/linux/commits/h616-usb-v2
Please have a look and test on your hardware, especically on all ports
exposed on header pins of the OrangePi Zero2 board.
Cheers,
Andre
Changelog v1 .. v2:
- Add Krzysztof's ACK
- wrap If: clause in allOf: (patch 2/7)
- limit old (H3) PHYs to 4 clocks (else clause, patch 2/7)
- change subsystem to phy: in subject (patch 2/7)
- use "regulator-" prefix for DT node name (patch 6/7)
- drop unneeded status property in regulator node (patch 6/7)
Andre Przywara (7):
dt-bindings: usb: Add H616 compatible string
dt-bindings: phy: Add special clock for Allwinner H616 PHY
phy: sun4i-usb: Introduce port2 SIDDQ quirk
phy: sun4i-usb: Add support for the H616 USB PHY
arm64: dts: allwinner: h616: Add USB nodes
arm64: dts: allwinner: h616: OrangePi Zero 2: Add USB nodes
arm64: dts: allwinner: h616: X96 Mate: Add USB nodes
.../phy/allwinner,sun8i-h3-usb-phy.yaml | 26 +++
.../devicetree/bindings/usb/generic-ehci.yaml | 1 +
.../devicetree/bindings/usb/generic-ohci.yaml | 1 +
.../allwinner/sun50i-h616-orangepi-zero2.dts | 41 +++++
.../dts/allwinner/sun50i-h616-x96-mate.dts | 25 +++
.../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 160 ++++++++++++++++++
drivers/phy/allwinner/phy-sun4i-usb.c | 71 ++++++++
7 files changed, 325 insertions(+)
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH v2 0/7] arm64: sunxi: h616: Add USB support
@ 2022-10-31 11:13 ` Andre Przywara
0 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-10-31 11:13 UTC (permalink / raw)
To: Jernej Skrabec, Samuel Holland, Chen-Yu Tsai,
Kishon Vijay Abraham I, Vinod Koul
Cc: Rob Herring, Krzysztof Kozlowski, Greg Kroah-Hartman, linux-phy,
linux-usb, devicetree, linux-arm-kernel, linux-sunxi,
Karl Kurbjun, Icenowy Zheng
This is a fixed and rebased update of the previous version, with only
the DT binding and one DT seeing changes, triggered by Krzysztof's
comments. For a changelog see below.
Thanks to Karl for testing this on the OrangePi Zero 2!
------------------------
The USB IP used in the Allwinner H616 SoC is very similar to the one
used in the H3 chip: it contains four USB 2.0 host controllers and four
PHYs, where the first PHY is shared with a separate USB-OTG controller.
But out of the four ports, only port 2 works out of the box, the other
ports require some resources and registers of port 2 to be enabled as
well.
Implement the required workaround in the Allwinner USB PHY driver, and
key this off the respective compatible string. This core code is
contained in patch 3/7. The first two patches add the respective DT
binding documentation, whereas patch 4/7 encodes all the configuration
options for the H616 USB PHY into the driver.
The last three patches add the respective devicetree nodes, to the H616
.dtsi, but also to the DTs of the two supported boards.
This allows USB to be used on any H616 based machine. This was tested on
the X96 Mate box.
The patches in this series were originally contained in the initial H616
support series, but where dropped there to speed up mainlining of the
basic support.
It is now based on v6.1-rc3 and is also available here:
https://github.com/apritzel/linux/commits/h616-usb-v2
Please have a look and test on your hardware, especically on all ports
exposed on header pins of the OrangePi Zero2 board.
Cheers,
Andre
Changelog v1 .. v2:
- Add Krzysztof's ACK
- wrap If: clause in allOf: (patch 2/7)
- limit old (H3) PHYs to 4 clocks (else clause, patch 2/7)
- change subsystem to phy: in subject (patch 2/7)
- use "regulator-" prefix for DT node name (patch 6/7)
- drop unneeded status property in regulator node (patch 6/7)
Andre Przywara (7):
dt-bindings: usb: Add H616 compatible string
dt-bindings: phy: Add special clock for Allwinner H616 PHY
phy: sun4i-usb: Introduce port2 SIDDQ quirk
phy: sun4i-usb: Add support for the H616 USB PHY
arm64: dts: allwinner: h616: Add USB nodes
arm64: dts: allwinner: h616: OrangePi Zero 2: Add USB nodes
arm64: dts: allwinner: h616: X96 Mate: Add USB nodes
.../phy/allwinner,sun8i-h3-usb-phy.yaml | 26 +++
.../devicetree/bindings/usb/generic-ehci.yaml | 1 +
.../devicetree/bindings/usb/generic-ohci.yaml | 1 +
.../allwinner/sun50i-h616-orangepi-zero2.dts | 41 +++++
.../dts/allwinner/sun50i-h616-x96-mate.dts | 25 +++
.../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 160 ++++++++++++++++++
drivers/phy/allwinner/phy-sun4i-usb.c | 71 ++++++++
7 files changed, 325 insertions(+)
--
2.25.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH v2 1/7] dt-bindings: usb: Add H616 compatible string
2022-10-31 11:13 ` Andre Przywara
(?)
@ 2022-10-31 11:13 ` Andre Przywara
-1 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-10-31 11:13 UTC (permalink / raw)
To: Jernej Skrabec, Samuel Holland, Chen-Yu Tsai,
Kishon Vijay Abraham I, Vinod Koul
Cc: Rob Herring, Krzysztof Kozlowski, Greg Kroah-Hartman, linux-phy,
linux-usb, devicetree, linux-arm-kernel, linux-sunxi,
Karl Kurbjun, Icenowy Zheng
The Allwinner H616 contains four fully OHCI/EHCI compatible USB host
controllers, so just add their compatible strings to the list of
generic OHCI/EHCI controllers.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Documentation/devicetree/bindings/usb/generic-ehci.yaml | 1 +
Documentation/devicetree/bindings/usb/generic-ohci.yaml | 1 +
2 files changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/generic-ehci.yaml b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
index c5f629c5bc617..994818cb60446 100644
--- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml
+++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
@@ -30,6 +30,7 @@ properties:
- allwinner,sun4i-a10-ehci
- allwinner,sun50i-a64-ehci
- allwinner,sun50i-h6-ehci
+ - allwinner,sun50i-h616-ehci
- allwinner,sun5i-a13-ehci
- allwinner,sun6i-a31-ehci
- allwinner,sun7i-a20-ehci
diff --git a/Documentation/devicetree/bindings/usb/generic-ohci.yaml b/Documentation/devicetree/bindings/usb/generic-ohci.yaml
index f838f78d6164a..4fcbd0add49d1 100644
--- a/Documentation/devicetree/bindings/usb/generic-ohci.yaml
+++ b/Documentation/devicetree/bindings/usb/generic-ohci.yaml
@@ -20,6 +20,7 @@ properties:
- allwinner,sun4i-a10-ohci
- allwinner,sun50i-a64-ohci
- allwinner,sun50i-h6-ohci
+ - allwinner,sun50i-h616-ohci
- allwinner,sun5i-a13-ohci
- allwinner,sun6i-a31-ohci
- allwinner,sun7i-a20-ohci
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v2 1/7] dt-bindings: usb: Add H616 compatible string
@ 2022-10-31 11:13 ` Andre Przywara
0 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-10-31 11:13 UTC (permalink / raw)
To: Jernej Skrabec, Samuel Holland, Chen-Yu Tsai,
Kishon Vijay Abraham I, Vinod Koul
Cc: Rob Herring, Krzysztof Kozlowski, Greg Kroah-Hartman, linux-phy,
linux-usb, devicetree, linux-arm-kernel, linux-sunxi,
Karl Kurbjun, Icenowy Zheng
The Allwinner H616 contains four fully OHCI/EHCI compatible USB host
controllers, so just add their compatible strings to the list of
generic OHCI/EHCI controllers.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Documentation/devicetree/bindings/usb/generic-ehci.yaml | 1 +
Documentation/devicetree/bindings/usb/generic-ohci.yaml | 1 +
2 files changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/generic-ehci.yaml b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
index c5f629c5bc617..994818cb60446 100644
--- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml
+++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
@@ -30,6 +30,7 @@ properties:
- allwinner,sun4i-a10-ehci
- allwinner,sun50i-a64-ehci
- allwinner,sun50i-h6-ehci
+ - allwinner,sun50i-h616-ehci
- allwinner,sun5i-a13-ehci
- allwinner,sun6i-a31-ehci
- allwinner,sun7i-a20-ehci
diff --git a/Documentation/devicetree/bindings/usb/generic-ohci.yaml b/Documentation/devicetree/bindings/usb/generic-ohci.yaml
index f838f78d6164a..4fcbd0add49d1 100644
--- a/Documentation/devicetree/bindings/usb/generic-ohci.yaml
+++ b/Documentation/devicetree/bindings/usb/generic-ohci.yaml
@@ -20,6 +20,7 @@ properties:
- allwinner,sun4i-a10-ohci
- allwinner,sun50i-a64-ohci
- allwinner,sun50i-h6-ohci
+ - allwinner,sun50i-h616-ohci
- allwinner,sun5i-a13-ohci
- allwinner,sun6i-a31-ohci
- allwinner,sun7i-a20-ohci
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v2 1/7] dt-bindings: usb: Add H616 compatible string
@ 2022-10-31 11:13 ` Andre Przywara
0 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-10-31 11:13 UTC (permalink / raw)
To: Jernej Skrabec, Samuel Holland, Chen-Yu Tsai,
Kishon Vijay Abraham I, Vinod Koul
Cc: Rob Herring, Krzysztof Kozlowski, Greg Kroah-Hartman, linux-phy,
linux-usb, devicetree, linux-arm-kernel, linux-sunxi,
Karl Kurbjun, Icenowy Zheng
The Allwinner H616 contains four fully OHCI/EHCI compatible USB host
controllers, so just add their compatible strings to the list of
generic OHCI/EHCI controllers.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Documentation/devicetree/bindings/usb/generic-ehci.yaml | 1 +
Documentation/devicetree/bindings/usb/generic-ohci.yaml | 1 +
2 files changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/generic-ehci.yaml b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
index c5f629c5bc617..994818cb60446 100644
--- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml
+++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
@@ -30,6 +30,7 @@ properties:
- allwinner,sun4i-a10-ehci
- allwinner,sun50i-a64-ehci
- allwinner,sun50i-h6-ehci
+ - allwinner,sun50i-h616-ehci
- allwinner,sun5i-a13-ehci
- allwinner,sun6i-a31-ehci
- allwinner,sun7i-a20-ehci
diff --git a/Documentation/devicetree/bindings/usb/generic-ohci.yaml b/Documentation/devicetree/bindings/usb/generic-ohci.yaml
index f838f78d6164a..4fcbd0add49d1 100644
--- a/Documentation/devicetree/bindings/usb/generic-ohci.yaml
+++ b/Documentation/devicetree/bindings/usb/generic-ohci.yaml
@@ -20,6 +20,7 @@ properties:
- allwinner,sun4i-a10-ohci
- allwinner,sun50i-a64-ohci
- allwinner,sun50i-h6-ohci
+ - allwinner,sun50i-h616-ohci
- allwinner,sun5i-a13-ohci
- allwinner,sun6i-a31-ohci
- allwinner,sun7i-a20-ohci
--
2.25.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v2 2/7] dt-bindings: phy: Add special clock for Allwinner H616 PHY
2022-10-31 11:13 ` Andre Przywara
(?)
@ 2022-10-31 11:13 ` Andre Przywara
-1 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-10-31 11:13 UTC (permalink / raw)
To: Jernej Skrabec, Samuel Holland, Chen-Yu Tsai,
Kishon Vijay Abraham I, Vinod Koul
Cc: Rob Herring, Krzysztof Kozlowski, Greg Kroah-Hartman, linux-phy,
linux-usb, devicetree, linux-arm-kernel, linux-sunxi,
Karl Kurbjun, Icenowy Zheng
The USB PHY IP in the Allwinner H616 SoC requires a quirk that involves
some resources from port 2's PHY and HCI IP. In particular the PMU clock
for port 2 must be surely ungated before accessing the REG_HCI_PHY_CTL
register of port 2. To allow each USB port to be controlled
independently of port 2, we need a handle to that particular PMU clock
in the *PHY* node, as the HCI and PHY part might be handled by separate
drivers.
Add that clock to the requirements of the H616 PHY binding, so that a
PHY driver can apply the quirk in isolation, without requiring help from
port 2's HCI driver.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
.../phy/allwinner,sun8i-h3-usb-phy.yaml | 26 +++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml
index 77539b4601c24..2df012d13655e 100644
--- a/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml
@@ -36,18 +36,22 @@ properties:
- const: pmu3
clocks:
+ minItems: 4
items:
- description: USB OTG PHY bus clock
- description: USB Host 0 PHY bus clock
- description: USB Host 1 PHY bus clock
- description: USB Host 2 PHY bus clock
+ - description: PMU clock for host port 2
clock-names:
+ minItems: 4
items:
- const: usb0_phy
- const: usb1_phy
- const: usb2_phy
- const: usb3_phy
+ - const: pmu2_clk
resets:
items:
@@ -96,6 +100,28 @@ required:
- resets
- reset-names
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - allwinner,sun50i-h616-usb-phy
+ then:
+ properties:
+ clocks:
+ minItems: 5
+
+ clock-names:
+ minItems: 5
+ else:
+ properties:
+ clocks:
+ maxItems: 4
+
+ clock-names:
+ maxItems: 4
+
additionalProperties: false
examples:
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v2 2/7] dt-bindings: phy: Add special clock for Allwinner H616 PHY
@ 2022-10-31 11:13 ` Andre Przywara
0 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-10-31 11:13 UTC (permalink / raw)
To: Jernej Skrabec, Samuel Holland, Chen-Yu Tsai,
Kishon Vijay Abraham I, Vinod Koul
Cc: Rob Herring, Krzysztof Kozlowski, Greg Kroah-Hartman, linux-phy,
linux-usb, devicetree, linux-arm-kernel, linux-sunxi,
Karl Kurbjun, Icenowy Zheng
The USB PHY IP in the Allwinner H616 SoC requires a quirk that involves
some resources from port 2's PHY and HCI IP. In particular the PMU clock
for port 2 must be surely ungated before accessing the REG_HCI_PHY_CTL
register of port 2. To allow each USB port to be controlled
independently of port 2, we need a handle to that particular PMU clock
in the *PHY* node, as the HCI and PHY part might be handled by separate
drivers.
Add that clock to the requirements of the H616 PHY binding, so that a
PHY driver can apply the quirk in isolation, without requiring help from
port 2's HCI driver.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
.../phy/allwinner,sun8i-h3-usb-phy.yaml | 26 +++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml
index 77539b4601c24..2df012d13655e 100644
--- a/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml
@@ -36,18 +36,22 @@ properties:
- const: pmu3
clocks:
+ minItems: 4
items:
- description: USB OTG PHY bus clock
- description: USB Host 0 PHY bus clock
- description: USB Host 1 PHY bus clock
- description: USB Host 2 PHY bus clock
+ - description: PMU clock for host port 2
clock-names:
+ minItems: 4
items:
- const: usb0_phy
- const: usb1_phy
- const: usb2_phy
- const: usb3_phy
+ - const: pmu2_clk
resets:
items:
@@ -96,6 +100,28 @@ required:
- resets
- reset-names
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - allwinner,sun50i-h616-usb-phy
+ then:
+ properties:
+ clocks:
+ minItems: 5
+
+ clock-names:
+ minItems: 5
+ else:
+ properties:
+ clocks:
+ maxItems: 4
+
+ clock-names:
+ maxItems: 4
+
additionalProperties: false
examples:
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v2 2/7] dt-bindings: phy: Add special clock for Allwinner H616 PHY
@ 2022-10-31 11:13 ` Andre Przywara
0 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-10-31 11:13 UTC (permalink / raw)
To: Jernej Skrabec, Samuel Holland, Chen-Yu Tsai,
Kishon Vijay Abraham I, Vinod Koul
Cc: Rob Herring, Krzysztof Kozlowski, Greg Kroah-Hartman, linux-phy,
linux-usb, devicetree, linux-arm-kernel, linux-sunxi,
Karl Kurbjun, Icenowy Zheng
The USB PHY IP in the Allwinner H616 SoC requires a quirk that involves
some resources from port 2's PHY and HCI IP. In particular the PMU clock
for port 2 must be surely ungated before accessing the REG_HCI_PHY_CTL
register of port 2. To allow each USB port to be controlled
independently of port 2, we need a handle to that particular PMU clock
in the *PHY* node, as the HCI and PHY part might be handled by separate
drivers.
Add that clock to the requirements of the H616 PHY binding, so that a
PHY driver can apply the quirk in isolation, without requiring help from
port 2's HCI driver.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
.../phy/allwinner,sun8i-h3-usb-phy.yaml | 26 +++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml
index 77539b4601c24..2df012d13655e 100644
--- a/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml
@@ -36,18 +36,22 @@ properties:
- const: pmu3
clocks:
+ minItems: 4
items:
- description: USB OTG PHY bus clock
- description: USB Host 0 PHY bus clock
- description: USB Host 1 PHY bus clock
- description: USB Host 2 PHY bus clock
+ - description: PMU clock for host port 2
clock-names:
+ minItems: 4
items:
- const: usb0_phy
- const: usb1_phy
- const: usb2_phy
- const: usb3_phy
+ - const: pmu2_clk
resets:
items:
@@ -96,6 +100,28 @@ required:
- resets
- reset-names
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - allwinner,sun50i-h616-usb-phy
+ then:
+ properties:
+ clocks:
+ minItems: 5
+
+ clock-names:
+ minItems: 5
+ else:
+ properties:
+ clocks:
+ maxItems: 4
+
+ clock-names:
+ maxItems: 4
+
additionalProperties: false
examples:
--
2.25.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v2 3/7] phy: sun4i-usb: Introduce port2 SIDDQ quirk
2022-10-31 11:13 ` Andre Przywara
(?)
@ 2022-10-31 11:13 ` Andre Przywara
-1 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-10-31 11:13 UTC (permalink / raw)
To: Jernej Skrabec, Samuel Holland, Chen-Yu Tsai,
Kishon Vijay Abraham I, Vinod Koul
Cc: Rob Herring, Krzysztof Kozlowski, Greg Kroah-Hartman, linux-phy,
linux-usb, devicetree, linux-arm-kernel, linux-sunxi,
Karl Kurbjun, Icenowy Zheng
At least the Allwinner H616 SoC requires a weird quirk to make most
USB PHYs work: Only port2 works out of the box, but all other ports
need some help from this port2 to work correctly: The CLK_BUS_PHY2 and
RST_USB_PHY2 clock and reset need to be enabled, and the SIDDQ bit in
the PMU PHY control register needs to be cleared. For this register to
be accessible, CLK_BUS_ECHI2 needs to be ungated. Don't ask ....
Instead of disguising this as some generic feature, treat it more like
a quirk (what it really is):
If the quirk bit is set, and we initialise a PHY other than PHY2, ungate
this one special clock, and clear the SIDDQ bit. We also pick the clock
and reset from PHY2 and enable them as well.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
drivers/phy/allwinner/phy-sun4i-usb.c | 59 +++++++++++++++++++++++++++
1 file changed, 59 insertions(+)
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
index 3a3831f6059a3..e39f5ad62cc19 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -120,6 +120,7 @@ struct sun4i_usb_phy_cfg {
u8 phyctl_offset;
bool dedicated_clocks;
bool phy0_dual_route;
+ bool needs_phy2_siddq;
int missing_phys;
};
@@ -289,6 +290,50 @@ static int sun4i_usb_phy_init(struct phy *_phy)
return ret;
}
+ /* Some PHYs on some SoCs need the help of PHY2 to work. */
+ if (data->cfg->needs_phy2_siddq && phy->index != 2) {
+ struct sun4i_usb_phy *phy2 = &data->phys[2];
+
+ ret = clk_prepare_enable(phy2->clk);
+ if (ret) {
+ reset_control_assert(phy->reset);
+ clk_disable_unprepare(phy->clk2);
+ clk_disable_unprepare(phy->clk);
+ return ret;
+ }
+
+ ret = reset_control_deassert(phy2->reset);
+ if (ret) {
+ clk_disable_unprepare(phy2->clk);
+ reset_control_assert(phy->reset);
+ clk_disable_unprepare(phy->clk2);
+ clk_disable_unprepare(phy->clk);
+ return ret;
+ }
+
+ /*
+ * This extra clock is just needed to access the
+ * REG_HCI_PHY_CTL PMU register for PHY2.
+ */
+ ret = clk_prepare_enable(phy2->clk2);
+ if (ret) {
+ reset_control_assert(phy2->reset);
+ clk_disable_unprepare(phy2->clk);
+ reset_control_assert(phy->reset);
+ clk_disable_unprepare(phy->clk2);
+ clk_disable_unprepare(phy->clk);
+ return ret;
+ }
+
+ if (phy2->pmu && data->cfg->hci_phy_ctl_clear) {
+ val = readl(phy2->pmu + REG_HCI_PHY_CTL);
+ val &= ~data->cfg->hci_phy_ctl_clear;
+ writel(val, phy2->pmu + REG_HCI_PHY_CTL);
+ }
+
+ clk_disable_unprepare(phy->clk2);
+ }
+
if (phy->pmu && data->cfg->hci_phy_ctl_clear) {
val = readl(phy->pmu + REG_HCI_PHY_CTL);
val &= ~data->cfg->hci_phy_ctl_clear;
@@ -354,6 +399,13 @@ static int sun4i_usb_phy_exit(struct phy *_phy)
data->phy0_init = false;
}
+ if (data->cfg->needs_phy2_siddq && phy->index != 2) {
+ struct sun4i_usb_phy *phy2 = &data->phys[2];
+
+ clk_disable_unprepare(phy2->clk);
+ reset_control_assert(phy2->reset);
+ }
+
sun4i_usb_phy_passby(phy, 0);
reset_control_assert(phy->reset);
clk_disable_unprepare(phy->clk2);
@@ -785,6 +837,13 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
dev_err(dev, "failed to get clock %s\n", name);
return PTR_ERR(phy->clk2);
}
+ } else {
+ snprintf(name, sizeof(name), "pmu%d_clk", i);
+ phy->clk2 = devm_clk_get_optional(dev, name);
+ if (IS_ERR(phy->clk2)) {
+ dev_err(dev, "failed to get clock %s\n", name);
+ return PTR_ERR(phy->clk2);
+ }
}
snprintf(name, sizeof(name), "usb%d_reset", i);
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v2 3/7] phy: sun4i-usb: Introduce port2 SIDDQ quirk
@ 2022-10-31 11:13 ` Andre Przywara
0 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-10-31 11:13 UTC (permalink / raw)
To: Jernej Skrabec, Samuel Holland, Chen-Yu Tsai,
Kishon Vijay Abraham I, Vinod Koul
Cc: Rob Herring, Krzysztof Kozlowski, Greg Kroah-Hartman, linux-phy,
linux-usb, devicetree, linux-arm-kernel, linux-sunxi,
Karl Kurbjun, Icenowy Zheng
At least the Allwinner H616 SoC requires a weird quirk to make most
USB PHYs work: Only port2 works out of the box, but all other ports
need some help from this port2 to work correctly: The CLK_BUS_PHY2 and
RST_USB_PHY2 clock and reset need to be enabled, and the SIDDQ bit in
the PMU PHY control register needs to be cleared. For this register to
be accessible, CLK_BUS_ECHI2 needs to be ungated. Don't ask ....
Instead of disguising this as some generic feature, treat it more like
a quirk (what it really is):
If the quirk bit is set, and we initialise a PHY other than PHY2, ungate
this one special clock, and clear the SIDDQ bit. We also pick the clock
and reset from PHY2 and enable them as well.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
drivers/phy/allwinner/phy-sun4i-usb.c | 59 +++++++++++++++++++++++++++
1 file changed, 59 insertions(+)
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
index 3a3831f6059a3..e39f5ad62cc19 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -120,6 +120,7 @@ struct sun4i_usb_phy_cfg {
u8 phyctl_offset;
bool dedicated_clocks;
bool phy0_dual_route;
+ bool needs_phy2_siddq;
int missing_phys;
};
@@ -289,6 +290,50 @@ static int sun4i_usb_phy_init(struct phy *_phy)
return ret;
}
+ /* Some PHYs on some SoCs need the help of PHY2 to work. */
+ if (data->cfg->needs_phy2_siddq && phy->index != 2) {
+ struct sun4i_usb_phy *phy2 = &data->phys[2];
+
+ ret = clk_prepare_enable(phy2->clk);
+ if (ret) {
+ reset_control_assert(phy->reset);
+ clk_disable_unprepare(phy->clk2);
+ clk_disable_unprepare(phy->clk);
+ return ret;
+ }
+
+ ret = reset_control_deassert(phy2->reset);
+ if (ret) {
+ clk_disable_unprepare(phy2->clk);
+ reset_control_assert(phy->reset);
+ clk_disable_unprepare(phy->clk2);
+ clk_disable_unprepare(phy->clk);
+ return ret;
+ }
+
+ /*
+ * This extra clock is just needed to access the
+ * REG_HCI_PHY_CTL PMU register for PHY2.
+ */
+ ret = clk_prepare_enable(phy2->clk2);
+ if (ret) {
+ reset_control_assert(phy2->reset);
+ clk_disable_unprepare(phy2->clk);
+ reset_control_assert(phy->reset);
+ clk_disable_unprepare(phy->clk2);
+ clk_disable_unprepare(phy->clk);
+ return ret;
+ }
+
+ if (phy2->pmu && data->cfg->hci_phy_ctl_clear) {
+ val = readl(phy2->pmu + REG_HCI_PHY_CTL);
+ val &= ~data->cfg->hci_phy_ctl_clear;
+ writel(val, phy2->pmu + REG_HCI_PHY_CTL);
+ }
+
+ clk_disable_unprepare(phy->clk2);
+ }
+
if (phy->pmu && data->cfg->hci_phy_ctl_clear) {
val = readl(phy->pmu + REG_HCI_PHY_CTL);
val &= ~data->cfg->hci_phy_ctl_clear;
@@ -354,6 +399,13 @@ static int sun4i_usb_phy_exit(struct phy *_phy)
data->phy0_init = false;
}
+ if (data->cfg->needs_phy2_siddq && phy->index != 2) {
+ struct sun4i_usb_phy *phy2 = &data->phys[2];
+
+ clk_disable_unprepare(phy2->clk);
+ reset_control_assert(phy2->reset);
+ }
+
sun4i_usb_phy_passby(phy, 0);
reset_control_assert(phy->reset);
clk_disable_unprepare(phy->clk2);
@@ -785,6 +837,13 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
dev_err(dev, "failed to get clock %s\n", name);
return PTR_ERR(phy->clk2);
}
+ } else {
+ snprintf(name, sizeof(name), "pmu%d_clk", i);
+ phy->clk2 = devm_clk_get_optional(dev, name);
+ if (IS_ERR(phy->clk2)) {
+ dev_err(dev, "failed to get clock %s\n", name);
+ return PTR_ERR(phy->clk2);
+ }
}
snprintf(name, sizeof(name), "usb%d_reset", i);
--
2.25.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v2 3/7] phy: sun4i-usb: Introduce port2 SIDDQ quirk
@ 2022-10-31 11:13 ` Andre Przywara
0 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-10-31 11:13 UTC (permalink / raw)
To: Jernej Skrabec, Samuel Holland, Chen-Yu Tsai,
Kishon Vijay Abraham I, Vinod Koul
Cc: Rob Herring, Krzysztof Kozlowski, Greg Kroah-Hartman, linux-phy,
linux-usb, devicetree, linux-arm-kernel, linux-sunxi,
Karl Kurbjun, Icenowy Zheng
At least the Allwinner H616 SoC requires a weird quirk to make most
USB PHYs work: Only port2 works out of the box, but all other ports
need some help from this port2 to work correctly: The CLK_BUS_PHY2 and
RST_USB_PHY2 clock and reset need to be enabled, and the SIDDQ bit in
the PMU PHY control register needs to be cleared. For this register to
be accessible, CLK_BUS_ECHI2 needs to be ungated. Don't ask ....
Instead of disguising this as some generic feature, treat it more like
a quirk (what it really is):
If the quirk bit is set, and we initialise a PHY other than PHY2, ungate
this one special clock, and clear the SIDDQ bit. We also pick the clock
and reset from PHY2 and enable them as well.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
drivers/phy/allwinner/phy-sun4i-usb.c | 59 +++++++++++++++++++++++++++
1 file changed, 59 insertions(+)
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
index 3a3831f6059a3..e39f5ad62cc19 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -120,6 +120,7 @@ struct sun4i_usb_phy_cfg {
u8 phyctl_offset;
bool dedicated_clocks;
bool phy0_dual_route;
+ bool needs_phy2_siddq;
int missing_phys;
};
@@ -289,6 +290,50 @@ static int sun4i_usb_phy_init(struct phy *_phy)
return ret;
}
+ /* Some PHYs on some SoCs need the help of PHY2 to work. */
+ if (data->cfg->needs_phy2_siddq && phy->index != 2) {
+ struct sun4i_usb_phy *phy2 = &data->phys[2];
+
+ ret = clk_prepare_enable(phy2->clk);
+ if (ret) {
+ reset_control_assert(phy->reset);
+ clk_disable_unprepare(phy->clk2);
+ clk_disable_unprepare(phy->clk);
+ return ret;
+ }
+
+ ret = reset_control_deassert(phy2->reset);
+ if (ret) {
+ clk_disable_unprepare(phy2->clk);
+ reset_control_assert(phy->reset);
+ clk_disable_unprepare(phy->clk2);
+ clk_disable_unprepare(phy->clk);
+ return ret;
+ }
+
+ /*
+ * This extra clock is just needed to access the
+ * REG_HCI_PHY_CTL PMU register for PHY2.
+ */
+ ret = clk_prepare_enable(phy2->clk2);
+ if (ret) {
+ reset_control_assert(phy2->reset);
+ clk_disable_unprepare(phy2->clk);
+ reset_control_assert(phy->reset);
+ clk_disable_unprepare(phy->clk2);
+ clk_disable_unprepare(phy->clk);
+ return ret;
+ }
+
+ if (phy2->pmu && data->cfg->hci_phy_ctl_clear) {
+ val = readl(phy2->pmu + REG_HCI_PHY_CTL);
+ val &= ~data->cfg->hci_phy_ctl_clear;
+ writel(val, phy2->pmu + REG_HCI_PHY_CTL);
+ }
+
+ clk_disable_unprepare(phy->clk2);
+ }
+
if (phy->pmu && data->cfg->hci_phy_ctl_clear) {
val = readl(phy->pmu + REG_HCI_PHY_CTL);
val &= ~data->cfg->hci_phy_ctl_clear;
@@ -354,6 +399,13 @@ static int sun4i_usb_phy_exit(struct phy *_phy)
data->phy0_init = false;
}
+ if (data->cfg->needs_phy2_siddq && phy->index != 2) {
+ struct sun4i_usb_phy *phy2 = &data->phys[2];
+
+ clk_disable_unprepare(phy2->clk);
+ reset_control_assert(phy2->reset);
+ }
+
sun4i_usb_phy_passby(phy, 0);
reset_control_assert(phy->reset);
clk_disable_unprepare(phy->clk2);
@@ -785,6 +837,13 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
dev_err(dev, "failed to get clock %s\n", name);
return PTR_ERR(phy->clk2);
}
+ } else {
+ snprintf(name, sizeof(name), "pmu%d_clk", i);
+ phy->clk2 = devm_clk_get_optional(dev, name);
+ if (IS_ERR(phy->clk2)) {
+ dev_err(dev, "failed to get clock %s\n", name);
+ return PTR_ERR(phy->clk2);
+ }
}
snprintf(name, sizeof(name), "usb%d_reset", i);
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v2 4/7] phy: sun4i-usb: Add support for the H616 USB PHY
2022-10-31 11:13 ` Andre Przywara
(?)
@ 2022-10-31 11:13 ` Andre Przywara
-1 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-10-31 11:13 UTC (permalink / raw)
To: Jernej Skrabec, Samuel Holland, Chen-Yu Tsai,
Kishon Vijay Abraham I, Vinod Koul
Cc: Rob Herring, Krzysztof Kozlowski, Greg Kroah-Hartman, linux-phy,
linux-usb, devicetree, linux-arm-kernel, linux-sunxi,
Karl Kurbjun, Icenowy Zheng
The USB PHY used in the Allwinner H616 SoC inherits some traits from its
various predecessors: it has four full PHYs like the H3, needs some
extra bits to be set like the H6, and puts SIDDQ on a different bit like
the A100. Plus it needs this weird PHY2 quirk.
Name all those properties in a new config struct and assign a new
compatible name to it.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
---
drivers/phy/allwinner/phy-sun4i-usb.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
index e39f5ad62cc19..5472db9e87ef8 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -1032,6 +1032,17 @@ static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = {
.missing_phys = BIT(1) | BIT(2),
};
+static const struct sun4i_usb_phy_cfg sun50i_h616_cfg = {
+ .num_phys = 4,
+ .type = sun50i_h6_phy,
+ .disc_thresh = 3,
+ .phyctl_offset = REG_PHYCTL_A33,
+ .dedicated_clocks = true,
+ .phy0_dual_route = true,
+ .hci_phy_ctl_clear = PHY_CTL_SIDDQ,
+ .needs_phy2_siddq = true,
+};
+
static const struct of_device_id sun4i_usb_phy_of_match[] = {
{ .compatible = "allwinner,sun4i-a10-usb-phy", .data = &sun4i_a10_cfg },
{ .compatible = "allwinner,sun5i-a13-usb-phy", .data = &sun5i_a13_cfg },
@@ -1047,6 +1058,7 @@ static const struct of_device_id sun4i_usb_phy_of_match[] = {
{ .compatible = "allwinner,sun50i-a64-usb-phy",
.data = &sun50i_a64_cfg},
{ .compatible = "allwinner,sun50i-h6-usb-phy", .data = &sun50i_h6_cfg },
+ { .compatible = "allwinner,sun50i-h616-usb-phy", .data = &sun50i_h616_cfg },
{ },
};
MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v2 4/7] phy: sun4i-usb: Add support for the H616 USB PHY
@ 2022-10-31 11:13 ` Andre Przywara
0 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-10-31 11:13 UTC (permalink / raw)
To: Jernej Skrabec, Samuel Holland, Chen-Yu Tsai,
Kishon Vijay Abraham I, Vinod Koul
Cc: Rob Herring, Krzysztof Kozlowski, Greg Kroah-Hartman, linux-phy,
linux-usb, devicetree, linux-arm-kernel, linux-sunxi,
Karl Kurbjun, Icenowy Zheng
The USB PHY used in the Allwinner H616 SoC inherits some traits from its
various predecessors: it has four full PHYs like the H3, needs some
extra bits to be set like the H6, and puts SIDDQ on a different bit like
the A100. Plus it needs this weird PHY2 quirk.
Name all those properties in a new config struct and assign a new
compatible name to it.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
---
drivers/phy/allwinner/phy-sun4i-usb.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
index e39f5ad62cc19..5472db9e87ef8 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -1032,6 +1032,17 @@ static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = {
.missing_phys = BIT(1) | BIT(2),
};
+static const struct sun4i_usb_phy_cfg sun50i_h616_cfg = {
+ .num_phys = 4,
+ .type = sun50i_h6_phy,
+ .disc_thresh = 3,
+ .phyctl_offset = REG_PHYCTL_A33,
+ .dedicated_clocks = true,
+ .phy0_dual_route = true,
+ .hci_phy_ctl_clear = PHY_CTL_SIDDQ,
+ .needs_phy2_siddq = true,
+};
+
static const struct of_device_id sun4i_usb_phy_of_match[] = {
{ .compatible = "allwinner,sun4i-a10-usb-phy", .data = &sun4i_a10_cfg },
{ .compatible = "allwinner,sun5i-a13-usb-phy", .data = &sun5i_a13_cfg },
@@ -1047,6 +1058,7 @@ static const struct of_device_id sun4i_usb_phy_of_match[] = {
{ .compatible = "allwinner,sun50i-a64-usb-phy",
.data = &sun50i_a64_cfg},
{ .compatible = "allwinner,sun50i-h6-usb-phy", .data = &sun50i_h6_cfg },
+ { .compatible = "allwinner,sun50i-h616-usb-phy", .data = &sun50i_h616_cfg },
{ },
};
MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v2 4/7] phy: sun4i-usb: Add support for the H616 USB PHY
@ 2022-10-31 11:13 ` Andre Przywara
0 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-10-31 11:13 UTC (permalink / raw)
To: Jernej Skrabec, Samuel Holland, Chen-Yu Tsai,
Kishon Vijay Abraham I, Vinod Koul
Cc: Rob Herring, Krzysztof Kozlowski, Greg Kroah-Hartman, linux-phy,
linux-usb, devicetree, linux-arm-kernel, linux-sunxi,
Karl Kurbjun, Icenowy Zheng
The USB PHY used in the Allwinner H616 SoC inherits some traits from its
various predecessors: it has four full PHYs like the H3, needs some
extra bits to be set like the H6, and puts SIDDQ on a different bit like
the A100. Plus it needs this weird PHY2 quirk.
Name all those properties in a new config struct and assign a new
compatible name to it.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
---
drivers/phy/allwinner/phy-sun4i-usb.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
index e39f5ad62cc19..5472db9e87ef8 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -1032,6 +1032,17 @@ static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = {
.missing_phys = BIT(1) | BIT(2),
};
+static const struct sun4i_usb_phy_cfg sun50i_h616_cfg = {
+ .num_phys = 4,
+ .type = sun50i_h6_phy,
+ .disc_thresh = 3,
+ .phyctl_offset = REG_PHYCTL_A33,
+ .dedicated_clocks = true,
+ .phy0_dual_route = true,
+ .hci_phy_ctl_clear = PHY_CTL_SIDDQ,
+ .needs_phy2_siddq = true,
+};
+
static const struct of_device_id sun4i_usb_phy_of_match[] = {
{ .compatible = "allwinner,sun4i-a10-usb-phy", .data = &sun4i_a10_cfg },
{ .compatible = "allwinner,sun5i-a13-usb-phy", .data = &sun5i_a13_cfg },
@@ -1047,6 +1058,7 @@ static const struct of_device_id sun4i_usb_phy_of_match[] = {
{ .compatible = "allwinner,sun50i-a64-usb-phy",
.data = &sun50i_a64_cfg},
{ .compatible = "allwinner,sun50i-h6-usb-phy", .data = &sun50i_h6_cfg },
+ { .compatible = "allwinner,sun50i-h616-usb-phy", .data = &sun50i_h616_cfg },
{ },
};
MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
--
2.25.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v2 5/7] arm64: dts: allwinner: h616: Add USB nodes
2022-10-31 11:13 ` Andre Przywara
(?)
@ 2022-10-31 11:13 ` Andre Przywara
-1 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-10-31 11:13 UTC (permalink / raw)
To: Jernej Skrabec, Samuel Holland, Chen-Yu Tsai,
Kishon Vijay Abraham I, Vinod Koul
Cc: Rob Herring, Krzysztof Kozlowski, Greg Kroah-Hartman, linux-phy,
linux-usb, devicetree, linux-arm-kernel, linux-sunxi,
Karl Kurbjun, Icenowy Zheng
Add the nodes for the MUSB and the four USB host controllers to the SoC
.dtsi, along with the PHY node needed to bind all of them together.
EHCI/OHCI and MUSB are compatible to previous SoCs, but the PHY requires
some quirks (handled in the driver).
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
.../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 160 ++++++++++++++++++
1 file changed, 160 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
index 622a1f7d16412..74aed0d232a9c 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
@@ -504,6 +504,166 @@ mdio0: mdio {
};
};
+ usbotg: usb@5100000 {
+ compatible = "allwinner,sun50i-h616-musb",
+ "allwinner,sun8i-h3-musb";
+ reg = <0x05100000 0x0400>;
+ clocks = <&ccu CLK_BUS_OTG>;
+ resets = <&ccu RST_BUS_OTG>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mc";
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ extcon = <&usbphy 0>;
+ status = "disabled";
+ };
+
+ usbphy: phy@5100400 {
+ compatible = "allwinner,sun50i-h616-usb-phy";
+ reg = <0x05100400 0x24>,
+ <0x05101800 0x14>,
+ <0x05200800 0x14>,
+ <0x05310800 0x14>,
+ <0x05311800 0x14>;
+ reg-names = "phy_ctrl",
+ "pmu0",
+ "pmu1",
+ "pmu2",
+ "pmu3";
+ clocks = <&ccu CLK_USB_PHY0>,
+ <&ccu CLK_USB_PHY1>,
+ <&ccu CLK_USB_PHY2>,
+ <&ccu CLK_USB_PHY3>,
+ <&ccu CLK_BUS_EHCI2>;
+ clock-names = "usb0_phy",
+ "usb1_phy",
+ "usb2_phy",
+ "usb3_phy",
+ "pmu2_clk";
+ resets = <&ccu RST_USB_PHY0>,
+ <&ccu RST_USB_PHY1>,
+ <&ccu RST_USB_PHY2>,
+ <&ccu RST_USB_PHY3>;
+ reset-names = "usb0_reset",
+ "usb1_reset",
+ "usb2_reset",
+ "usb3_reset";
+ status = "disabled";
+ #phy-cells = <1>;
+ };
+
+ ehci0: usb@5101000 {
+ compatible = "allwinner,sun50i-h616-ehci",
+ "generic-ehci";
+ reg = <0x05101000 0x100>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI0>,
+ <&ccu CLK_BUS_EHCI0>,
+ <&ccu CLK_USB_OHCI0>;
+ resets = <&ccu RST_BUS_OHCI0>,
+ <&ccu RST_BUS_EHCI0>;
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci0: usb@5101400 {
+ compatible = "allwinner,sun50i-h616-ohci",
+ "generic-ohci";
+ reg = <0x05101400 0x100>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI0>,
+ <&ccu CLK_USB_OHCI0>;
+ resets = <&ccu RST_BUS_OHCI0>;
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ehci1: usb@5200000 {
+ compatible = "allwinner,sun50i-h616-ehci",
+ "generic-ehci";
+ reg = <0x05200000 0x100>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI1>,
+ <&ccu CLK_BUS_EHCI1>,
+ <&ccu CLK_USB_OHCI1>;
+ resets = <&ccu RST_BUS_OHCI1>,
+ <&ccu RST_BUS_EHCI1>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci1: usb@5200400 {
+ compatible = "allwinner,sun50i-h616-ohci",
+ "generic-ohci";
+ reg = <0x05200400 0x100>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI1>,
+ <&ccu CLK_USB_OHCI1>;
+ resets = <&ccu RST_BUS_OHCI1>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ehci2: usb@5310000 {
+ compatible = "allwinner,sun50i-h616-ehci",
+ "generic-ehci";
+ reg = <0x05310000 0x100>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI2>,
+ <&ccu CLK_BUS_EHCI2>,
+ <&ccu CLK_USB_OHCI2>;
+ resets = <&ccu RST_BUS_OHCI2>,
+ <&ccu RST_BUS_EHCI2>;
+ phys = <&usbphy 2>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci2: usb@5310400 {
+ compatible = "allwinner,sun50i-h616-ohci",
+ "generic-ohci";
+ reg = <0x05310400 0x100>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI2>,
+ <&ccu CLK_USB_OHCI2>;
+ resets = <&ccu RST_BUS_OHCI2>;
+ phys = <&usbphy 2>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ehci3: usb@5311000 {
+ compatible = "allwinner,sun50i-h616-ehci",
+ "generic-ehci";
+ reg = <0x05311000 0x100>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI3>,
+ <&ccu CLK_BUS_EHCI3>,
+ <&ccu CLK_USB_OHCI3>;
+ resets = <&ccu RST_BUS_OHCI3>,
+ <&ccu RST_BUS_EHCI3>;
+ phys = <&usbphy 3>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci3: usb@5311400 {
+ compatible = "allwinner,sun50i-h616-ohci",
+ "generic-ohci";
+ reg = <0x05311400 0x100>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI3>,
+ <&ccu CLK_USB_OHCI3>;
+ resets = <&ccu RST_BUS_OHCI3>;
+ phys = <&usbphy 3>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
rtc: rtc@7000000 {
compatible = "allwinner,sun50i-h616-rtc";
reg = <0x07000000 0x400>;
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v2 5/7] arm64: dts: allwinner: h616: Add USB nodes
@ 2022-10-31 11:13 ` Andre Przywara
0 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-10-31 11:13 UTC (permalink / raw)
To: Jernej Skrabec, Samuel Holland, Chen-Yu Tsai,
Kishon Vijay Abraham I, Vinod Koul
Cc: Rob Herring, Krzysztof Kozlowski, Greg Kroah-Hartman, linux-phy,
linux-usb, devicetree, linux-arm-kernel, linux-sunxi,
Karl Kurbjun, Icenowy Zheng
Add the nodes for the MUSB and the four USB host controllers to the SoC
.dtsi, along with the PHY node needed to bind all of them together.
EHCI/OHCI and MUSB are compatible to previous SoCs, but the PHY requires
some quirks (handled in the driver).
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
.../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 160 ++++++++++++++++++
1 file changed, 160 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
index 622a1f7d16412..74aed0d232a9c 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
@@ -504,6 +504,166 @@ mdio0: mdio {
};
};
+ usbotg: usb@5100000 {
+ compatible = "allwinner,sun50i-h616-musb",
+ "allwinner,sun8i-h3-musb";
+ reg = <0x05100000 0x0400>;
+ clocks = <&ccu CLK_BUS_OTG>;
+ resets = <&ccu RST_BUS_OTG>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mc";
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ extcon = <&usbphy 0>;
+ status = "disabled";
+ };
+
+ usbphy: phy@5100400 {
+ compatible = "allwinner,sun50i-h616-usb-phy";
+ reg = <0x05100400 0x24>,
+ <0x05101800 0x14>,
+ <0x05200800 0x14>,
+ <0x05310800 0x14>,
+ <0x05311800 0x14>;
+ reg-names = "phy_ctrl",
+ "pmu0",
+ "pmu1",
+ "pmu2",
+ "pmu3";
+ clocks = <&ccu CLK_USB_PHY0>,
+ <&ccu CLK_USB_PHY1>,
+ <&ccu CLK_USB_PHY2>,
+ <&ccu CLK_USB_PHY3>,
+ <&ccu CLK_BUS_EHCI2>;
+ clock-names = "usb0_phy",
+ "usb1_phy",
+ "usb2_phy",
+ "usb3_phy",
+ "pmu2_clk";
+ resets = <&ccu RST_USB_PHY0>,
+ <&ccu RST_USB_PHY1>,
+ <&ccu RST_USB_PHY2>,
+ <&ccu RST_USB_PHY3>;
+ reset-names = "usb0_reset",
+ "usb1_reset",
+ "usb2_reset",
+ "usb3_reset";
+ status = "disabled";
+ #phy-cells = <1>;
+ };
+
+ ehci0: usb@5101000 {
+ compatible = "allwinner,sun50i-h616-ehci",
+ "generic-ehci";
+ reg = <0x05101000 0x100>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI0>,
+ <&ccu CLK_BUS_EHCI0>,
+ <&ccu CLK_USB_OHCI0>;
+ resets = <&ccu RST_BUS_OHCI0>,
+ <&ccu RST_BUS_EHCI0>;
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci0: usb@5101400 {
+ compatible = "allwinner,sun50i-h616-ohci",
+ "generic-ohci";
+ reg = <0x05101400 0x100>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI0>,
+ <&ccu CLK_USB_OHCI0>;
+ resets = <&ccu RST_BUS_OHCI0>;
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ehci1: usb@5200000 {
+ compatible = "allwinner,sun50i-h616-ehci",
+ "generic-ehci";
+ reg = <0x05200000 0x100>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI1>,
+ <&ccu CLK_BUS_EHCI1>,
+ <&ccu CLK_USB_OHCI1>;
+ resets = <&ccu RST_BUS_OHCI1>,
+ <&ccu RST_BUS_EHCI1>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci1: usb@5200400 {
+ compatible = "allwinner,sun50i-h616-ohci",
+ "generic-ohci";
+ reg = <0x05200400 0x100>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI1>,
+ <&ccu CLK_USB_OHCI1>;
+ resets = <&ccu RST_BUS_OHCI1>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ehci2: usb@5310000 {
+ compatible = "allwinner,sun50i-h616-ehci",
+ "generic-ehci";
+ reg = <0x05310000 0x100>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI2>,
+ <&ccu CLK_BUS_EHCI2>,
+ <&ccu CLK_USB_OHCI2>;
+ resets = <&ccu RST_BUS_OHCI2>,
+ <&ccu RST_BUS_EHCI2>;
+ phys = <&usbphy 2>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci2: usb@5310400 {
+ compatible = "allwinner,sun50i-h616-ohci",
+ "generic-ohci";
+ reg = <0x05310400 0x100>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI2>,
+ <&ccu CLK_USB_OHCI2>;
+ resets = <&ccu RST_BUS_OHCI2>;
+ phys = <&usbphy 2>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ehci3: usb@5311000 {
+ compatible = "allwinner,sun50i-h616-ehci",
+ "generic-ehci";
+ reg = <0x05311000 0x100>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI3>,
+ <&ccu CLK_BUS_EHCI3>,
+ <&ccu CLK_USB_OHCI3>;
+ resets = <&ccu RST_BUS_OHCI3>,
+ <&ccu RST_BUS_EHCI3>;
+ phys = <&usbphy 3>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci3: usb@5311400 {
+ compatible = "allwinner,sun50i-h616-ohci",
+ "generic-ohci";
+ reg = <0x05311400 0x100>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI3>,
+ <&ccu CLK_USB_OHCI3>;
+ resets = <&ccu RST_BUS_OHCI3>;
+ phys = <&usbphy 3>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
rtc: rtc@7000000 {
compatible = "allwinner,sun50i-h616-rtc";
reg = <0x07000000 0x400>;
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v2 5/7] arm64: dts: allwinner: h616: Add USB nodes
@ 2022-10-31 11:13 ` Andre Przywara
0 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-10-31 11:13 UTC (permalink / raw)
To: Jernej Skrabec, Samuel Holland, Chen-Yu Tsai,
Kishon Vijay Abraham I, Vinod Koul
Cc: Rob Herring, Krzysztof Kozlowski, Greg Kroah-Hartman, linux-phy,
linux-usb, devicetree, linux-arm-kernel, linux-sunxi,
Karl Kurbjun, Icenowy Zheng
Add the nodes for the MUSB and the four USB host controllers to the SoC
.dtsi, along with the PHY node needed to bind all of them together.
EHCI/OHCI and MUSB are compatible to previous SoCs, but the PHY requires
some quirks (handled in the driver).
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
.../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 160 ++++++++++++++++++
1 file changed, 160 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
index 622a1f7d16412..74aed0d232a9c 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
@@ -504,6 +504,166 @@ mdio0: mdio {
};
};
+ usbotg: usb@5100000 {
+ compatible = "allwinner,sun50i-h616-musb",
+ "allwinner,sun8i-h3-musb";
+ reg = <0x05100000 0x0400>;
+ clocks = <&ccu CLK_BUS_OTG>;
+ resets = <&ccu RST_BUS_OTG>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mc";
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ extcon = <&usbphy 0>;
+ status = "disabled";
+ };
+
+ usbphy: phy@5100400 {
+ compatible = "allwinner,sun50i-h616-usb-phy";
+ reg = <0x05100400 0x24>,
+ <0x05101800 0x14>,
+ <0x05200800 0x14>,
+ <0x05310800 0x14>,
+ <0x05311800 0x14>;
+ reg-names = "phy_ctrl",
+ "pmu0",
+ "pmu1",
+ "pmu2",
+ "pmu3";
+ clocks = <&ccu CLK_USB_PHY0>,
+ <&ccu CLK_USB_PHY1>,
+ <&ccu CLK_USB_PHY2>,
+ <&ccu CLK_USB_PHY3>,
+ <&ccu CLK_BUS_EHCI2>;
+ clock-names = "usb0_phy",
+ "usb1_phy",
+ "usb2_phy",
+ "usb3_phy",
+ "pmu2_clk";
+ resets = <&ccu RST_USB_PHY0>,
+ <&ccu RST_USB_PHY1>,
+ <&ccu RST_USB_PHY2>,
+ <&ccu RST_USB_PHY3>;
+ reset-names = "usb0_reset",
+ "usb1_reset",
+ "usb2_reset",
+ "usb3_reset";
+ status = "disabled";
+ #phy-cells = <1>;
+ };
+
+ ehci0: usb@5101000 {
+ compatible = "allwinner,sun50i-h616-ehci",
+ "generic-ehci";
+ reg = <0x05101000 0x100>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI0>,
+ <&ccu CLK_BUS_EHCI0>,
+ <&ccu CLK_USB_OHCI0>;
+ resets = <&ccu RST_BUS_OHCI0>,
+ <&ccu RST_BUS_EHCI0>;
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci0: usb@5101400 {
+ compatible = "allwinner,sun50i-h616-ohci",
+ "generic-ohci";
+ reg = <0x05101400 0x100>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI0>,
+ <&ccu CLK_USB_OHCI0>;
+ resets = <&ccu RST_BUS_OHCI0>;
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ehci1: usb@5200000 {
+ compatible = "allwinner,sun50i-h616-ehci",
+ "generic-ehci";
+ reg = <0x05200000 0x100>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI1>,
+ <&ccu CLK_BUS_EHCI1>,
+ <&ccu CLK_USB_OHCI1>;
+ resets = <&ccu RST_BUS_OHCI1>,
+ <&ccu RST_BUS_EHCI1>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci1: usb@5200400 {
+ compatible = "allwinner,sun50i-h616-ohci",
+ "generic-ohci";
+ reg = <0x05200400 0x100>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI1>,
+ <&ccu CLK_USB_OHCI1>;
+ resets = <&ccu RST_BUS_OHCI1>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ehci2: usb@5310000 {
+ compatible = "allwinner,sun50i-h616-ehci",
+ "generic-ehci";
+ reg = <0x05310000 0x100>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI2>,
+ <&ccu CLK_BUS_EHCI2>,
+ <&ccu CLK_USB_OHCI2>;
+ resets = <&ccu RST_BUS_OHCI2>,
+ <&ccu RST_BUS_EHCI2>;
+ phys = <&usbphy 2>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci2: usb@5310400 {
+ compatible = "allwinner,sun50i-h616-ohci",
+ "generic-ohci";
+ reg = <0x05310400 0x100>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI2>,
+ <&ccu CLK_USB_OHCI2>;
+ resets = <&ccu RST_BUS_OHCI2>;
+ phys = <&usbphy 2>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ehci3: usb@5311000 {
+ compatible = "allwinner,sun50i-h616-ehci",
+ "generic-ehci";
+ reg = <0x05311000 0x100>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI3>,
+ <&ccu CLK_BUS_EHCI3>,
+ <&ccu CLK_USB_OHCI3>;
+ resets = <&ccu RST_BUS_OHCI3>,
+ <&ccu RST_BUS_EHCI3>;
+ phys = <&usbphy 3>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci3: usb@5311400 {
+ compatible = "allwinner,sun50i-h616-ohci",
+ "generic-ohci";
+ reg = <0x05311400 0x100>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI3>,
+ <&ccu CLK_USB_OHCI3>;
+ resets = <&ccu RST_BUS_OHCI3>;
+ phys = <&usbphy 3>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
rtc: rtc@7000000 {
compatible = "allwinner,sun50i-h616-rtc";
reg = <0x07000000 0x400>;
--
2.25.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v2 6/7] arm64: dts: allwinner: h616: OrangePi Zero 2: Add USB nodes
2022-10-31 11:13 ` Andre Przywara
(?)
@ 2022-10-31 11:13 ` Andre Przywara
-1 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-10-31 11:13 UTC (permalink / raw)
To: Jernej Skrabec, Samuel Holland, Chen-Yu Tsai,
Kishon Vijay Abraham I, Vinod Koul
Cc: Rob Herring, Krzysztof Kozlowski, Greg Kroah-Hartman, linux-phy,
linux-usb, devicetree, linux-arm-kernel, linux-sunxi,
Karl Kurbjun, Icenowy Zheng
The OrangePi Zero 2 has one USB-A host port, VBUS is provided by
a GPIO controlled regulator.
The USB-C port is meant to power the board, but is also connected to
the USB 0 port, which we configure as an MUSB peripheral.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
.../allwinner/sun50i-h616-orangepi-zero2.dts | 41 +++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
index 02893f3ac99d4..cb8600d0ea1ef 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
@@ -49,8 +49,24 @@ reg_vcc5v: vcc5v {
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
+
+ reg_usb1_vbus: regulator-usb1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb1-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <®_vcc5v>;
+ enable-active-high;
+ gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */
+ };
};
+&ehci1 {
+ status = "okay";
+};
+
+/* USB 2 & 3 are on headers only. */
+
&emac0 {
pinctrl-names = "default";
pinctrl-0 = <&ext_rgmii_pins>;
@@ -76,6 +92,10 @@ &mmc0 {
status = "okay";
};
+&ohci1 {
+ status = "okay";
+};
+
&r_rsb {
status = "okay";
@@ -211,3 +231,24 @@ &uart0 {
pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};
+
+&usbotg {
+ /*
+ * PHY0 pins are connected to a USB-C socket, but a role switch
+ * is not implemented: both CC pins are pulled to GND.
+ * The VBUS pins power the device, so a fixed peripheral mode
+ * is the best choice.
+ * The board can be powered via GPIOs, in this case port0 *can*
+ * act as a host (with a cable/adapter ignoring CC), as VBUS is
+ * then provided by the GPIOs. Any user of this setup would
+ * need to adjust the DT accordingly: dr_mode set to "host",
+ * enabling OHCI0 and EHCI0.
+ */
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ status = "okay";
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v2 6/7] arm64: dts: allwinner: h616: OrangePi Zero 2: Add USB nodes
@ 2022-10-31 11:13 ` Andre Przywara
0 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-10-31 11:13 UTC (permalink / raw)
To: Jernej Skrabec, Samuel Holland, Chen-Yu Tsai,
Kishon Vijay Abraham I, Vinod Koul
Cc: Rob Herring, Krzysztof Kozlowski, Greg Kroah-Hartman, linux-phy,
linux-usb, devicetree, linux-arm-kernel, linux-sunxi,
Karl Kurbjun, Icenowy Zheng
The OrangePi Zero 2 has one USB-A host port, VBUS is provided by
a GPIO controlled regulator.
The USB-C port is meant to power the board, but is also connected to
the USB 0 port, which we configure as an MUSB peripheral.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
.../allwinner/sun50i-h616-orangepi-zero2.dts | 41 +++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
index 02893f3ac99d4..cb8600d0ea1ef 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
@@ -49,8 +49,24 @@ reg_vcc5v: vcc5v {
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
+
+ reg_usb1_vbus: regulator-usb1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb1-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <®_vcc5v>;
+ enable-active-high;
+ gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */
+ };
};
+&ehci1 {
+ status = "okay";
+};
+
+/* USB 2 & 3 are on headers only. */
+
&emac0 {
pinctrl-names = "default";
pinctrl-0 = <&ext_rgmii_pins>;
@@ -76,6 +92,10 @@ &mmc0 {
status = "okay";
};
+&ohci1 {
+ status = "okay";
+};
+
&r_rsb {
status = "okay";
@@ -211,3 +231,24 @@ &uart0 {
pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};
+
+&usbotg {
+ /*
+ * PHY0 pins are connected to a USB-C socket, but a role switch
+ * is not implemented: both CC pins are pulled to GND.
+ * The VBUS pins power the device, so a fixed peripheral mode
+ * is the best choice.
+ * The board can be powered via GPIOs, in this case port0 *can*
+ * act as a host (with a cable/adapter ignoring CC), as VBUS is
+ * then provided by the GPIOs. Any user of this setup would
+ * need to adjust the DT accordingly: dr_mode set to "host",
+ * enabling OHCI0 and EHCI0.
+ */
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ status = "okay";
+};
--
2.25.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v2 6/7] arm64: dts: allwinner: h616: OrangePi Zero 2: Add USB nodes
@ 2022-10-31 11:13 ` Andre Przywara
0 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-10-31 11:13 UTC (permalink / raw)
To: Jernej Skrabec, Samuel Holland, Chen-Yu Tsai,
Kishon Vijay Abraham I, Vinod Koul
Cc: Rob Herring, Krzysztof Kozlowski, Greg Kroah-Hartman, linux-phy,
linux-usb, devicetree, linux-arm-kernel, linux-sunxi,
Karl Kurbjun, Icenowy Zheng
The OrangePi Zero 2 has one USB-A host port, VBUS is provided by
a GPIO controlled regulator.
The USB-C port is meant to power the board, but is also connected to
the USB 0 port, which we configure as an MUSB peripheral.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
.../allwinner/sun50i-h616-orangepi-zero2.dts | 41 +++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
index 02893f3ac99d4..cb8600d0ea1ef 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
@@ -49,8 +49,24 @@ reg_vcc5v: vcc5v {
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
+
+ reg_usb1_vbus: regulator-usb1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb1-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <®_vcc5v>;
+ enable-active-high;
+ gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */
+ };
};
+&ehci1 {
+ status = "okay";
+};
+
+/* USB 2 & 3 are on headers only. */
+
&emac0 {
pinctrl-names = "default";
pinctrl-0 = <&ext_rgmii_pins>;
@@ -76,6 +92,10 @@ &mmc0 {
status = "okay";
};
+&ohci1 {
+ status = "okay";
+};
+
&r_rsb {
status = "okay";
@@ -211,3 +231,24 @@ &uart0 {
pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};
+
+&usbotg {
+ /*
+ * PHY0 pins are connected to a USB-C socket, but a role switch
+ * is not implemented: both CC pins are pulled to GND.
+ * The VBUS pins power the device, so a fixed peripheral mode
+ * is the best choice.
+ * The board can be powered via GPIOs, in this case port0 *can*
+ * act as a host (with a cable/adapter ignoring CC), as VBUS is
+ * then provided by the GPIOs. Any user of this setup would
+ * need to adjust the DT accordingly: dr_mode set to "host",
+ * enabling OHCI0 and EHCI0.
+ */
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ status = "okay";
+};
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v2 7/7] arm64: dts: allwinner: h616: X96 Mate: Add USB nodes
2022-10-31 11:13 ` Andre Przywara
(?)
@ 2022-10-31 11:13 ` Andre Przywara
-1 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-10-31 11:13 UTC (permalink / raw)
To: Jernej Skrabec, Samuel Holland, Chen-Yu Tsai,
Kishon Vijay Abraham I, Vinod Koul
Cc: Rob Herring, Krzysztof Kozlowski, Greg Kroah-Hartman, linux-phy,
linux-usb, devicetree, linux-arm-kernel, linux-sunxi,
Karl Kurbjun, Icenowy Zheng
The X96 Mate TV box has two USB-A ports, VBUS is always on and connected
to the DC input.
Since USB port 0 is connected to an USB-A receptable, we configure it
as a host port. Using it as a peripheral is dangerous, because VBUS is
always on.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
.../dts/allwinner/sun50i-h616-x96-mate.dts | 25 +++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
index 6619db34714a4..07424c28b696c 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
@@ -32,6 +32,14 @@ reg_vcc5v: vcc5v {
};
};
+&ehci0 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
&ir {
status = "okay";
};
@@ -54,6 +62,14 @@ &mmc2 {
status = "okay";
};
+&ohci0 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
&r_rsb {
status = "okay";
@@ -175,3 +191,12 @@ &uart0 {
pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};
+
+&usbotg {
+ dr_mode = "host"; /* USB A type receptable */
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v2 7/7] arm64: dts: allwinner: h616: X96 Mate: Add USB nodes
@ 2022-10-31 11:13 ` Andre Przywara
0 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-10-31 11:13 UTC (permalink / raw)
To: Jernej Skrabec, Samuel Holland, Chen-Yu Tsai,
Kishon Vijay Abraham I, Vinod Koul
Cc: Rob Herring, Krzysztof Kozlowski, Greg Kroah-Hartman, linux-phy,
linux-usb, devicetree, linux-arm-kernel, linux-sunxi,
Karl Kurbjun, Icenowy Zheng
The X96 Mate TV box has two USB-A ports, VBUS is always on and connected
to the DC input.
Since USB port 0 is connected to an USB-A receptable, we configure it
as a host port. Using it as a peripheral is dangerous, because VBUS is
always on.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
.../dts/allwinner/sun50i-h616-x96-mate.dts | 25 +++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
index 6619db34714a4..07424c28b696c 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
@@ -32,6 +32,14 @@ reg_vcc5v: vcc5v {
};
};
+&ehci0 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
&ir {
status = "okay";
};
@@ -54,6 +62,14 @@ &mmc2 {
status = "okay";
};
+&ohci0 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
&r_rsb {
status = "okay";
@@ -175,3 +191,12 @@ &uart0 {
pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};
+
+&usbotg {
+ dr_mode = "host"; /* USB A type receptable */
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
--
2.25.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v2 7/7] arm64: dts: allwinner: h616: X96 Mate: Add USB nodes
@ 2022-10-31 11:13 ` Andre Przywara
0 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-10-31 11:13 UTC (permalink / raw)
To: Jernej Skrabec, Samuel Holland, Chen-Yu Tsai,
Kishon Vijay Abraham I, Vinod Koul
Cc: Rob Herring, Krzysztof Kozlowski, Greg Kroah-Hartman, linux-phy,
linux-usb, devicetree, linux-arm-kernel, linux-sunxi,
Karl Kurbjun, Icenowy Zheng
The X96 Mate TV box has two USB-A ports, VBUS is always on and connected
to the DC input.
Since USB port 0 is connected to an USB-A receptable, we configure it
as a host port. Using it as a peripheral is dangerous, because VBUS is
always on.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
.../dts/allwinner/sun50i-h616-x96-mate.dts | 25 +++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
index 6619db34714a4..07424c28b696c 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
@@ -32,6 +32,14 @@ reg_vcc5v: vcc5v {
};
};
+&ehci0 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
&ir {
status = "okay";
};
@@ -54,6 +62,14 @@ &mmc2 {
status = "okay";
};
+&ohci0 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
&r_rsb {
status = "okay";
@@ -175,3 +191,12 @@ &uart0 {
pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};
+
+&usbotg {
+ dr_mode = "host"; /* USB A type receptable */
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 48+ messages in thread
* Re: [PATCH v2 2/7] dt-bindings: phy: Add special clock for Allwinner H616 PHY
2022-10-31 11:13 ` Andre Przywara
(?)
@ 2022-11-01 1:03 ` Rob Herring
-1 siblings, 0 replies; 48+ messages in thread
From: Rob Herring @ 2022-11-01 1:03 UTC (permalink / raw)
To: Andre Przywara
Cc: linux-phy, devicetree, Samuel Holland, linux-usb, Chen-Yu Tsai,
Karl Kurbjun, Vinod Koul, Jernej Skrabec, Icenowy Zheng,
Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski,
linux-sunxi, Kishon Vijay Abraham I, linux-arm-kernel
On Mon, 31 Oct 2022 11:13:53 +0000, Andre Przywara wrote:
> The USB PHY IP in the Allwinner H616 SoC requires a quirk that involves
> some resources from port 2's PHY and HCI IP. In particular the PMU clock
> for port 2 must be surely ungated before accessing the REG_HCI_PHY_CTL
> register of port 2. To allow each USB port to be controlled
> independently of port 2, we need a handle to that particular PMU clock
> in the *PHY* node, as the HCI and PHY part might be handled by separate
> drivers.
>
> Add that clock to the requirements of the H616 PHY binding, so that a
> PHY driver can apply the quirk in isolation, without requiring help from
> port 2's HCI driver.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> .../phy/allwinner,sun8i-h3-usb-phy.yaml | 26 +++++++++++++++++++
> 1 file changed, 26 insertions(+)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v2 2/7] dt-bindings: phy: Add special clock for Allwinner H616 PHY
@ 2022-11-01 1:03 ` Rob Herring
0 siblings, 0 replies; 48+ messages in thread
From: Rob Herring @ 2022-11-01 1:03 UTC (permalink / raw)
To: Andre Przywara
Cc: linux-phy, devicetree, Samuel Holland, linux-usb, Chen-Yu Tsai,
Karl Kurbjun, Vinod Koul, Jernej Skrabec, Icenowy Zheng,
Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski,
linux-sunxi, Kishon Vijay Abraham I, linux-arm-kernel
On Mon, 31 Oct 2022 11:13:53 +0000, Andre Przywara wrote:
> The USB PHY IP in the Allwinner H616 SoC requires a quirk that involves
> some resources from port 2's PHY and HCI IP. In particular the PMU clock
> for port 2 must be surely ungated before accessing the REG_HCI_PHY_CTL
> register of port 2. To allow each USB port to be controlled
> independently of port 2, we need a handle to that particular PMU clock
> in the *PHY* node, as the HCI and PHY part might be handled by separate
> drivers.
>
> Add that clock to the requirements of the H616 PHY binding, so that a
> PHY driver can apply the quirk in isolation, without requiring help from
> port 2's HCI driver.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> .../phy/allwinner,sun8i-h3-usb-phy.yaml | 26 +++++++++++++++++++
> 1 file changed, 26 insertions(+)
>
Reviewed-by: Rob Herring <robh@kernel.org>
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v2 2/7] dt-bindings: phy: Add special clock for Allwinner H616 PHY
@ 2022-11-01 1:03 ` Rob Herring
0 siblings, 0 replies; 48+ messages in thread
From: Rob Herring @ 2022-11-01 1:03 UTC (permalink / raw)
To: Andre Przywara
Cc: linux-phy, devicetree, Samuel Holland, linux-usb, Chen-Yu Tsai,
Karl Kurbjun, Vinod Koul, Jernej Skrabec, Icenowy Zheng,
Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski,
linux-sunxi, Kishon Vijay Abraham I, linux-arm-kernel
On Mon, 31 Oct 2022 11:13:53 +0000, Andre Przywara wrote:
> The USB PHY IP in the Allwinner H616 SoC requires a quirk that involves
> some resources from port 2's PHY and HCI IP. In particular the PMU clock
> for port 2 must be surely ungated before accessing the REG_HCI_PHY_CTL
> register of port 2. To allow each USB port to be controlled
> independently of port 2, we need a handle to that particular PMU clock
> in the *PHY* node, as the HCI and PHY part might be handled by separate
> drivers.
>
> Add that clock to the requirements of the H616 PHY binding, so that a
> PHY driver can apply the quirk in isolation, without requiring help from
> port 2's HCI driver.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> .../phy/allwinner,sun8i-h3-usb-phy.yaml | 26 +++++++++++++++++++
> 1 file changed, 26 insertions(+)
>
Reviewed-by: Rob Herring <robh@kernel.org>
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v2 2/7] dt-bindings: phy: Add special clock for Allwinner H616 PHY
2022-10-31 11:13 ` Andre Przywara
(?)
@ 2022-11-05 7:45 ` Vinod Koul
-1 siblings, 0 replies; 48+ messages in thread
From: Vinod Koul @ 2022-11-05 7:45 UTC (permalink / raw)
To: Andre Przywara
Cc: Jernej Skrabec, Samuel Holland, Chen-Yu Tsai,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
Greg Kroah-Hartman, linux-phy, linux-usb, devicetree,
linux-arm-kernel, linux-sunxi, Karl Kurbjun, Icenowy Zheng
On 31-10-22, 11:13, Andre Przywara wrote:
> The USB PHY IP in the Allwinner H616 SoC requires a quirk that involves
> some resources from port 2's PHY and HCI IP. In particular the PMU clock
> for port 2 must be surely ungated before accessing the REG_HCI_PHY_CTL
> register of port 2. To allow each USB port to be controlled
> independently of port 2, we need a handle to that particular PMU clock
> in the *PHY* node, as the HCI and PHY part might be handled by separate
> drivers.
>
> Add that clock to the requirements of the H616 PHY binding, so that a
> PHY driver can apply the quirk in isolation, without requiring help from
> port 2's HCI driver.
Applied, thanks
--
~Vinod
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v2 2/7] dt-bindings: phy: Add special clock for Allwinner H616 PHY
@ 2022-11-05 7:45 ` Vinod Koul
0 siblings, 0 replies; 48+ messages in thread
From: Vinod Koul @ 2022-11-05 7:45 UTC (permalink / raw)
To: Andre Przywara
Cc: Jernej Skrabec, Samuel Holland, Chen-Yu Tsai,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
Greg Kroah-Hartman, linux-phy, linux-usb, devicetree,
linux-arm-kernel, linux-sunxi, Karl Kurbjun, Icenowy Zheng
On 31-10-22, 11:13, Andre Przywara wrote:
> The USB PHY IP in the Allwinner H616 SoC requires a quirk that involves
> some resources from port 2's PHY and HCI IP. In particular the PMU clock
> for port 2 must be surely ungated before accessing the REG_HCI_PHY_CTL
> register of port 2. To allow each USB port to be controlled
> independently of port 2, we need a handle to that particular PMU clock
> in the *PHY* node, as the HCI and PHY part might be handled by separate
> drivers.
>
> Add that clock to the requirements of the H616 PHY binding, so that a
> PHY driver can apply the quirk in isolation, without requiring help from
> port 2's HCI driver.
Applied, thanks
--
~Vinod
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v2 2/7] dt-bindings: phy: Add special clock for Allwinner H616 PHY
@ 2022-11-05 7:45 ` Vinod Koul
0 siblings, 0 replies; 48+ messages in thread
From: Vinod Koul @ 2022-11-05 7:45 UTC (permalink / raw)
To: Andre Przywara
Cc: Jernej Skrabec, Samuel Holland, Chen-Yu Tsai,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
Greg Kroah-Hartman, linux-phy, linux-usb, devicetree,
linux-arm-kernel, linux-sunxi, Karl Kurbjun, Icenowy Zheng
On 31-10-22, 11:13, Andre Przywara wrote:
> The USB PHY IP in the Allwinner H616 SoC requires a quirk that involves
> some resources from port 2's PHY and HCI IP. In particular the PMU clock
> for port 2 must be surely ungated before accessing the REG_HCI_PHY_CTL
> register of port 2. To allow each USB port to be controlled
> independently of port 2, we need a handle to that particular PMU clock
> in the *PHY* node, as the HCI and PHY part might be handled by separate
> drivers.
>
> Add that clock to the requirements of the H616 PHY binding, so that a
> PHY driver can apply the quirk in isolation, without requiring help from
> port 2's HCI driver.
Applied, thanks
--
~Vinod
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v2 3/7] phy: sun4i-usb: Introduce port2 SIDDQ quirk
2022-10-31 11:13 ` Andre Przywara
(?)
@ 2022-11-05 7:46 ` Vinod Koul
-1 siblings, 0 replies; 48+ messages in thread
From: Vinod Koul @ 2022-11-05 7:46 UTC (permalink / raw)
To: Andre Przywara
Cc: Jernej Skrabec, Samuel Holland, Chen-Yu Tsai,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
Greg Kroah-Hartman, linux-phy, linux-usb, devicetree,
linux-arm-kernel, linux-sunxi, Karl Kurbjun, Icenowy Zheng
On 31-10-22, 11:13, Andre Przywara wrote:
> At least the Allwinner H616 SoC requires a weird quirk to make most
> USB PHYs work: Only port2 works out of the box, but all other ports
> need some help from this port2 to work correctly: The CLK_BUS_PHY2 and
> RST_USB_PHY2 clock and reset need to be enabled, and the SIDDQ bit in
> the PMU PHY control register needs to be cleared. For this register to
> be accessible, CLK_BUS_ECHI2 needs to be ungated. Don't ask ....
>
> Instead of disguising this as some generic feature, treat it more like
> a quirk (what it really is):
> If the quirk bit is set, and we initialise a PHY other than PHY2, ungate
> this one special clock, and clear the SIDDQ bit. We also pick the clock
> and reset from PHY2 and enable them as well.
Applied, thanks
--
~Vinod
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v2 3/7] phy: sun4i-usb: Introduce port2 SIDDQ quirk
@ 2022-11-05 7:46 ` Vinod Koul
0 siblings, 0 replies; 48+ messages in thread
From: Vinod Koul @ 2022-11-05 7:46 UTC (permalink / raw)
To: Andre Przywara
Cc: Jernej Skrabec, Samuel Holland, Chen-Yu Tsai,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
Greg Kroah-Hartman, linux-phy, linux-usb, devicetree,
linux-arm-kernel, linux-sunxi, Karl Kurbjun, Icenowy Zheng
On 31-10-22, 11:13, Andre Przywara wrote:
> At least the Allwinner H616 SoC requires a weird quirk to make most
> USB PHYs work: Only port2 works out of the box, but all other ports
> need some help from this port2 to work correctly: The CLK_BUS_PHY2 and
> RST_USB_PHY2 clock and reset need to be enabled, and the SIDDQ bit in
> the PMU PHY control register needs to be cleared. For this register to
> be accessible, CLK_BUS_ECHI2 needs to be ungated. Don't ask ....
>
> Instead of disguising this as some generic feature, treat it more like
> a quirk (what it really is):
> If the quirk bit is set, and we initialise a PHY other than PHY2, ungate
> this one special clock, and clear the SIDDQ bit. We also pick the clock
> and reset from PHY2 and enable them as well.
Applied, thanks
--
~Vinod
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v2 3/7] phy: sun4i-usb: Introduce port2 SIDDQ quirk
@ 2022-11-05 7:46 ` Vinod Koul
0 siblings, 0 replies; 48+ messages in thread
From: Vinod Koul @ 2022-11-05 7:46 UTC (permalink / raw)
To: Andre Przywara
Cc: Jernej Skrabec, Samuel Holland, Chen-Yu Tsai,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
Greg Kroah-Hartman, linux-phy, linux-usb, devicetree,
linux-arm-kernel, linux-sunxi, Karl Kurbjun, Icenowy Zheng
On 31-10-22, 11:13, Andre Przywara wrote:
> At least the Allwinner H616 SoC requires a weird quirk to make most
> USB PHYs work: Only port2 works out of the box, but all other ports
> need some help from this port2 to work correctly: The CLK_BUS_PHY2 and
> RST_USB_PHY2 clock and reset need to be enabled, and the SIDDQ bit in
> the PMU PHY control register needs to be cleared. For this register to
> be accessible, CLK_BUS_ECHI2 needs to be ungated. Don't ask ....
>
> Instead of disguising this as some generic feature, treat it more like
> a quirk (what it really is):
> If the quirk bit is set, and we initialise a PHY other than PHY2, ungate
> this one special clock, and clear the SIDDQ bit. We also pick the clock
> and reset from PHY2 and enable them as well.
Applied, thanks
--
~Vinod
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v2 4/7] phy: sun4i-usb: Add support for the H616 USB PHY
2022-10-31 11:13 ` Andre Przywara
(?)
@ 2022-11-05 7:46 ` Vinod Koul
-1 siblings, 0 replies; 48+ messages in thread
From: Vinod Koul @ 2022-11-05 7:46 UTC (permalink / raw)
To: Andre Przywara
Cc: Jernej Skrabec, Samuel Holland, Chen-Yu Tsai,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
Greg Kroah-Hartman, linux-phy, linux-usb, devicetree,
linux-arm-kernel, linux-sunxi, Karl Kurbjun, Icenowy Zheng
On 31-10-22, 11:13, Andre Przywara wrote:
> The USB PHY used in the Allwinner H616 SoC inherits some traits from its
> various predecessors: it has four full PHYs like the H3, needs some
> extra bits to be set like the H6, and puts SIDDQ on a different bit like
> the A100. Plus it needs this weird PHY2 quirk.
>
> Name all those properties in a new config struct and assign a new
> compatible name to it.
Applied, thanks
--
~Vinod
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v2 4/7] phy: sun4i-usb: Add support for the H616 USB PHY
@ 2022-11-05 7:46 ` Vinod Koul
0 siblings, 0 replies; 48+ messages in thread
From: Vinod Koul @ 2022-11-05 7:46 UTC (permalink / raw)
To: Andre Przywara
Cc: Jernej Skrabec, Samuel Holland, Chen-Yu Tsai,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
Greg Kroah-Hartman, linux-phy, linux-usb, devicetree,
linux-arm-kernel, linux-sunxi, Karl Kurbjun, Icenowy Zheng
On 31-10-22, 11:13, Andre Przywara wrote:
> The USB PHY used in the Allwinner H616 SoC inherits some traits from its
> various predecessors: it has four full PHYs like the H3, needs some
> extra bits to be set like the H6, and puts SIDDQ on a different bit like
> the A100. Plus it needs this weird PHY2 quirk.
>
> Name all those properties in a new config struct and assign a new
> compatible name to it.
Applied, thanks
--
~Vinod
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v2 4/7] phy: sun4i-usb: Add support for the H616 USB PHY
@ 2022-11-05 7:46 ` Vinod Koul
0 siblings, 0 replies; 48+ messages in thread
From: Vinod Koul @ 2022-11-05 7:46 UTC (permalink / raw)
To: Andre Przywara
Cc: Jernej Skrabec, Samuel Holland, Chen-Yu Tsai,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
Greg Kroah-Hartman, linux-phy, linux-usb, devicetree,
linux-arm-kernel, linux-sunxi, Karl Kurbjun, Icenowy Zheng
On 31-10-22, 11:13, Andre Przywara wrote:
> The USB PHY used in the Allwinner H616 SoC inherits some traits from its
> various predecessors: it has four full PHYs like the H3, needs some
> extra bits to be set like the H6, and puts SIDDQ on a different bit like
> the A100. Plus it needs this weird PHY2 quirk.
>
> Name all those properties in a new config struct and assign a new
> compatible name to it.
Applied, thanks
--
~Vinod
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v2 5/7] arm64: dts: allwinner: h616: Add USB nodes
2022-10-31 11:13 ` Andre Przywara
(?)
@ 2022-11-05 21:07 ` Jernej Škrabec
-1 siblings, 0 replies; 48+ messages in thread
From: Jernej Škrabec @ 2022-11-05 21:07 UTC (permalink / raw)
To: Samuel Holland, Chen-Yu Tsai, Kishon Vijay Abraham I, Vinod Koul,
Andre Przywara
Cc: Rob Herring, Krzysztof Kozlowski, Greg Kroah-Hartman, linux-phy,
linux-usb, devicetree, linux-arm-kernel, linux-sunxi,
Karl Kurbjun, Icenowy Zheng
Dne ponedeljek, 31. oktober 2022 ob 12:13:56 CET je Andre Przywara napisal(a):
> Add the nodes for the MUSB and the four USB host controllers to the SoC
> .dtsi, along with the PHY node needed to bind all of them together.
>
> EHCI/OHCI and MUSB are compatible to previous SoCs, but the PHY requires
> some quirks (handled in the driver).
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Best regards,
Jernej
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v2 5/7] arm64: dts: allwinner: h616: Add USB nodes
@ 2022-11-05 21:07 ` Jernej Škrabec
0 siblings, 0 replies; 48+ messages in thread
From: Jernej Škrabec @ 2022-11-05 21:07 UTC (permalink / raw)
To: Samuel Holland, Chen-Yu Tsai, Kishon Vijay Abraham I, Vinod Koul,
Andre Przywara
Cc: Rob Herring, Krzysztof Kozlowski, Greg Kroah-Hartman, linux-phy,
linux-usb, devicetree, linux-arm-kernel, linux-sunxi,
Karl Kurbjun, Icenowy Zheng
Dne ponedeljek, 31. oktober 2022 ob 12:13:56 CET je Andre Przywara napisal(a):
> Add the nodes for the MUSB and the four USB host controllers to the SoC
> .dtsi, along with the PHY node needed to bind all of them together.
>
> EHCI/OHCI and MUSB are compatible to previous SoCs, but the PHY requires
> some quirks (handled in the driver).
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Best regards,
Jernej
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v2 5/7] arm64: dts: allwinner: h616: Add USB nodes
@ 2022-11-05 21:07 ` Jernej Škrabec
0 siblings, 0 replies; 48+ messages in thread
From: Jernej Škrabec @ 2022-11-05 21:07 UTC (permalink / raw)
To: Samuel Holland, Chen-Yu Tsai, Kishon Vijay Abraham I, Vinod Koul,
Andre Przywara
Cc: Rob Herring, Krzysztof Kozlowski, Greg Kroah-Hartman, linux-phy,
linux-usb, devicetree, linux-arm-kernel, linux-sunxi,
Karl Kurbjun, Icenowy Zheng
Dne ponedeljek, 31. oktober 2022 ob 12:13:56 CET je Andre Przywara napisal(a):
> Add the nodes for the MUSB and the four USB host controllers to the SoC
> .dtsi, along with the PHY node needed to bind all of them together.
>
> EHCI/OHCI and MUSB are compatible to previous SoCs, but the PHY requires
> some quirks (handled in the driver).
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Best regards,
Jernej
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v2 6/7] arm64: dts: allwinner: h616: OrangePi Zero 2: Add USB nodes
2022-10-31 11:13 ` Andre Przywara
(?)
@ 2022-11-05 21:13 ` Jernej Škrabec
-1 siblings, 0 replies; 48+ messages in thread
From: Jernej Škrabec @ 2022-11-05 21:13 UTC (permalink / raw)
To: Samuel Holland, Chen-Yu Tsai, Kishon Vijay Abraham I, Vinod Koul,
Andre Przywara
Cc: Rob Herring, Krzysztof Kozlowski, Greg Kroah-Hartman, linux-phy,
linux-usb, devicetree, linux-arm-kernel, linux-sunxi,
Karl Kurbjun, Icenowy Zheng
Dne ponedeljek, 31. oktober 2022 ob 12:13:57 CET je Andre Przywara napisal(a):
> The OrangePi Zero 2 has one USB-A host port, VBUS is provided by
> a GPIO controlled regulator.
> The USB-C port is meant to power the board, but is also connected to
> the USB 0 port, which we configure as an MUSB peripheral.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Best regards,
Jernej
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v2 6/7] arm64: dts: allwinner: h616: OrangePi Zero 2: Add USB nodes
@ 2022-11-05 21:13 ` Jernej Škrabec
0 siblings, 0 replies; 48+ messages in thread
From: Jernej Škrabec @ 2022-11-05 21:13 UTC (permalink / raw)
To: Samuel Holland, Chen-Yu Tsai, Kishon Vijay Abraham I, Vinod Koul,
Andre Przywara
Cc: Rob Herring, Krzysztof Kozlowski, Greg Kroah-Hartman, linux-phy,
linux-usb, devicetree, linux-arm-kernel, linux-sunxi,
Karl Kurbjun, Icenowy Zheng
Dne ponedeljek, 31. oktober 2022 ob 12:13:57 CET je Andre Przywara napisal(a):
> The OrangePi Zero 2 has one USB-A host port, VBUS is provided by
> a GPIO controlled regulator.
> The USB-C port is meant to power the board, but is also connected to
> the USB 0 port, which we configure as an MUSB peripheral.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Best regards,
Jernej
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v2 6/7] arm64: dts: allwinner: h616: OrangePi Zero 2: Add USB nodes
@ 2022-11-05 21:13 ` Jernej Škrabec
0 siblings, 0 replies; 48+ messages in thread
From: Jernej Škrabec @ 2022-11-05 21:13 UTC (permalink / raw)
To: Samuel Holland, Chen-Yu Tsai, Kishon Vijay Abraham I, Vinod Koul,
Andre Przywara
Cc: Rob Herring, Krzysztof Kozlowski, Greg Kroah-Hartman, linux-phy,
linux-usb, devicetree, linux-arm-kernel, linux-sunxi,
Karl Kurbjun, Icenowy Zheng
Dne ponedeljek, 31. oktober 2022 ob 12:13:57 CET je Andre Przywara napisal(a):
> The OrangePi Zero 2 has one USB-A host port, VBUS is provided by
> a GPIO controlled regulator.
> The USB-C port is meant to power the board, but is also connected to
> the USB 0 port, which we configure as an MUSB peripheral.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Best regards,
Jernej
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v2 7/7] arm64: dts: allwinner: h616: X96 Mate: Add USB nodes
2022-10-31 11:13 ` Andre Przywara
(?)
@ 2022-11-05 21:14 ` Jernej Škrabec
-1 siblings, 0 replies; 48+ messages in thread
From: Jernej Škrabec @ 2022-11-05 21:14 UTC (permalink / raw)
To: Samuel Holland, Chen-Yu Tsai, Kishon Vijay Abraham I, Vinod Koul,
Andre Przywara
Cc: Rob Herring, Krzysztof Kozlowski, Greg Kroah-Hartman, linux-phy,
linux-usb, devicetree, linux-arm-kernel, linux-sunxi,
Karl Kurbjun, Icenowy Zheng
Dne ponedeljek, 31. oktober 2022 ob 12:13:58 CET je Andre Przywara napisal(a):
> The X96 Mate TV box has two USB-A ports, VBUS is always on and connected
> to the DC input.
> Since USB port 0 is connected to an USB-A receptable, we configure it
> as a host port. Using it as a peripheral is dangerous, because VBUS is
> always on.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Best regards,
Jernej
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v2 7/7] arm64: dts: allwinner: h616: X96 Mate: Add USB nodes
@ 2022-11-05 21:14 ` Jernej Škrabec
0 siblings, 0 replies; 48+ messages in thread
From: Jernej Škrabec @ 2022-11-05 21:14 UTC (permalink / raw)
To: Samuel Holland, Chen-Yu Tsai, Kishon Vijay Abraham I, Vinod Koul,
Andre Przywara
Cc: Rob Herring, Krzysztof Kozlowski, Greg Kroah-Hartman, linux-phy,
linux-usb, devicetree, linux-arm-kernel, linux-sunxi,
Karl Kurbjun, Icenowy Zheng
Dne ponedeljek, 31. oktober 2022 ob 12:13:58 CET je Andre Przywara napisal(a):
> The X96 Mate TV box has two USB-A ports, VBUS is always on and connected
> to the DC input.
> Since USB port 0 is connected to an USB-A receptable, we configure it
> as a host port. Using it as a peripheral is dangerous, because VBUS is
> always on.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Best regards,
Jernej
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v2 7/7] arm64: dts: allwinner: h616: X96 Mate: Add USB nodes
@ 2022-11-05 21:14 ` Jernej Škrabec
0 siblings, 0 replies; 48+ messages in thread
From: Jernej Škrabec @ 2022-11-05 21:14 UTC (permalink / raw)
To: Samuel Holland, Chen-Yu Tsai, Kishon Vijay Abraham I, Vinod Koul,
Andre Przywara
Cc: Rob Herring, Krzysztof Kozlowski, Greg Kroah-Hartman, linux-phy,
linux-usb, devicetree, linux-arm-kernel, linux-sunxi,
Karl Kurbjun, Icenowy Zheng
Dne ponedeljek, 31. oktober 2022 ob 12:13:58 CET je Andre Przywara napisal(a):
> The X96 Mate TV box has two USB-A ports, VBUS is always on and connected
> to the DC input.
> Since USB port 0 is connected to an USB-A receptable, we configure it
> as a host port. Using it as a peripheral is dangerous, because VBUS is
> always on.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Best regards,
Jernej
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v2 0/7] arm64: sunxi: h616: Add USB support
2022-10-31 11:13 ` Andre Przywara
(?)
@ 2022-11-07 19:09 ` Jernej Škrabec
-1 siblings, 0 replies; 48+ messages in thread
From: Jernej Škrabec @ 2022-11-07 19:09 UTC (permalink / raw)
To: Samuel Holland, Chen-Yu Tsai, Kishon Vijay Abraham I, Vinod Koul,
Andre Przywara
Cc: Rob Herring, Krzysztof Kozlowski, Greg Kroah-Hartman, linux-phy,
linux-usb, devicetree, linux-arm-kernel, linux-sunxi,
Karl Kurbjun, Icenowy Zheng
Dne ponedeljek, 31. oktober 2022 ob 12:13:51 CET je Andre Przywara napisal(a):
> This is a fixed and rebased update of the previous version, with only
> the DT binding and one DT seeing changes, triggered by Krzysztof's
> comments. For a changelog see below.
> Thanks to Karl for testing this on the OrangePi Zero 2!
>
> ------------------------
> The USB IP used in the Allwinner H616 SoC is very similar to the one
> used in the H3 chip: it contains four USB 2.0 host controllers and four
> PHYs, where the first PHY is shared with a separate USB-OTG controller.
>
> But out of the four ports, only port 2 works out of the box, the other
> ports require some resources and registers of port 2 to be enabled as
> well.
>
> Implement the required workaround in the Allwinner USB PHY driver, and
> key this off the respective compatible string. This core code is
> contained in patch 3/7. The first two patches add the respective DT
> binding documentation, whereas patch 4/7 encodes all the configuration
> options for the H616 USB PHY into the driver.
> The last three patches add the respective devicetree nodes, to the H616
> .dtsi, but also to the DTs of the two supported boards.
>
> This allows USB to be used on any H616 based machine. This was tested on
> the X96 Mate box.
>
> The patches in this series were originally contained in the initial H616
> support series, but where dropped there to speed up mainlining of the
> basic support.
>
> It is now based on v6.1-rc3 and is also available here:
> https://github.com/apritzel/linux/commits/h616-usb-v2
>
> Please have a look and test on your hardware, especically on all ports
> exposed on header pins of the OrangePi Zero2 board.
>
> Cheers,
> Andre
>
> Changelog v1 .. v2:
> - Add Krzysztof's ACK
> - wrap If: clause in allOf: (patch 2/7)
> - limit old (H3) PHYs to 4 clocks (else clause, patch 2/7)
> - change subsystem to phy: in subject (patch 2/7)
> - use "regulator-" prefix for DT node name (patch 6/7)
> - drop unneeded status property in regulator node (patch 6/7)
>
> Andre Przywara (7):
> dt-bindings: usb: Add H616 compatible string
> dt-bindings: phy: Add special clock for Allwinner H616 PHY
> phy: sun4i-usb: Introduce port2 SIDDQ quirk
> phy: sun4i-usb: Add support for the H616 USB PHY
> arm64: dts: allwinner: h616: Add USB nodes
> arm64: dts: allwinner: h616: OrangePi Zero 2: Add USB nodes
> arm64: dts: allwinner: h616: X96 Mate: Add USB nodes
Applied patches 1, 5, 6, 7. Thanks!
Best regards,
Jernej
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v2 0/7] arm64: sunxi: h616: Add USB support
@ 2022-11-07 19:09 ` Jernej Škrabec
0 siblings, 0 replies; 48+ messages in thread
From: Jernej Škrabec @ 2022-11-07 19:09 UTC (permalink / raw)
To: Samuel Holland, Chen-Yu Tsai, Kishon Vijay Abraham I, Vinod Koul,
Andre Przywara
Cc: Rob Herring, Krzysztof Kozlowski, Greg Kroah-Hartman, linux-phy,
linux-usb, devicetree, linux-arm-kernel, linux-sunxi,
Karl Kurbjun, Icenowy Zheng
Dne ponedeljek, 31. oktober 2022 ob 12:13:51 CET je Andre Przywara napisal(a):
> This is a fixed and rebased update of the previous version, with only
> the DT binding and one DT seeing changes, triggered by Krzysztof's
> comments. For a changelog see below.
> Thanks to Karl for testing this on the OrangePi Zero 2!
>
> ------------------------
> The USB IP used in the Allwinner H616 SoC is very similar to the one
> used in the H3 chip: it contains four USB 2.0 host controllers and four
> PHYs, where the first PHY is shared with a separate USB-OTG controller.
>
> But out of the four ports, only port 2 works out of the box, the other
> ports require some resources and registers of port 2 to be enabled as
> well.
>
> Implement the required workaround in the Allwinner USB PHY driver, and
> key this off the respective compatible string. This core code is
> contained in patch 3/7. The first two patches add the respective DT
> binding documentation, whereas patch 4/7 encodes all the configuration
> options for the H616 USB PHY into the driver.
> The last three patches add the respective devicetree nodes, to the H616
> .dtsi, but also to the DTs of the two supported boards.
>
> This allows USB to be used on any H616 based machine. This was tested on
> the X96 Mate box.
>
> The patches in this series were originally contained in the initial H616
> support series, but where dropped there to speed up mainlining of the
> basic support.
>
> It is now based on v6.1-rc3 and is also available here:
> https://github.com/apritzel/linux/commits/h616-usb-v2
>
> Please have a look and test on your hardware, especically on all ports
> exposed on header pins of the OrangePi Zero2 board.
>
> Cheers,
> Andre
>
> Changelog v1 .. v2:
> - Add Krzysztof's ACK
> - wrap If: clause in allOf: (patch 2/7)
> - limit old (H3) PHYs to 4 clocks (else clause, patch 2/7)
> - change subsystem to phy: in subject (patch 2/7)
> - use "regulator-" prefix for DT node name (patch 6/7)
> - drop unneeded status property in regulator node (patch 6/7)
>
> Andre Przywara (7):
> dt-bindings: usb: Add H616 compatible string
> dt-bindings: phy: Add special clock for Allwinner H616 PHY
> phy: sun4i-usb: Introduce port2 SIDDQ quirk
> phy: sun4i-usb: Add support for the H616 USB PHY
> arm64: dts: allwinner: h616: Add USB nodes
> arm64: dts: allwinner: h616: OrangePi Zero 2: Add USB nodes
> arm64: dts: allwinner: h616: X96 Mate: Add USB nodes
Applied patches 1, 5, 6, 7. Thanks!
Best regards,
Jernej
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v2 0/7] arm64: sunxi: h616: Add USB support
@ 2022-11-07 19:09 ` Jernej Škrabec
0 siblings, 0 replies; 48+ messages in thread
From: Jernej Škrabec @ 2022-11-07 19:09 UTC (permalink / raw)
To: Samuel Holland, Chen-Yu Tsai, Kishon Vijay Abraham I, Vinod Koul,
Andre Przywara
Cc: Rob Herring, Krzysztof Kozlowski, Greg Kroah-Hartman, linux-phy,
linux-usb, devicetree, linux-arm-kernel, linux-sunxi,
Karl Kurbjun, Icenowy Zheng
Dne ponedeljek, 31. oktober 2022 ob 12:13:51 CET je Andre Przywara napisal(a):
> This is a fixed and rebased update of the previous version, with only
> the DT binding and one DT seeing changes, triggered by Krzysztof's
> comments. For a changelog see below.
> Thanks to Karl for testing this on the OrangePi Zero 2!
>
> ------------------------
> The USB IP used in the Allwinner H616 SoC is very similar to the one
> used in the H3 chip: it contains four USB 2.0 host controllers and four
> PHYs, where the first PHY is shared with a separate USB-OTG controller.
>
> But out of the four ports, only port 2 works out of the box, the other
> ports require some resources and registers of port 2 to be enabled as
> well.
>
> Implement the required workaround in the Allwinner USB PHY driver, and
> key this off the respective compatible string. This core code is
> contained in patch 3/7. The first two patches add the respective DT
> binding documentation, whereas patch 4/7 encodes all the configuration
> options for the H616 USB PHY into the driver.
> The last three patches add the respective devicetree nodes, to the H616
> .dtsi, but also to the DTs of the two supported boards.
>
> This allows USB to be used on any H616 based machine. This was tested on
> the X96 Mate box.
>
> The patches in this series were originally contained in the initial H616
> support series, but where dropped there to speed up mainlining of the
> basic support.
>
> It is now based on v6.1-rc3 and is also available here:
> https://github.com/apritzel/linux/commits/h616-usb-v2
>
> Please have a look and test on your hardware, especically on all ports
> exposed on header pins of the OrangePi Zero2 board.
>
> Cheers,
> Andre
>
> Changelog v1 .. v2:
> - Add Krzysztof's ACK
> - wrap If: clause in allOf: (patch 2/7)
> - limit old (H3) PHYs to 4 clocks (else clause, patch 2/7)
> - change subsystem to phy: in subject (patch 2/7)
> - use "regulator-" prefix for DT node name (patch 6/7)
> - drop unneeded status property in regulator node (patch 6/7)
>
> Andre Przywara (7):
> dt-bindings: usb: Add H616 compatible string
> dt-bindings: phy: Add special clock for Allwinner H616 PHY
> phy: sun4i-usb: Introduce port2 SIDDQ quirk
> phy: sun4i-usb: Add support for the H616 USB PHY
> arm64: dts: allwinner: h616: Add USB nodes
> arm64: dts: allwinner: h616: OrangePi Zero 2: Add USB nodes
> arm64: dts: allwinner: h616: X96 Mate: Add USB nodes
Applied patches 1, 5, 6, 7. Thanks!
Best regards,
Jernej
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
end of thread, other threads:[~2022-11-07 19:12 UTC | newest]
Thread overview: 48+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-10-31 11:13 [PATCH v2 0/7] arm64: sunxi: h616: Add USB support Andre Przywara
2022-10-31 11:13 ` Andre Przywara
2022-10-31 11:13 ` Andre Przywara
2022-10-31 11:13 ` [PATCH v2 1/7] dt-bindings: usb: Add H616 compatible string Andre Przywara
2022-10-31 11:13 ` Andre Przywara
2022-10-31 11:13 ` Andre Przywara
2022-10-31 11:13 ` [PATCH v2 2/7] dt-bindings: phy: Add special clock for Allwinner H616 PHY Andre Przywara
2022-10-31 11:13 ` Andre Przywara
2022-10-31 11:13 ` Andre Przywara
2022-11-01 1:03 ` Rob Herring
2022-11-01 1:03 ` Rob Herring
2022-11-01 1:03 ` Rob Herring
2022-11-05 7:45 ` Vinod Koul
2022-11-05 7:45 ` Vinod Koul
2022-11-05 7:45 ` Vinod Koul
2022-10-31 11:13 ` [PATCH v2 3/7] phy: sun4i-usb: Introduce port2 SIDDQ quirk Andre Przywara
2022-10-31 11:13 ` Andre Przywara
2022-10-31 11:13 ` Andre Przywara
2022-11-05 7:46 ` Vinod Koul
2022-11-05 7:46 ` Vinod Koul
2022-11-05 7:46 ` Vinod Koul
2022-10-31 11:13 ` [PATCH v2 4/7] phy: sun4i-usb: Add support for the H616 USB PHY Andre Przywara
2022-10-31 11:13 ` Andre Przywara
2022-10-31 11:13 ` Andre Przywara
2022-11-05 7:46 ` Vinod Koul
2022-11-05 7:46 ` Vinod Koul
2022-11-05 7:46 ` Vinod Koul
2022-10-31 11:13 ` [PATCH v2 5/7] arm64: dts: allwinner: h616: Add USB nodes Andre Przywara
2022-10-31 11:13 ` Andre Przywara
2022-10-31 11:13 ` Andre Przywara
2022-11-05 21:07 ` Jernej Škrabec
2022-11-05 21:07 ` Jernej Škrabec
2022-11-05 21:07 ` Jernej Škrabec
2022-10-31 11:13 ` [PATCH v2 6/7] arm64: dts: allwinner: h616: OrangePi Zero 2: " Andre Przywara
2022-10-31 11:13 ` Andre Przywara
2022-10-31 11:13 ` Andre Przywara
2022-11-05 21:13 ` Jernej Škrabec
2022-11-05 21:13 ` Jernej Škrabec
2022-11-05 21:13 ` Jernej Škrabec
2022-10-31 11:13 ` [PATCH v2 7/7] arm64: dts: allwinner: h616: X96 Mate: " Andre Przywara
2022-10-31 11:13 ` Andre Przywara
2022-10-31 11:13 ` Andre Przywara
2022-11-05 21:14 ` Jernej Škrabec
2022-11-05 21:14 ` Jernej Škrabec
2022-11-05 21:14 ` Jernej Škrabec
2022-11-07 19:09 ` [PATCH v2 0/7] arm64: sunxi: h616: Add USB support Jernej Škrabec
2022-11-07 19:09 ` Jernej Škrabec
2022-11-07 19:09 ` Jernej Škrabec
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