[PATCH 0/9] ARM: dts: suniv: F1C100s: add more peripherals

[PATCH 0/9] ARM: dts: suniv: F1C100s: add more peripherals

[Andre Przywara]

The Allwinner F1C100s series of SoCs shares many peripherals with other
Allwinner SoCs. Since they are compatible, we can use the existing
drivers, and just need to enable the devices in the DT.

This series adds the I2C controllers, the PWM device, the CIR (infrared)
device and the LRADC (aka. KEYADC, low res ADC) to the F1C100s .dtsi, so
boards can just use them by setting 'status = "okay";'.

The only thing missing driver-wise is the IR mod clock, which was not
modeled in our CCU driver. Patch 5/9 fixes that.

For every device there is one patch that adds the new compatible string
to the DT binding, and another patch to add the DT node.

This has been tested with a Lctech Pi F1C200s board, by:
- Connecting an LED to PE6, and configuring this as the PWM pin in the DT.
  Doing a sweep on /sys/class/pwm/pwm1/duty_cycle made the LED fade out.
- Configuring PD0/PD12 as I2C0, and letting i2c-detect find the on-board
  NS2009 I2C chip.
- Connecting two resistors to the "ADC" pin, and configuring them as two
  buttons in the DT. /dev/input/event0 properly reported button presses.
- Connecting an infrared receiver to PE11, configured as CIR.
  ir-keytable reported key presses on a remote control.

All those (basic) tests were successful, and prove that the peripherals
do work and are compatible.

Please have a look and test on your hardware, if possible.

Cheers,
Andre

Andre Przywara (9):
  dt-bindings: pwm: allwinner,sun4i-a10: Add F1C100s compatible
  ARM: dts: suniv: f1c100s: add PWM node
  dt-bindings: i2c: mv64xxx: Add F1C100s compatible string
  ARM: dts: suniv: f1c100s: add I2C DT nodes
  clk: sunxi-ng: f1c100s: Add IR mod clock
  dt-bindings: media: IR: Add F1C100s IR compatible string
  ARM: dts: suniv: f1c100s: add CIR DT node
  dt-bindings: input: sun4i-lradc-keys: Add F1C100s compatible
  ARM: dts: suniv: f1c100s: add LRADC node

 .../bindings/i2c/marvell,mv64xxx-i2c.yaml     |  1 +
 .../input/allwinner,sun4i-a10-lradc-keys.yaml |  4 +-
 .../media/allwinner,sun4i-a10-ir.yaml         |  1 +
 .../bindings/pwm/allwinner,sun4i-a10-pwm.yaml |  4 +-
 arch/arm/boot/dts/suniv-f1c100s.dtsi          | 78 +++++++++++++++++++
 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c      | 11 ++-
 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h      |  2 +-
 include/dt-bindings/clock/suniv-ccu-f1c100s.h |  2 +
 8 files changed, 99 insertions(+), 4 deletions(-)

-- 
2.25.1

[PATCH 0/9] ARM: dts: suniv: F1C100s: add more peripherals

[Andre Przywara]

The Allwinner F1C100s series of SoCs shares many peripherals with other
Allwinner SoCs. Since they are compatible, we can use the existing
drivers, and just need to enable the devices in the DT.

This series adds the I2C controllers, the PWM device, the CIR (infrared)
device and the LRADC (aka. KEYADC, low res ADC) to the F1C100s .dtsi, so
boards can just use them by setting 'status = "okay";'.

The only thing missing driver-wise is the IR mod clock, which was not
modeled in our CCU driver. Patch 5/9 fixes that.

For every device there is one patch that adds the new compatible string
to the DT binding, and another patch to add the DT node.

This has been tested with a Lctech Pi F1C200s board, by:
- Connecting an LED to PE6, and configuring this as the PWM pin in the DT.
  Doing a sweep on /sys/class/pwm/pwm1/duty_cycle made the LED fade out.
- Configuring PD0/PD12 as I2C0, and letting i2c-detect find the on-board
  NS2009 I2C chip.
- Connecting two resistors to the "ADC" pin, and configuring them as two
  buttons in the DT. /dev/input/event0 properly reported button presses.
- Connecting an infrared receiver to PE11, configured as CIR.
  ir-keytable reported key presses on a remote control.

All those (basic) tests were successful, and prove that the peripherals
do work and are compatible.

Please have a look and test on your hardware, if possible.

Cheers,
Andre

Andre Przywara (9):
  dt-bindings: pwm: allwinner,sun4i-a10: Add F1C100s compatible
  ARM: dts: suniv: f1c100s: add PWM node
  dt-bindings: i2c: mv64xxx: Add F1C100s compatible string
  ARM: dts: suniv: f1c100s: add I2C DT nodes
  clk: sunxi-ng: f1c100s: Add IR mod clock
  dt-bindings: media: IR: Add F1C100s IR compatible string
  ARM: dts: suniv: f1c100s: add CIR DT node
  dt-bindings: input: sun4i-lradc-keys: Add F1C100s compatible
  ARM: dts: suniv: f1c100s: add LRADC node

 .../bindings/i2c/marvell,mv64xxx-i2c.yaml     |  1 +
 .../input/allwinner,sun4i-a10-lradc-keys.yaml |  4 +-
 .../media/allwinner,sun4i-a10-ir.yaml         |  1 +
 .../bindings/pwm/allwinner,sun4i-a10-pwm.yaml |  4 +-
 arch/arm/boot/dts/suniv-f1c100s.dtsi          | 78 +++++++++++++++++++
 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c      | 11 ++-
 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h      |  2 +-
 include/dt-bindings/clock/suniv-ccu-f1c100s.h |  2 +
 8 files changed, 99 insertions(+), 4 deletions(-)

-- 
2.25.1


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[PATCH 1/9] dt-bindings: pwm: allwinner,sun4i-a10: Add F1C100s compatible

[Andre Przywara]

The PWM controller in the Allwinner F1C100s series of SoCs is the same
as in the A20 SoCs, so allow using that as the fallback name.

Join the V3s compatible string in an enum on the way.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 .../devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml      | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml
index 4cc3cc7c50bec..66e400f2a3a4f 100644
--- a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml
+++ b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml
@@ -25,7 +25,9 @@ properties:
           - const: allwinner,sun8i-a83t-pwm
           - const: allwinner,sun8i-h3-pwm
       - items:
-          - const: allwinner,sun8i-v3s-pwm
+          - enum:
+              - allwinner,suniv-f1c100s-pwm
+              - allwinner,sun8i-v3s-pwm
           - const: allwinner,sun7i-a20-pwm
       - items:
           - const: allwinner,sun50i-a64-pwm
-- 
2.25.1

[PATCH 1/9] dt-bindings: pwm: allwinner,sun4i-a10: Add F1C100s compatible

[Andre Przywara]

The PWM controller in the Allwinner F1C100s series of SoCs is the same
as in the A20 SoCs, so allow using that as the fallback name.

Join the V3s compatible string in an enum on the way.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 .../devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml      | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml
index 4cc3cc7c50bec..66e400f2a3a4f 100644
--- a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml
+++ b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml
@@ -25,7 +25,9 @@ properties:
           - const: allwinner,sun8i-a83t-pwm
           - const: allwinner,sun8i-h3-pwm
       - items:
-          - const: allwinner,sun8i-v3s-pwm
+          - enum:
+              - allwinner,suniv-f1c100s-pwm
+              - allwinner,sun8i-v3s-pwm
           - const: allwinner,sun7i-a20-pwm
       - items:
           - const: allwinner,sun50i-a64-pwm
-- 
2.25.1


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[PATCH 2/9] ARM: dts: suniv: f1c100s: add PWM node

[Andre Przywara]

The Allwinner F1C100s family of SoCs contain a PWM controller compatible
to the one used in the A20 chip.
Add the DT node so that any users can simply enable it in their board
DT.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm/boot/dts/suniv-f1c100s.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
index 0edc1724407b3..d5a6324e76465 100644
--- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
+++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
@@ -192,6 +192,15 @@ wdt: watchdog@1c20ca0 {
 			clocks = <&osc32k>;
 		};
 
+		pwm: pwm@1c21000 {
+			compatible = "allwinner,suniv-f1c100s-pwm",
+				     "allwinner,sun7i-a20-pwm";
+			reg = <0x01c21000 0xc>;
+			clocks = <&osc24M>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
+
 		uart0: serial@1c25000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x01c25000 0x400>;
-- 
2.25.1

[PATCH 2/9] ARM: dts: suniv: f1c100s: add PWM node

[Andre Przywara]

The Allwinner F1C100s family of SoCs contain a PWM controller compatible
to the one used in the A20 chip.
Add the DT node so that any users can simply enable it in their board
DT.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm/boot/dts/suniv-f1c100s.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
index 0edc1724407b3..d5a6324e76465 100644
--- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
+++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
@@ -192,6 +192,15 @@ wdt: watchdog@1c20ca0 {
 			clocks = <&osc32k>;
 		};
 
+		pwm: pwm@1c21000 {
+			compatible = "allwinner,suniv-f1c100s-pwm",
+				     "allwinner,sun7i-a20-pwm";
+			reg = <0x01c21000 0xc>;
+			clocks = <&osc24M>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
+
 		uart0: serial@1c25000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x01c25000 0x400>;
-- 
2.25.1


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[PATCH 3/9] dt-bindings: i2c: mv64xxx: Add F1C100s compatible string

[Andre Przywara]

The I2C controller IP used in the Allwinner F1C100s series of SoCs is
compatible with the ones used in the other Allwinner SoCs.

Add an F1C100s specific compatible string to the list of existing names.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml b/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml
index 93c164aa00daf..984fc1ed3ec6a 100644
--- a/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml
+++ b/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml
@@ -19,6 +19,7 @@ properties:
       - const: allwinner,sun6i-a31-i2c
       - items:
           - enum:
+              - allwinner,suniv-f1c100s-i2c
               - allwinner,sun8i-a23-i2c
               - allwinner,sun8i-a83t-i2c
               - allwinner,sun8i-v536-i2c
-- 
2.25.1

[PATCH 3/9] dt-bindings: i2c: mv64xxx: Add F1C100s compatible string

[Andre Przywara]

The I2C controller IP used in the Allwinner F1C100s series of SoCs is
compatible with the ones used in the other Allwinner SoCs.

Add an F1C100s specific compatible string to the list of existing names.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml b/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml
index 93c164aa00daf..984fc1ed3ec6a 100644
--- a/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml
+++ b/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml
@@ -19,6 +19,7 @@ properties:
       - const: allwinner,sun6i-a31-i2c
       - items:
           - enum:
+              - allwinner,suniv-f1c100s-i2c
               - allwinner,sun8i-a23-i2c
               - allwinner,sun8i-a83t-i2c
               - allwinner,sun8i-v536-i2c
-- 
2.25.1


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[PATCH 4/9] ARM: dts: suniv: f1c100s: add I2C DT nodes

[Andre Przywara]

The Allwinner F1C100s series of SoCs contain three I2C controllers
compatible to the ones used in other Allwinner SoCs.

Add the DT nodes describing the resources of the controllers.
I2C1 has only one possible pinmux, so add the pinctrl properties for
that already.
At least one board connects an on-board I2C chip to PD0/PD12 (I2C0), so
include those pins already, to simplify referencing them later.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm/boot/dts/suniv-f1c100s.dtsi | 50 ++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)

diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
index d5a6324e76465..2901c586971b4 100644
--- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
+++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
@@ -166,6 +166,18 @@ mmc0_pins: mmc0-pins {
 				drive-strength = <30>;
 			};
 
+			/omit-if-no-ref/
+			i2c0_pd_pins: i2c0-pd-pins {
+				pins = "PD0", "PD12";
+				function = "i2c0";
+			};
+
+			/omit-if-no-ref/
+			i2c1_pins: i2c1-pins {
+				pins = "PD5", "PD6";
+				function = "i2c1";
+			};
+
 			spi0_pc_pins: spi0-pc-pins {
 				pins = "PC0", "PC1", "PC2", "PC3";
 				function = "spi0";
@@ -177,6 +189,44 @@ uart0_pe_pins: uart0-pe-pins {
 			};
 		};
 
+		i2c0: i2c@1c27000 {
+			compatible = "allwinner,suniv-f1c100s-i2c",
+				     "allwinner,sun6i-a31-i2c";
+			reg = <0x01c27000 0x400>;
+			interrupts = <7>;
+			clocks = <&ccu CLK_BUS_I2C0>;
+			resets = <&ccu RST_BUS_I2C0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@1c27400 {
+			compatible = "allwinner,suniv-f1c100s-i2c",
+				     "allwinner,sun6i-a31-i2c";
+			reg = <0x01c27400 0x400>;
+			interrupts = <8>;
+			clocks = <&ccu CLK_BUS_I2C1>;
+			resets = <&ccu RST_BUS_I2C1>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c1_pins>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c2: i2c@1c27800 {
+			compatible = "allwinner,suniv-f1c100s-i2c",
+				     "allwinner,sun6i-a31-i2c";
+			reg = <0x01c27800 0x400>;
+			interrupts = <9>;
+			clocks = <&ccu CLK_BUS_I2C2>;
+			resets = <&ccu RST_BUS_I2C2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		timer@1c20c00 {
 			compatible = "allwinner,suniv-f1c100s-timer";
 			reg = <0x01c20c00 0x90>;
-- 
2.25.1

[PATCH 4/9] ARM: dts: suniv: f1c100s: add I2C DT nodes

[Andre Przywara]

The Allwinner F1C100s series of SoCs contain three I2C controllers
compatible to the ones used in other Allwinner SoCs.

Add the DT nodes describing the resources of the controllers.
I2C1 has only one possible pinmux, so add the pinctrl properties for
that already.
At least one board connects an on-board I2C chip to PD0/PD12 (I2C0), so
include those pins already, to simplify referencing them later.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm/boot/dts/suniv-f1c100s.dtsi | 50 ++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)

diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
index d5a6324e76465..2901c586971b4 100644
--- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
+++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
@@ -166,6 +166,18 @@ mmc0_pins: mmc0-pins {
 				drive-strength = <30>;
 			};
 
+			/omit-if-no-ref/
+			i2c0_pd_pins: i2c0-pd-pins {
+				pins = "PD0", "PD12";
+				function = "i2c0";
+			};
+
+			/omit-if-no-ref/
+			i2c1_pins: i2c1-pins {
+				pins = "PD5", "PD6";
+				function = "i2c1";
+			};
+
 			spi0_pc_pins: spi0-pc-pins {
 				pins = "PC0", "PC1", "PC2", "PC3";
 				function = "spi0";
@@ -177,6 +189,44 @@ uart0_pe_pins: uart0-pe-pins {
 			};
 		};
 
+		i2c0: i2c@1c27000 {
+			compatible = "allwinner,suniv-f1c100s-i2c",
+				     "allwinner,sun6i-a31-i2c";
+			reg = <0x01c27000 0x400>;
+			interrupts = <7>;
+			clocks = <&ccu CLK_BUS_I2C0>;
+			resets = <&ccu RST_BUS_I2C0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@1c27400 {
+			compatible = "allwinner,suniv-f1c100s-i2c",
+				     "allwinner,sun6i-a31-i2c";
+			reg = <0x01c27400 0x400>;
+			interrupts = <8>;
+			clocks = <&ccu CLK_BUS_I2C1>;
+			resets = <&ccu RST_BUS_I2C1>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c1_pins>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c2: i2c@1c27800 {
+			compatible = "allwinner,suniv-f1c100s-i2c",
+				     "allwinner,sun6i-a31-i2c";
+			reg = <0x01c27800 0x400>;
+			interrupts = <9>;
+			clocks = <&ccu CLK_BUS_I2C2>;
+			resets = <&ccu RST_BUS_I2C2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		timer@1c20c00 {
 			compatible = "allwinner,suniv-f1c100s-timer";
 			reg = <0x01c20c00 0x90>;
-- 
2.25.1


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[PATCH 5/9] clk: sunxi-ng: f1c100s: Add IR mod clock

[Andre Przywara]

For some reason the mod clock for the Allwinner F1C100s CIR (infrared
receiver) peripheral was not modeled in the CCU driver.

Add the clock description to the list, and wire it up in the clock list.
By assigning a new clock ID at the end, it extends the number of clocks.

This allows to use the CIR peripheral on any F1C100s series board.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c      | 11 ++++++++++-
 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h      |  2 +-
 include/dt-bindings/clock/suniv-ccu-f1c100s.h |  2 ++
 3 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
index ed097c4f780ff..af4811e720b39 100644
--- a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
+++ b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
@@ -239,7 +239,14 @@ static SUNXI_CCU_MUX_WITH_GATE(i2s_clk, "i2s", i2s_spdif_parents,
 static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", i2s_spdif_parents,
 			       0x0b4, 16, 2, BIT(31), 0);
 
-/* The BSP header file has a CIR_CFG, but no mod clock uses this definition */
+static const char * const ir_parents[] = { "osc32k", "osc24M" };
+static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir",
+				  ir_parents, 0x0b8,
+				  0, 4,		/* M */
+				  16, 2,	/* P */
+				  24, 1,        /* mux */
+				  BIT(31),      /* gate */
+				  0);
 
 static SUNXI_CCU_GATE(usb_phy0_clk,	"usb-phy0",	"osc24M",
 		      0x0cc, BIT(1), 0);
@@ -355,6 +362,7 @@ static struct ccu_common *suniv_ccu_clks[] = {
 	&mmc1_output_clk.common,
 	&i2s_clk.common,
 	&spdif_clk.common,
+	&ir_clk.common,
 	&usb_phy0_clk.common,
 	&dram_ve_clk.common,
 	&dram_csi_clk.common,
@@ -446,6 +454,7 @@ static struct clk_hw_onecell_data suniv_hw_clks = {
 		[CLK_MMC1_OUTPUT]	= &mmc1_output_clk.common.hw,
 		[CLK_I2S]		= &i2s_clk.common.hw,
 		[CLK_SPDIF]		= &spdif_clk.common.hw,
+		[CLK_IR]		= &ir_clk.common.hw,
 		[CLK_USB_PHY0]		= &usb_phy0_clk.common.hw,
 		[CLK_DRAM_VE]		= &dram_ve_clk.common.hw,
 		[CLK_DRAM_CSI]		= &dram_csi_clk.common.hw,
diff --git a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h
index b22484f1bb9a5..d56a4316289d8 100644
--- a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h
+++ b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h
@@ -29,6 +29,6 @@
 
 /* All bus gates, DRAM gates and mod clocks are exported */
 
-#define CLK_NUMBER		(CLK_AVS + 1)
+#define CLK_NUMBER		(CLK_IR + 1)
 
 #endif /* _CCU_SUNIV_F1C100S_H_ */
diff --git a/include/dt-bindings/clock/suniv-ccu-f1c100s.h b/include/dt-bindings/clock/suniv-ccu-f1c100s.h
index f5ac155c9c70a..d7570765f424d 100644
--- a/include/dt-bindings/clock/suniv-ccu-f1c100s.h
+++ b/include/dt-bindings/clock/suniv-ccu-f1c100s.h
@@ -67,4 +67,6 @@
 #define CLK_CODEC		65
 #define CLK_AVS			66
 
+#define CLK_IR			67
+
 #endif
-- 
2.25.1

[PATCH 5/9] clk: sunxi-ng: f1c100s: Add IR mod clock

[Andre Przywara]

For some reason the mod clock for the Allwinner F1C100s CIR (infrared
receiver) peripheral was not modeled in the CCU driver.

Add the clock description to the list, and wire it up in the clock list.
By assigning a new clock ID at the end, it extends the number of clocks.

This allows to use the CIR peripheral on any F1C100s series board.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c      | 11 ++++++++++-
 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h      |  2 +-
 include/dt-bindings/clock/suniv-ccu-f1c100s.h |  2 ++
 3 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
index ed097c4f780ff..af4811e720b39 100644
--- a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
+++ b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
@@ -239,7 +239,14 @@ static SUNXI_CCU_MUX_WITH_GATE(i2s_clk, "i2s", i2s_spdif_parents,
 static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", i2s_spdif_parents,
 			       0x0b4, 16, 2, BIT(31), 0);
 
-/* The BSP header file has a CIR_CFG, but no mod clock uses this definition */
+static const char * const ir_parents[] = { "osc32k", "osc24M" };
+static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir",
+				  ir_parents, 0x0b8,
+				  0, 4,		/* M */
+				  16, 2,	/* P */
+				  24, 1,        /* mux */
+				  BIT(31),      /* gate */
+				  0);
 
 static SUNXI_CCU_GATE(usb_phy0_clk,	"usb-phy0",	"osc24M",
 		      0x0cc, BIT(1), 0);
@@ -355,6 +362,7 @@ static struct ccu_common *suniv_ccu_clks[] = {
 	&mmc1_output_clk.common,
 	&i2s_clk.common,
 	&spdif_clk.common,
+	&ir_clk.common,
 	&usb_phy0_clk.common,
 	&dram_ve_clk.common,
 	&dram_csi_clk.common,
@@ -446,6 +454,7 @@ static struct clk_hw_onecell_data suniv_hw_clks = {
 		[CLK_MMC1_OUTPUT]	= &mmc1_output_clk.common.hw,
 		[CLK_I2S]		= &i2s_clk.common.hw,
 		[CLK_SPDIF]		= &spdif_clk.common.hw,
+		[CLK_IR]		= &ir_clk.common.hw,
 		[CLK_USB_PHY0]		= &usb_phy0_clk.common.hw,
 		[CLK_DRAM_VE]		= &dram_ve_clk.common.hw,
 		[CLK_DRAM_CSI]		= &dram_csi_clk.common.hw,
diff --git a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h
index b22484f1bb9a5..d56a4316289d8 100644
--- a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h
+++ b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h
@@ -29,6 +29,6 @@
 
 /* All bus gates, DRAM gates and mod clocks are exported */
 
-#define CLK_NUMBER		(CLK_AVS + 1)
+#define CLK_NUMBER		(CLK_IR + 1)
 
 #endif /* _CCU_SUNIV_F1C100S_H_ */
diff --git a/include/dt-bindings/clock/suniv-ccu-f1c100s.h b/include/dt-bindings/clock/suniv-ccu-f1c100s.h
index f5ac155c9c70a..d7570765f424d 100644
--- a/include/dt-bindings/clock/suniv-ccu-f1c100s.h
+++ b/include/dt-bindings/clock/suniv-ccu-f1c100s.h
@@ -67,4 +67,6 @@
 #define CLK_CODEC		65
 #define CLK_AVS			66
 
+#define CLK_IR			67
+
 #endif
-- 
2.25.1


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[PATCH 6/9] dt-bindings: media: IR: Add F1C100s IR compatible string

[Andre Przywara]

The CIR controller in the Allwinner F1C100s series of SoCs is compatible
to the ones used in other Allwinner SoCs.

Add the respective compatible name to the existing IR binding, and pair
it with the A31 fallback compatible string.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 .../devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml        | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml b/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml
index 704033e21ee80..53945c61325c7 100644
--- a/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml
+++ b/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml
@@ -21,6 +21,7 @@ properties:
       - const: allwinner,sun6i-a31-ir
       - items:
           - enum:
+              - allwinner,suniv-f1c100s-ir
               - allwinner,sun8i-a83t-ir
               - allwinner,sun8i-r40-ir
               - allwinner,sun50i-a64-ir
-- 
2.25.1

[PATCH 6/9] dt-bindings: media: IR: Add F1C100s IR compatible string

[Andre Przywara]

The CIR controller in the Allwinner F1C100s series of SoCs is compatible
to the ones used in other Allwinner SoCs.

Add the respective compatible name to the existing IR binding, and pair
it with the A31 fallback compatible string.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 .../devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml        | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml b/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml
index 704033e21ee80..53945c61325c7 100644
--- a/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml
+++ b/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml
@@ -21,6 +21,7 @@ properties:
       - const: allwinner,sun6i-a31-ir
       - items:
           - enum:
+              - allwinner,suniv-f1c100s-ir
               - allwinner,sun8i-a83t-ir
               - allwinner,sun8i-r40-ir
               - allwinner,sun50i-a64-ir
-- 
2.25.1


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[PATCH 7/9] ARM: dts: suniv: f1c100s: add CIR DT node

[Andre Przywara]

The CIR (infrared receiver) controller in the Allwinner F1C100s series
of SoCs is compatible to the ones used in other Allwinner SoCs.

Add the DT node describing the resources of the controller.
There are multiple possible pinmuxes, but none as them seem to be an
obvious choice, so refrain from adding any pincontroller subnodes for
now.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm/boot/dts/suniv-f1c100s.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
index 2901c586971b4..d29b48f23b89a 100644
--- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
+++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
@@ -251,6 +251,17 @@ pwm: pwm@1c21000 {
 			status = "disabled";
 		};
 
+		ir: ir@1c22c00 {
+			compatible = "allwinner,suniv-f1c100s-ir",
+				     "allwinner,sun6i-a31-ir";
+			reg = <0x01c22c00 0x400>;
+			clocks = <&ccu CLK_BUS_IR>, <&ccu CLK_IR>;
+			clock-names = "apb", "ir";
+			resets = <&ccu RST_BUS_IR>;
+			interrupts = <6>;
+			status = "disabled";
+		};
+
 		uart0: serial@1c25000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x01c25000 0x400>;
-- 
2.25.1

[PATCH 7/9] ARM: dts: suniv: f1c100s: add CIR DT node

[Andre Przywara]

The CIR (infrared receiver) controller in the Allwinner F1C100s series
of SoCs is compatible to the ones used in other Allwinner SoCs.

Add the DT node describing the resources of the controller.
There are multiple possible pinmuxes, but none as them seem to be an
obvious choice, so refrain from adding any pincontroller subnodes for
now.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm/boot/dts/suniv-f1c100s.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
index 2901c586971b4..d29b48f23b89a 100644
--- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
+++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
@@ -251,6 +251,17 @@ pwm: pwm@1c21000 {
 			status = "disabled";
 		};
 
+		ir: ir@1c22c00 {
+			compatible = "allwinner,suniv-f1c100s-ir",
+				     "allwinner,sun6i-a31-ir";
+			reg = <0x01c22c00 0x400>;
+			clocks = <&ccu CLK_BUS_IR>, <&ccu CLK_IR>;
+			clock-names = "apb", "ir";
+			resets = <&ccu RST_BUS_IR>;
+			interrupts = <6>;
+			status = "disabled";
+		};
+
 		uart0: serial@1c25000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x01c25000 0x400>;
-- 
2.25.1


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[PATCH 8/9] dt-bindings: input: sun4i-lradc-keys: Add F1C100s compatible

[Andre Przywara]

The Allwinner F1C100s series of SoCs contain a LRADC (aka. KEYADC)
compatible to the version in other SoCs.
The manual doesn't mention the ratio of the input voltage that is used,
but comparing actual measurements with the values in the register
suggests that it is 3/4 of Vref.

Add an F1C100s compatible string to the list, and pair it with the
A83T fallback. Since the A64 is the same, combined both using an enum.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 .../bindings/input/allwinner,sun4i-a10-lradc-keys.yaml        | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/input/allwinner,sun4i-a10-lradc-keys.yaml b/Documentation/devicetree/bindings/input/allwinner,sun4i-a10-lradc-keys.yaml
index 5d631f7137e78..5efceb3138791 100644
--- a/Documentation/devicetree/bindings/input/allwinner,sun4i-a10-lradc-keys.yaml
+++ b/Documentation/devicetree/bindings/input/allwinner,sun4i-a10-lradc-keys.yaml
@@ -16,7 +16,9 @@ properties:
       - const: allwinner,sun4i-a10-lradc-keys
       - const: allwinner,sun8i-a83t-r-lradc
       - items:
-          - const: allwinner,sun50i-a64-lradc
+          - enum:
+              - allwinner,suniv-f1c100s-lradc
+              - allwinner,sun50i-a64-lradc
           - const: allwinner,sun8i-a83t-r-lradc
       - const: allwinner,sun50i-r329-lradc
       - items:
-- 
2.25.1

[PATCH 8/9] dt-bindings: input: sun4i-lradc-keys: Add F1C100s compatible

[Andre Przywara]

The Allwinner F1C100s series of SoCs contain a LRADC (aka. KEYADC)
compatible to the version in other SoCs.
The manual doesn't mention the ratio of the input voltage that is used,
but comparing actual measurements with the values in the register
suggests that it is 3/4 of Vref.

Add an F1C100s compatible string to the list, and pair it with the
A83T fallback. Since the A64 is the same, combined both using an enum.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 .../bindings/input/allwinner,sun4i-a10-lradc-keys.yaml        | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/input/allwinner,sun4i-a10-lradc-keys.yaml b/Documentation/devicetree/bindings/input/allwinner,sun4i-a10-lradc-keys.yaml
index 5d631f7137e78..5efceb3138791 100644
--- a/Documentation/devicetree/bindings/input/allwinner,sun4i-a10-lradc-keys.yaml
+++ b/Documentation/devicetree/bindings/input/allwinner,sun4i-a10-lradc-keys.yaml
@@ -16,7 +16,9 @@ properties:
       - const: allwinner,sun4i-a10-lradc-keys
       - const: allwinner,sun8i-a83t-r-lradc
       - items:
-          - const: allwinner,sun50i-a64-lradc
+          - enum:
+              - allwinner,suniv-f1c100s-lradc
+              - allwinner,sun50i-a64-lradc
           - const: allwinner,sun8i-a83t-r-lradc
       - const: allwinner,sun50i-r329-lradc
       - items:
-- 
2.25.1


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[PATCH 9/9] ARM: dts: suniv: f1c100s: add LRADC node

[Andre Przywara]

The Allwinner F1C100s series of SoCs contain a LRADC (aka. KEYADC)
compatible to the version in other SoCs.
The manual doesn't mention the ratio of the input voltage that is used,
but comparing actual measurements with the values in the register
suggests that it is 3/4 of Vref.

Add the DT node describing the base address and interrupt. As in the
older SoCs, there is no explicit reset or clock gate, also there is a
dedicated, non-multiplexed pin, so need for more properties.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm/boot/dts/suniv-f1c100s.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
index d29b48f23b89a..03592c8e63fed 100644
--- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
+++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
@@ -262,6 +262,14 @@ ir: ir@1c22c00 {
 			status = "disabled";
 		};
 
+		lradc: lradc@1c23400 {
+			compatible = "allwinner,suniv-f1c100s-lradc",
+				     "allwinner,sun8i-a83t-r-lradc";
+			reg = <0x01c23400 0x100>;
+			interrupts = <22>;
+			status = "disabled";
+		};
+
 		uart0: serial@1c25000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x01c25000 0x400>;
-- 
2.25.1

[PATCH 9/9] ARM: dts: suniv: f1c100s: add LRADC node

[Andre Przywara]

The Allwinner F1C100s series of SoCs contain a LRADC (aka. KEYADC)
compatible to the version in other SoCs.
The manual doesn't mention the ratio of the input voltage that is used,
but comparing actual measurements with the values in the register
suggests that it is 3/4 of Vref.

Add the DT node describing the base address and interrupt. As in the
older SoCs, there is no explicit reset or clock gate, also there is a
dedicated, non-multiplexed pin, so need for more properties.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm/boot/dts/suniv-f1c100s.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
index d29b48f23b89a..03592c8e63fed 100644
--- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
+++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
@@ -262,6 +262,14 @@ ir: ir@1c22c00 {
 			status = "disabled";
 		};
 
+		lradc: lradc@1c23400 {
+			compatible = "allwinner,suniv-f1c100s-lradc",
+				     "allwinner,sun8i-a83t-r-lradc";
+			reg = <0x01c23400 0x100>;
+			interrupts = <22>;
+			status = "disabled";
+		};
+
 		uart0: serial@1c25000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x01c25000 0x400>;
-- 
2.25.1


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Re: [PATCH 1/9] dt-bindings: pwm: allwinner,sun4i-a10: Add F1C100s compatible

[Rob Herring]

On Tue, 01 Nov 2022 14:16:50 +0000, Andre Przywara wrote:
> The PWM controller in the Allwinner F1C100s series of SoCs is the same
> as in the A20 SoCs, so allow using that as the fallback name.
> 
> Join the V3s compatible string in an enum on the way.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
>  .../devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml      | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH 1/9] dt-bindings: pwm: allwinner,sun4i-a10: Add F1C100s compatible

[Rob Herring]

On Tue, 01 Nov 2022 14:16:50 +0000, Andre Przywara wrote:
> The PWM controller in the Allwinner F1C100s series of SoCs is the same
> as in the A20 SoCs, so allow using that as the fallback name.
> 
> Join the V3s compatible string in an enum on the way.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
>  .../devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml      | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 

Acked-by: Rob Herring <robh@kernel.org>

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Re: [PATCH 3/9] dt-bindings: i2c: mv64xxx: Add F1C100s compatible string

[Rob Herring]

On Tue, 01 Nov 2022 14:16:52 +0000, Andre Przywara wrote:
> The I2C controller IP used in the Allwinner F1C100s series of SoCs is
> compatible with the ones used in the other Allwinner SoCs.
> 
> Add an F1C100s specific compatible string to the list of existing names.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
>  Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH 3/9] dt-bindings: i2c: mv64xxx: Add F1C100s compatible string

[Rob Herring]

On Tue, 01 Nov 2022 14:16:52 +0000, Andre Przywara wrote:
> The I2C controller IP used in the Allwinner F1C100s series of SoCs is
> compatible with the ones used in the other Allwinner SoCs.
> 
> Add an F1C100s specific compatible string to the list of existing names.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
>  Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

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Re: [PATCH 6/9] dt-bindings: media: IR: Add F1C100s IR compatible string

[Rob Herring]

On Tue, 01 Nov 2022 14:16:55 +0000, Andre Przywara wrote:
> The CIR controller in the Allwinner F1C100s series of SoCs is compatible
> to the ones used in other Allwinner SoCs.
> 
> Add the respective compatible name to the existing IR binding, and pair
> it with the A31 fallback compatible string.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
>  .../devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml        | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH 6/9] dt-bindings: media: IR: Add F1C100s IR compatible string

[Rob Herring]

On Tue, 01 Nov 2022 14:16:55 +0000, Andre Przywara wrote:
> The CIR controller in the Allwinner F1C100s series of SoCs is compatible
> to the ones used in other Allwinner SoCs.
> 
> Add the respective compatible name to the existing IR binding, and pair
> it with the A31 fallback compatible string.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
>  .../devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml        | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

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Re: [PATCH 8/9] dt-bindings: input: sun4i-lradc-keys: Add F1C100s compatible

[Rob Herring]

On Tue, 01 Nov 2022 14:16:57 +0000, Andre Przywara wrote:
> The Allwinner F1C100s series of SoCs contain a LRADC (aka. KEYADC)
> compatible to the version in other SoCs.
> The manual doesn't mention the ratio of the input voltage that is used,
> but comparing actual measurements with the values in the register
> suggests that it is 3/4 of Vref.
> 
> Add an F1C100s compatible string to the list, and pair it with the
> A83T fallback. Since the A64 is the same, combined both using an enum.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
>  .../bindings/input/allwinner,sun4i-a10-lradc-keys.yaml        | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH 8/9] dt-bindings: input: sun4i-lradc-keys: Add F1C100s compatible

[Rob Herring]

On Tue, 01 Nov 2022 14:16:57 +0000, Andre Przywara wrote:
> The Allwinner F1C100s series of SoCs contain a LRADC (aka. KEYADC)
> compatible to the version in other SoCs.
> The manual doesn't mention the ratio of the input voltage that is used,
> but comparing actual measurements with the values in the register
> suggests that it is 3/4 of Vref.
> 
> Add an F1C100s compatible string to the list, and pair it with the
> A83T fallback. Since the A64 is the same, combined both using an enum.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
>  .../bindings/input/allwinner,sun4i-a10-lradc-keys.yaml        | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 

Acked-by: Rob Herring <robh@kernel.org>

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Re: [PATCH 3/9] dt-bindings: i2c: mv64xxx: Add F1C100s compatible string

[Wolfram Sang]

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On Tue, Nov 01, 2022 at 02:16:52PM +0000, Andre Przywara wrote:
> The I2C controller IP used in the Allwinner F1C100s series of SoCs is
> compatible with the ones used in the other Allwinner SoCs.
> 
> Add an F1C100s specific compatible string to the list of existing names.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Applied to for-next, thanks!


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Re: [PATCH 3/9] dt-bindings: i2c: mv64xxx: Add F1C100s compatible string

[Wolfram Sang]

[-- Attachment #1.1: Type: text/plain, Size: 376 bytes --]

On Tue, Nov 01, 2022 at 02:16:52PM +0000, Andre Przywara wrote:
> The I2C controller IP used in the Allwinner F1C100s series of SoCs is
> compatible with the ones used in the other Allwinner SoCs.
> 
> Add an F1C100s specific compatible string to the list of existing names.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Applied to for-next, thanks!


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Re: [PATCH 8/9] dt-bindings: input: sun4i-lradc-keys: Add F1C100s compatible

[Dmitry Torokhov]

On Tue, Nov 01, 2022 at 02:16:57PM +0000, Andre Przywara wrote:
> The Allwinner F1C100s series of SoCs contain a LRADC (aka. KEYADC)
> compatible to the version in other SoCs.
> The manual doesn't mention the ratio of the input voltage that is used,
> but comparing actual measurements with the values in the register
> suggests that it is 3/4 of Vref.
> 
> Add an F1C100s compatible string to the list, and pair it with the
> A83T fallback. Since the A64 is the same, combined both using an enum.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Applied, thank you.

-- 
Dmitry

Re: [PATCH 8/9] dt-bindings: input: sun4i-lradc-keys: Add F1C100s compatible

[Dmitry Torokhov]

On Tue, Nov 01, 2022 at 02:16:57PM +0000, Andre Przywara wrote:
> The Allwinner F1C100s series of SoCs contain a LRADC (aka. KEYADC)
> compatible to the version in other SoCs.
> The manual doesn't mention the ratio of the input voltage that is used,
> but comparing actual measurements with the values in the register
> suggests that it is 3/4 of Vref.
> 
> Add an F1C100s compatible string to the list, and pair it with the
> A83T fallback. Since the A64 is the same, combined both using an enum.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Applied, thank you.

-- 
Dmitry

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Re: [PATCH 2/9] ARM: dts: suniv: f1c100s: add PWM node

[Jernej Škrabec]

Dne torek, 01. november 2022 ob 15:16:51 CET je Andre Przywara napisal(a):
> The Allwinner F1C100s family of SoCs contain a PWM controller compatible
> to the one used in the A20 chip.
> Add the DT node so that any users can simply enable it in their board
> DT.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
>  arch/arm/boot/dts/suniv-f1c100s.dtsi | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi
> b/arch/arm/boot/dts/suniv-f1c100s.dtsi index 0edc1724407b3..d5a6324e76465
> 100644
> --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
> +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
> @@ -192,6 +192,15 @@ wdt: watchdog@1c20ca0 {
>  			clocks = <&osc32k>;
>  		};
> 
> +		pwm: pwm@1c21000 {
> +			compatible = "allwinner,suniv-f1c100s-pwm",
> +				     "allwinner,sun7i-a20-pwm";
> +			reg = <0x01c21000 0xc>;

According to documentation, size is 0x400.

Best regards,
Jernej

> +			clocks = <&osc24M>;
> +			#pwm-cells = <3>;
> +			status = "disabled";
> +		};
> +
>  		uart0: serial@1c25000 {
>  			compatible = "snps,dw-apb-uart";
>  			reg = <0x01c25000 0x400>;

Re: [PATCH 2/9] ARM: dts: suniv: f1c100s: add PWM node

[Jernej Škrabec]

Dne torek, 01. november 2022 ob 15:16:51 CET je Andre Przywara napisal(a):
> The Allwinner F1C100s family of SoCs contain a PWM controller compatible
> to the one used in the A20 chip.
> Add the DT node so that any users can simply enable it in their board
> DT.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
>  arch/arm/boot/dts/suniv-f1c100s.dtsi | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi
> b/arch/arm/boot/dts/suniv-f1c100s.dtsi index 0edc1724407b3..d5a6324e76465
> 100644
> --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
> +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
> @@ -192,6 +192,15 @@ wdt: watchdog@1c20ca0 {
>  			clocks = <&osc32k>;
>  		};
> 
> +		pwm: pwm@1c21000 {
> +			compatible = "allwinner,suniv-f1c100s-pwm",
> +				     "allwinner,sun7i-a20-pwm";
> +			reg = <0x01c21000 0xc>;

According to documentation, size is 0x400.

Best regards,
Jernej

> +			clocks = <&osc24M>;
> +			#pwm-cells = <3>;
> +			status = "disabled";
> +		};
> +
>  		uart0: serial@1c25000 {
>  			compatible = "snps,dw-apb-uart";
>  			reg = <0x01c25000 0x400>;





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Re: [PATCH 4/9] ARM: dts: suniv: f1c100s: add I2C DT nodes

[Jernej Škrabec]

Dne torek, 01. november 2022 ob 15:16:53 CET je Andre Przywara napisal(a):
> The Allwinner F1C100s series of SoCs contain three I2C controllers
> compatible to the ones used in other Allwinner SoCs.
> 
> Add the DT nodes describing the resources of the controllers.
> I2C1 has only one possible pinmux, so add the pinctrl properties for
> that already.
> At least one board connects an on-board I2C chip to PD0/PD12 (I2C0), so
> include those pins already, to simplify referencing them later.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
>  arch/arm/boot/dts/suniv-f1c100s.dtsi | 50 ++++++++++++++++++++++++++++
>  1 file changed, 50 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi
> b/arch/arm/boot/dts/suniv-f1c100s.dtsi index d5a6324e76465..2901c586971b4
> 100644
> --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
> +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
> @@ -166,6 +166,18 @@ mmc0_pins: mmc0-pins {
>  				drive-strength = <30>;
>  			};
> 
> +			/omit-if-no-ref/
> +			i2c0_pd_pins: i2c0-pd-pins {
> +				pins = "PD0", "PD12";
> +				function = "i2c0";
> +			};
> +
> +			/omit-if-no-ref/

Above flag is meaningless if i2c1_pins is always referenced by i2c1. Anyway, I 
see in pinctrl driver that there are actually two possible pin assignments for 
i2c1. One on port D and another on port B.

Best regards,
Jernej

> +			i2c1_pins: i2c1-pins {
> +				pins = "PD5", "PD6";
> +				function = "i2c1";
> +			};
> +
>  			spi0_pc_pins: spi0-pc-pins {
>  				pins = "PC0", "PC1", "PC2", 
"PC3";
>  				function = "spi0";
> @@ -177,6 +189,44 @@ uart0_pe_pins: uart0-pe-pins {
>  			};
>  		};
> 
> +		i2c0: i2c@1c27000 {
> +			compatible = "allwinner,suniv-f1c100s-i2c",
> +				     "allwinner,sun6i-a31-i2c";
> +			reg = <0x01c27000 0x400>;
> +			interrupts = <7>;
> +			clocks = <&ccu CLK_BUS_I2C0>;
> +			resets = <&ccu RST_BUS_I2C0>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +
> +		i2c1: i2c@1c27400 {
> +			compatible = "allwinner,suniv-f1c100s-i2c",
> +				     "allwinner,sun6i-a31-i2c";
> +			reg = <0x01c27400 0x400>;
> +			interrupts = <8>;
> +			clocks = <&ccu CLK_BUS_I2C1>;
> +			resets = <&ccu RST_BUS_I2C1>;
> +			pinctrl-names = "default";
> +			pinctrl-0 = <&i2c1_pins>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +
> +		i2c2: i2c@1c27800 {
> +			compatible = "allwinner,suniv-f1c100s-i2c",
> +				     "allwinner,sun6i-a31-i2c";
> +			reg = <0x01c27800 0x400>;
> +			interrupts = <9>;
> +			clocks = <&ccu CLK_BUS_I2C2>;
> +			resets = <&ccu RST_BUS_I2C2>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +
>  		timer@1c20c00 {
>  			compatible = "allwinner,suniv-f1c100s-
timer";
>  			reg = <0x01c20c00 0x90>;

Re: [PATCH 4/9] ARM: dts: suniv: f1c100s: add I2C DT nodes

[Jernej Škrabec]

Dne torek, 01. november 2022 ob 15:16:53 CET je Andre Przywara napisal(a):
> The Allwinner F1C100s series of SoCs contain three I2C controllers
> compatible to the ones used in other Allwinner SoCs.
> 
> Add the DT nodes describing the resources of the controllers.
> I2C1 has only one possible pinmux, so add the pinctrl properties for
> that already.
> At least one board connects an on-board I2C chip to PD0/PD12 (I2C0), so
> include those pins already, to simplify referencing them later.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
>  arch/arm/boot/dts/suniv-f1c100s.dtsi | 50 ++++++++++++++++++++++++++++
>  1 file changed, 50 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi
> b/arch/arm/boot/dts/suniv-f1c100s.dtsi index d5a6324e76465..2901c586971b4
> 100644
> --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
> +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
> @@ -166,6 +166,18 @@ mmc0_pins: mmc0-pins {
>  				drive-strength = <30>;
>  			};
> 
> +			/omit-if-no-ref/
> +			i2c0_pd_pins: i2c0-pd-pins {
> +				pins = "PD0", "PD12";
> +				function = "i2c0";
> +			};
> +
> +			/omit-if-no-ref/

Above flag is meaningless if i2c1_pins is always referenced by i2c1. Anyway, I 
see in pinctrl driver that there are actually two possible pin assignments for 
i2c1. One on port D and another on port B.

Best regards,
Jernej

> +			i2c1_pins: i2c1-pins {
> +				pins = "PD5", "PD6";
> +				function = "i2c1";
> +			};
> +
>  			spi0_pc_pins: spi0-pc-pins {
>  				pins = "PC0", "PC1", "PC2", 
"PC3";
>  				function = "spi0";
> @@ -177,6 +189,44 @@ uart0_pe_pins: uart0-pe-pins {
>  			};
>  		};
> 
> +		i2c0: i2c@1c27000 {
> +			compatible = "allwinner,suniv-f1c100s-i2c",
> +				     "allwinner,sun6i-a31-i2c";
> +			reg = <0x01c27000 0x400>;
> +			interrupts = <7>;
> +			clocks = <&ccu CLK_BUS_I2C0>;
> +			resets = <&ccu RST_BUS_I2C0>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +
> +		i2c1: i2c@1c27400 {
> +			compatible = "allwinner,suniv-f1c100s-i2c",
> +				     "allwinner,sun6i-a31-i2c";
> +			reg = <0x01c27400 0x400>;
> +			interrupts = <8>;
> +			clocks = <&ccu CLK_BUS_I2C1>;
> +			resets = <&ccu RST_BUS_I2C1>;
> +			pinctrl-names = "default";
> +			pinctrl-0 = <&i2c1_pins>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +
> +		i2c2: i2c@1c27800 {
> +			compatible = "allwinner,suniv-f1c100s-i2c",
> +				     "allwinner,sun6i-a31-i2c";
> +			reg = <0x01c27800 0x400>;
> +			interrupts = <9>;
> +			clocks = <&ccu CLK_BUS_I2C2>;
> +			resets = <&ccu RST_BUS_I2C2>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +
>  		timer@1c20c00 {
>  			compatible = "allwinner,suniv-f1c100s-
timer";
>  			reg = <0x01c20c00 0x90>;





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Re: [PATCH 5/9] clk: sunxi-ng: f1c100s: Add IR mod clock

[Jernej Škrabec]

Dne torek, 01. november 2022 ob 15:16:54 CET je Andre Przywara napisal(a):
> For some reason the mod clock for the Allwinner F1C100s CIR (infrared
> receiver) peripheral was not modeled in the CCU driver.
> 
> Add the clock description to the list, and wire it up in the clock list.
> By assigning a new clock ID at the end, it extends the number of clocks.
> 
> This allows to use the CIR peripheral on any F1C100s series board.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
>  drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c      | 11 ++++++++++-
>  drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h      |  2 +-
>  include/dt-bindings/clock/suniv-ccu-f1c100s.h |  2 ++
>  3 files changed, 13 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
> b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c index
> ed097c4f780ff..af4811e720b39 100644
> --- a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
> +++ b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
> @@ -239,7 +239,14 @@ static SUNXI_CCU_MUX_WITH_GATE(i2s_clk, "i2s",
> i2s_spdif_parents, static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif",
> i2s_spdif_parents, 0x0b4, 16, 2, BIT(31), 0);
> 
> -/* The BSP header file has a CIR_CFG, but no mod clock uses this definition
> */ +static const char * const ir_parents[] = { "osc32k", "osc24M" };
> +static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir",
> +				  ir_parents, 0x0b8,
> +				  0, 4,		/* M */
> +				  16, 2,	/* P */
> +				  24, 1,        /* mux */

Let's follow user manual here and make mux 2 bits wide. That way we'll 
guarantee that bit 1 is always written 0.

Best regards,
Jernej

> +				  BIT(31),      /* gate */
> +				  0);
> 
>  static SUNXI_CCU_GATE(usb_phy0_clk,	"usb-phy0",	"osc24M",
>  		      0x0cc, BIT(1), 0);
> @@ -355,6 +362,7 @@ static struct ccu_common *suniv_ccu_clks[] = {
>  	&mmc1_output_clk.common,
>  	&i2s_clk.common,
>  	&spdif_clk.common,
> +	&ir_clk.common,
>  	&usb_phy0_clk.common,
>  	&dram_ve_clk.common,
>  	&dram_csi_clk.common,
> @@ -446,6 +454,7 @@ static struct clk_hw_onecell_data suniv_hw_clks = {
>  		[CLK_MMC1_OUTPUT]	= &mmc1_output_clk.common.hw,
>  		[CLK_I2S]		= &i2s_clk.common.hw,
>  		[CLK_SPDIF]		= &spdif_clk.common.hw,
> +		[CLK_IR]		= &ir_clk.common.hw,
>  		[CLK_USB_PHY0]		= 
&usb_phy0_clk.common.hw,
>  		[CLK_DRAM_VE]		= 
&dram_ve_clk.common.hw,
>  		[CLK_DRAM_CSI]		= 
&dram_csi_clk.common.hw,
> diff --git a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h
> b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h index
> b22484f1bb9a5..d56a4316289d8 100644
> --- a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h
> +++ b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h
> @@ -29,6 +29,6 @@
> 
>  /* All bus gates, DRAM gates and mod clocks are exported */
> 
> -#define CLK_NUMBER		(CLK_AVS + 1)
> +#define CLK_NUMBER		(CLK_IR + 1)
> 
>  #endif /* _CCU_SUNIV_F1C100S_H_ */
> diff --git a/include/dt-bindings/clock/suniv-ccu-f1c100s.h
> b/include/dt-bindings/clock/suniv-ccu-f1c100s.h index
> f5ac155c9c70a..d7570765f424d 100644
> --- a/include/dt-bindings/clock/suniv-ccu-f1c100s.h
> +++ b/include/dt-bindings/clock/suniv-ccu-f1c100s.h
> @@ -67,4 +67,6 @@
>  #define CLK_CODEC		65
>  #define CLK_AVS			66
> 
> +#define CLK_IR			67
> +
>  #endif

Re: [PATCH 5/9] clk: sunxi-ng: f1c100s: Add IR mod clock

[Jernej Škrabec]

Dne torek, 01. november 2022 ob 15:16:54 CET je Andre Przywara napisal(a):
> For some reason the mod clock for the Allwinner F1C100s CIR (infrared
> receiver) peripheral was not modeled in the CCU driver.
> 
> Add the clock description to the list, and wire it up in the clock list.
> By assigning a new clock ID at the end, it extends the number of clocks.
> 
> This allows to use the CIR peripheral on any F1C100s series board.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
>  drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c      | 11 ++++++++++-
>  drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h      |  2 +-
>  include/dt-bindings/clock/suniv-ccu-f1c100s.h |  2 ++
>  3 files changed, 13 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
> b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c index
> ed097c4f780ff..af4811e720b39 100644
> --- a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
> +++ b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
> @@ -239,7 +239,14 @@ static SUNXI_CCU_MUX_WITH_GATE(i2s_clk, "i2s",
> i2s_spdif_parents, static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif",
> i2s_spdif_parents, 0x0b4, 16, 2, BIT(31), 0);
> 
> -/* The BSP header file has a CIR_CFG, but no mod clock uses this definition
> */ +static const char * const ir_parents[] = { "osc32k", "osc24M" };
> +static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir",
> +				  ir_parents, 0x0b8,
> +				  0, 4,		/* M */
> +				  16, 2,	/* P */
> +				  24, 1,        /* mux */

Let's follow user manual here and make mux 2 bits wide. That way we'll 
guarantee that bit 1 is always written 0.

Best regards,
Jernej

> +				  BIT(31),      /* gate */
> +				  0);
> 
>  static SUNXI_CCU_GATE(usb_phy0_clk,	"usb-phy0",	"osc24M",
>  		      0x0cc, BIT(1), 0);
> @@ -355,6 +362,7 @@ static struct ccu_common *suniv_ccu_clks[] = {
>  	&mmc1_output_clk.common,
>  	&i2s_clk.common,
>  	&spdif_clk.common,
> +	&ir_clk.common,
>  	&usb_phy0_clk.common,
>  	&dram_ve_clk.common,
>  	&dram_csi_clk.common,
> @@ -446,6 +454,7 @@ static struct clk_hw_onecell_data suniv_hw_clks = {
>  		[CLK_MMC1_OUTPUT]	= &mmc1_output_clk.common.hw,
>  		[CLK_I2S]		= &i2s_clk.common.hw,
>  		[CLK_SPDIF]		= &spdif_clk.common.hw,
> +		[CLK_IR]		= &ir_clk.common.hw,
>  		[CLK_USB_PHY0]		= 
&usb_phy0_clk.common.hw,
>  		[CLK_DRAM_VE]		= 
&dram_ve_clk.common.hw,
>  		[CLK_DRAM_CSI]		= 
&dram_csi_clk.common.hw,
> diff --git a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h
> b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h index
> b22484f1bb9a5..d56a4316289d8 100644
> --- a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h
> +++ b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h
> @@ -29,6 +29,6 @@
> 
>  /* All bus gates, DRAM gates and mod clocks are exported */
> 
> -#define CLK_NUMBER		(CLK_AVS + 1)
> +#define CLK_NUMBER		(CLK_IR + 1)
> 
>  #endif /* _CCU_SUNIV_F1C100S_H_ */
> diff --git a/include/dt-bindings/clock/suniv-ccu-f1c100s.h
> b/include/dt-bindings/clock/suniv-ccu-f1c100s.h index
> f5ac155c9c70a..d7570765f424d 100644
> --- a/include/dt-bindings/clock/suniv-ccu-f1c100s.h
> +++ b/include/dt-bindings/clock/suniv-ccu-f1c100s.h
> @@ -67,4 +67,6 @@
>  #define CLK_CODEC		65
>  #define CLK_AVS			66
> 
> +#define CLK_IR			67
> +
>  #endif





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Re: [PATCH 7/9] ARM: dts: suniv: f1c100s: add CIR DT node

[Jernej Škrabec]

Dne torek, 01. november 2022 ob 15:16:56 CET je Andre Przywara napisal(a):
> The CIR (infrared receiver) controller in the Allwinner F1C100s series
> of SoCs is compatible to the ones used in other Allwinner SoCs.
> 
> Add the DT node describing the resources of the controller.
> There are multiple possible pinmuxes, but none as them seem to be an
> obvious choice, so refrain from adding any pincontroller subnodes for
> now.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>

Best regards,
Jernej

Re: [PATCH 7/9] ARM: dts: suniv: f1c100s: add CIR DT node

[Jernej Škrabec]

Dne torek, 01. november 2022 ob 15:16:56 CET je Andre Przywara napisal(a):
> The CIR (infrared receiver) controller in the Allwinner F1C100s series
> of SoCs is compatible to the ones used in other Allwinner SoCs.
> 
> Add the DT node describing the resources of the controller.
> There are multiple possible pinmuxes, but none as them seem to be an
> obvious choice, so refrain from adding any pincontroller subnodes for
> now.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>

Best regards,
Jernej



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Re: [PATCH 9/9] ARM: dts: suniv: f1c100s: add LRADC node

[Jernej Škrabec]

Dne torek, 01. november 2022 ob 15:16:58 CET je Andre Przywara napisal(a):
> The Allwinner F1C100s series of SoCs contain a LRADC (aka. KEYADC)
> compatible to the version in other SoCs.
> The manual doesn't mention the ratio of the input voltage that is used,
> but comparing actual measurements with the values in the register
> suggests that it is 3/4 of Vref.
> 
> Add the DT node describing the base address and interrupt. As in the
> older SoCs, there is no explicit reset or clock gate, also there is a
> dedicated, non-multiplexed pin, so need for more properties.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
>  arch/arm/boot/dts/suniv-f1c100s.dtsi | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi
> b/arch/arm/boot/dts/suniv-f1c100s.dtsi index d29b48f23b89a..03592c8e63fed
> 100644
> --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
> +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
> @@ -262,6 +262,14 @@ ir: ir@1c22c00 {
>  			status = "disabled";
>  		};
> 
> +		lradc: lradc@1c23400 {
> +			compatible = "allwinner,suniv-f1c100s-
lradc",
> +				     "allwinner,sun8i-a83t-r-
lradc";
> +			reg = <0x01c23400 0x100>;

User manual says 0x400 is reserved for this peripheral. With that fixed:
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>

Best regards,
Jernej

> +			interrupts = <22>;
> +			status = "disabled";
> +		};
> +
>  		uart0: serial@1c25000 {
>  			compatible = "snps,dw-apb-uart";
>  			reg = <0x01c25000 0x400>;

Re: [PATCH 9/9] ARM: dts: suniv: f1c100s: add LRADC node

[Jernej Škrabec]

Dne torek, 01. november 2022 ob 15:16:58 CET je Andre Przywara napisal(a):
> The Allwinner F1C100s series of SoCs contain a LRADC (aka. KEYADC)
> compatible to the version in other SoCs.
> The manual doesn't mention the ratio of the input voltage that is used,
> but comparing actual measurements with the values in the register
> suggests that it is 3/4 of Vref.
> 
> Add the DT node describing the base address and interrupt. As in the
> older SoCs, there is no explicit reset or clock gate, also there is a
> dedicated, non-multiplexed pin, so need for more properties.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
>  arch/arm/boot/dts/suniv-f1c100s.dtsi | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi
> b/arch/arm/boot/dts/suniv-f1c100s.dtsi index d29b48f23b89a..03592c8e63fed
> 100644
> --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
> +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
> @@ -262,6 +262,14 @@ ir: ir@1c22c00 {
>  			status = "disabled";
>  		};
> 
> +		lradc: lradc@1c23400 {
> +			compatible = "allwinner,suniv-f1c100s-
lradc",
> +				     "allwinner,sun8i-a83t-r-
lradc";
> +			reg = <0x01c23400 0x100>;

User manual says 0x400 is reserved for this peripheral. With that fixed:
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>

Best regards,
Jernej

> +			interrupts = <22>;
> +			status = "disabled";
> +		};
> +
>  		uart0: serial@1c25000 {
>  			compatible = "snps,dw-apb-uart";
>  			reg = <0x01c25000 0x400>;





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Re: [PATCH 4/9] ARM: dts: suniv: f1c100s: add I2C DT nodes

[Andre Przywara]

On Sun, 06 Nov 2022 09:09:17 +0100
Jernej Škrabec <jernej.skrabec@gmail.com> wrote:

> Dne torek, 01. november 2022 ob 15:16:53 CET je Andre Przywara napisal(a):
> > The Allwinner F1C100s series of SoCs contain three I2C controllers
> > compatible to the ones used in other Allwinner SoCs.
> > 
> > Add the DT nodes describing the resources of the controllers.
> > I2C1 has only one possible pinmux, so add the pinctrl properties for
> > that already.
> > At least one board connects an on-board I2C chip to PD0/PD12 (I2C0), so
> > include those pins already, to simplify referencing them later.
> > 
> > Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> > ---
> >  arch/arm/boot/dts/suniv-f1c100s.dtsi | 50 ++++++++++++++++++++++++++++
> >  1 file changed, 50 insertions(+)
> > 
> > diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi
> > b/arch/arm/boot/dts/suniv-f1c100s.dtsi index d5a6324e76465..2901c586971b4
> > 100644
> > --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
> > +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
> > @@ -166,6 +166,18 @@ mmc0_pins: mmc0-pins {
> >  				drive-strength = <30>;
> >  			};
> > 
> > +			/omit-if-no-ref/
> > +			i2c0_pd_pins: i2c0-pd-pins {
> > +				pins = "PD0", "PD12";
> > +				function = "i2c0";
> > +			};
> > +
> > +			/omit-if-no-ref/  
> 
> Above flag is meaningless if i2c1_pins is always referenced by i2c1.

Indeed, good point.

> Anyway, I 
> see in pinctrl driver that there are actually two possible pin assignments for 
> i2c1. One on port D and another on port B.

Ah, those are the pins that are not documented in the manual (which is
where I looked at). I will drop that node.

Cheers,
Andre

> 
> Best regards,
> Jernej
> 
> > +			i2c1_pins: i2c1-pins {
> > +				pins = "PD5", "PD6";
> > +				function = "i2c1";
> > +			};
> > +
> >  			spi0_pc_pins: spi0-pc-pins {
> >  				pins = "PC0", "PC1", "PC2",   
> "PC3";
> >  				function = "spi0";
> > @@ -177,6 +189,44 @@ uart0_pe_pins: uart0-pe-pins {
> >  			};
> >  		};
> > 
> > +		i2c0: i2c@1c27000 {
> > +			compatible = "allwinner,suniv-f1c100s-i2c",
> > +				     "allwinner,sun6i-a31-i2c";
> > +			reg = <0x01c27000 0x400>;
> > +			interrupts = <7>;
> > +			clocks = <&ccu CLK_BUS_I2C0>;
> > +			resets = <&ccu RST_BUS_I2C0>;
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +			status = "disabled";
> > +		};
> > +
> > +		i2c1: i2c@1c27400 {
> > +			compatible = "allwinner,suniv-f1c100s-i2c",
> > +				     "allwinner,sun6i-a31-i2c";
> > +			reg = <0x01c27400 0x400>;
> > +			interrupts = <8>;
> > +			clocks = <&ccu CLK_BUS_I2C1>;
> > +			resets = <&ccu RST_BUS_I2C1>;
> > +			pinctrl-names = "default";
> > +			pinctrl-0 = <&i2c1_pins>;
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +			status = "disabled";
> > +		};
> > +
> > +		i2c2: i2c@1c27800 {
> > +			compatible = "allwinner,suniv-f1c100s-i2c",
> > +				     "allwinner,sun6i-a31-i2c";
> > +			reg = <0x01c27800 0x400>;
> > +			interrupts = <9>;
> > +			clocks = <&ccu CLK_BUS_I2C2>;
> > +			resets = <&ccu RST_BUS_I2C2>;
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +			status = "disabled";
> > +		};
> > +
> >  		timer@1c20c00 {
> >  			compatible = "allwinner,suniv-f1c100s-  
> timer";
> >  			reg = <0x01c20c00 0x90>;  
> 
> 
> 
> 
> 

Re: [PATCH 4/9] ARM: dts: suniv: f1c100s: add I2C DT nodes

[Andre Przywara]

On Sun, 06 Nov 2022 09:09:17 +0100
Jernej Škrabec <jernej.skrabec@gmail.com> wrote:

> Dne torek, 01. november 2022 ob 15:16:53 CET je Andre Przywara napisal(a):
> > The Allwinner F1C100s series of SoCs contain three I2C controllers
> > compatible to the ones used in other Allwinner SoCs.
> > 
> > Add the DT nodes describing the resources of the controllers.
> > I2C1 has only one possible pinmux, so add the pinctrl properties for
> > that already.
> > At least one board connects an on-board I2C chip to PD0/PD12 (I2C0), so
> > include those pins already, to simplify referencing them later.
> > 
> > Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> > ---
> >  arch/arm/boot/dts/suniv-f1c100s.dtsi | 50 ++++++++++++++++++++++++++++
> >  1 file changed, 50 insertions(+)
> > 
> > diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi
> > b/arch/arm/boot/dts/suniv-f1c100s.dtsi index d5a6324e76465..2901c586971b4
> > 100644
> > --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
> > +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
> > @@ -166,6 +166,18 @@ mmc0_pins: mmc0-pins {
> >  				drive-strength = <30>;
> >  			};
> > 
> > +			/omit-if-no-ref/
> > +			i2c0_pd_pins: i2c0-pd-pins {
> > +				pins = "PD0", "PD12";
> > +				function = "i2c0";
> > +			};
> > +
> > +			/omit-if-no-ref/  
> 
> Above flag is meaningless if i2c1_pins is always referenced by i2c1.

Indeed, good point.

> Anyway, I 
> see in pinctrl driver that there are actually two possible pin assignments for 
> i2c1. One on port D and another on port B.

Ah, those are the pins that are not documented in the manual (which is
where I looked at). I will drop that node.

Cheers,
Andre

> 
> Best regards,
> Jernej
> 
> > +			i2c1_pins: i2c1-pins {
> > +				pins = "PD5", "PD6";
> > +				function = "i2c1";
> > +			};
> > +
> >  			spi0_pc_pins: spi0-pc-pins {
> >  				pins = "PC0", "PC1", "PC2",   
> "PC3";
> >  				function = "spi0";
> > @@ -177,6 +189,44 @@ uart0_pe_pins: uart0-pe-pins {
> >  			};
> >  		};
> > 
> > +		i2c0: i2c@1c27000 {
> > +			compatible = "allwinner,suniv-f1c100s-i2c",
> > +				     "allwinner,sun6i-a31-i2c";
> > +			reg = <0x01c27000 0x400>;
> > +			interrupts = <7>;
> > +			clocks = <&ccu CLK_BUS_I2C0>;
> > +			resets = <&ccu RST_BUS_I2C0>;
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +			status = "disabled";
> > +		};
> > +
> > +		i2c1: i2c@1c27400 {
> > +			compatible = "allwinner,suniv-f1c100s-i2c",
> > +				     "allwinner,sun6i-a31-i2c";
> > +			reg = <0x01c27400 0x400>;
> > +			interrupts = <8>;
> > +			clocks = <&ccu CLK_BUS_I2C1>;
> > +			resets = <&ccu RST_BUS_I2C1>;
> > +			pinctrl-names = "default";
> > +			pinctrl-0 = <&i2c1_pins>;
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +			status = "disabled";
> > +		};
> > +
> > +		i2c2: i2c@1c27800 {
> > +			compatible = "allwinner,suniv-f1c100s-i2c",
> > +				     "allwinner,sun6i-a31-i2c";
> > +			reg = <0x01c27800 0x400>;
> > +			interrupts = <9>;
> > +			clocks = <&ccu CLK_BUS_I2C2>;
> > +			resets = <&ccu RST_BUS_I2C2>;
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +			status = "disabled";
> > +		};
> > +
> >  		timer@1c20c00 {
> >  			compatible = "allwinner,suniv-f1c100s-  
> timer";
> >  			reg = <0x01c20c00 0x90>;  
> 
> 
> 
> 
> 


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Re: [PATCH 2/9] ARM: dts: suniv: f1c100s: add PWM node

[Uwe Kleine-König]

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On Tue, Nov 01, 2022 at 02:16:51PM +0000, Andre Przywara wrote:
> The Allwinner F1C100s family of SoCs contain a PWM controller compatible
> to the one used in the A20 chip.
> Add the DT node so that any users can simply enable it in their board
> DT.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>

I assume this patch will go via an architecture tree (i.e. not PWM).

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-König            |
Industrial Linux Solutions                 | https://www.pengutronix.de/ |

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Re: [PATCH 2/9] ARM: dts: suniv: f1c100s: add PWM node

[Uwe Kleine-König]

[-- Attachment #1.1: Type: text/plain, Size: 634 bytes --]

On Tue, Nov 01, 2022 at 02:16:51PM +0000, Andre Przywara wrote:
> The Allwinner F1C100s family of SoCs contain a PWM controller compatible
> to the one used in the A20 chip.
> Add the DT node so that any users can simply enable it in their board
> DT.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>

I assume this patch will go via an architecture tree (i.e. not PWM).

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-König            |
Industrial Linux Solutions                 | https://www.pengutronix.de/ |

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Re: [PATCH 1/9] dt-bindings: pwm: allwinner,sun4i-a10: Add F1C100s compatible

[Uwe Kleine-König]

[-- Attachment #1: Type: text/plain, Size: 702 bytes --]

On Tue, Nov 01, 2022 at 02:16:50PM +0000, Andre Przywara wrote:
> The PWM controller in the Allwinner F1C100s series of SoCs is the same
> as in the A20 SoCs, so allow using that as the fallback name.
> 
> Join the V3s compatible string in an enum on the way.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>

Similar to patch #2 I assume this will not go via the PWM tree and so
mark the patch as handled-elsewhere in the PWM patchwork.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-König            |
Industrial Linux Solutions                 | https://www.pengutronix.de/ |

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Re: [PATCH 1/9] dt-bindings: pwm: allwinner,sun4i-a10: Add F1C100s compatible

[Uwe Kleine-König]

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On Tue, Nov 01, 2022 at 02:16:50PM +0000, Andre Przywara wrote:
> The PWM controller in the Allwinner F1C100s series of SoCs is the same
> as in the A20 SoCs, so allow using that as the fallback name.
> 
> Join the V3s compatible string in an enum on the way.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>

Similar to patch #2 I assume this will not go via the PWM tree and so
mark the patch as handled-elsewhere in the PWM patchwork.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-König            |
Industrial Linux Solutions                 | https://www.pengutronix.de/ |

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Re: [PATCH 2/9] ARM: dts: suniv: f1c100s: add PWM node

[Andre Przywara]

On Thu, 17 Nov 2022 13:03:50 +0100
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> wrote:

Hi Uwe,

> On Tue, Nov 01, 2022 at 02:16:51PM +0000, Andre Przywara wrote:
> > The Allwinner F1C100s family of SoCs contain a PWM controller compatible
> > to the one used in the A20 chip.
> > Add the DT node so that any users can simply enable it in their board
> > DT.
> > 
> > Signed-off-by: Andre Przywara <andre.przywara@arm.com>  
> 
> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
> 
> I assume this patch will go via an architecture tree (i.e. not PWM).

Yes, still the same as in the v2 that you already acked ;-)

In fact the patches are in today's -next already.

Cheers,
Andre

Re: [PATCH 2/9] ARM: dts: suniv: f1c100s: add PWM node

[Andre Przywara]

On Thu, 17 Nov 2022 13:03:50 +0100
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> wrote:

Hi Uwe,

> On Tue, Nov 01, 2022 at 02:16:51PM +0000, Andre Przywara wrote:
> > The Allwinner F1C100s family of SoCs contain a PWM controller compatible
> > to the one used in the A20 chip.
> > Add the DT node so that any users can simply enable it in their board
> > DT.
> > 
> > Signed-off-by: Andre Przywara <andre.przywara@arm.com>  
> 
> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
> 
> I assume this patch will go via an architecture tree (i.e. not PWM).

Yes, still the same as in the v2 that you already acked ;-)

In fact the patches are in today's -next already.

Cheers,
Andre

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