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Wed, 2 Nov 2022 17:40:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=stgolabs.net; s=dreamhost; t=1667436040; bh=vpS3mhEue3M8RKX/+6FKbKKv5EcohCrOAR91cRsHCBI=; h=Date:From:To:Cc:Subject:Content-Type; b=beRjdnFNqmKzYfnHS6fQulqGfsOIhHkx05NJiudJWN+QPO7VqLwXezQXIpie4vsXm m90+TvBer2m1vrgX9IUnmUeQ02T9WIh/RbrNQO7zEQQA1dPbnKQGbTCmngJ5+txo1O pbd3uGz38RyjmzQtaWUXay3qJ0sUZn0p0URHh+3uYwZ5vEHzP97zjJPSzXWT/Qeg5H IATns+JFepomjGjvkxBes3mh8ssMmRMmuQlsNYdagNXKtpKmi/1zm5FViDIxNdTr69 ySNH5cv+ITNzLJm+P7SVj0QBW+N8ZSZF+QoDqPux+FMdNE5RL7dX/1c6fRV6DQaSpo aAlk+ZUZD54FA== Date: Wed, 2 Nov 2022 17:18:33 -0700 From: Davidlohr Bueso To: Ira Weiny Cc: Bjorn Helgaas , Jonathan Cameron , Dan Williams , dave.jiang@intel.com, alison.schofield@intel.com, bwidawsk@kernel.org, vishal.l.verma@intel.com, a.manzanares@samsung.com, linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org, Bjorn Helgaas , linux-pci@vger.kernel.org, Christoph Hellwig Subject: Re: [PATCH 1/2] cxl/pci: Add generic MSI-X/MSI irq support Message-ID: <20221103001833.n2gsoflnji3pcsfr@offworld> References: <20221024133633.00000467@huawei.com> <20221025232535.GA579167@bhelgaas> <20221102171524.thsz2kwtirhxn7ee@offworld> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Disposition: inline In-Reply-To: User-Agent: NeoMutt/20220429 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 02 Nov 2022, Ira Weiny wrote: >On Wed, Nov 02, 2022 at 10:15:24AM -0700, Davidlohr Bueso wrote: >> Most CXL features that can have irqs will normally use only the first 16, >> with the exception of isolation (cxl 3.0), which per the spec is up to 32. > >Dan, Dave, and I were discussing this and we agree. For now the only things >people are working on are within the first 16 so why not just request 16 as the >max for now? It is a fair compromise, yes.