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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id i13-20020a056870890d00b0013b09a56d59sm3774129oao.27.2022.11.07.15.11.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Nov 2022 15:11:52 -0800 (PST) Received: (nullmailer pid 1834437 invoked by uid 1000); Mon, 07 Nov 2022 23:11:52 -0000 Date: Mon, 7 Nov 2022 17:11:52 -0600 From: Rob Herring To: Pierre Gondois Cc: linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Florian Fainelli , Scott Branden , Tsahee Zidenberg , Antoine Tenart , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Sudeep Holla , Lorenzo Pieralisi , =?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?= , Alim Akhtar , Shawn Guo , Sascha Hauer , =?UTF-8?Q?Andreas_F=C3=A4rber?= , Matthias Brugger , Wei Xu , Chanho Min , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Lars Povlsen , Steen Hegelund , Daniel Machon , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Thierry Reding , Bjorn Andersson , Konrad Dybcio , Geert Uytterhoeven , Magnus Damm , Heiko Stuebner , Kunihiko Hayashi , Masami Hiramatsu , Jisheng Zhang , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Peng Fan , Lucas Stach , Adam Ford , Tim Harvey , Richard Zhu , Joakim Zhang , Markus Niebel , Marek Vasut , Laurent Pinchart , Alexander Stein , Paul Elder , David Heidelberg , Oliver Graute , Liu Ying , Jacky Bai , Chris Packham , Vidya Sagar , Johan Jonker , Ezequiel Garcia , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v2 00/23] Update cache properties for arm64 DTS Message-ID: <20221107231152.GB1779129-robh@kernel.org> References: <20221107155825.1644604-1-pierre.gondois@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20221107155825.1644604-1-pierre.gondois@arm.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Nov 07, 2022 at 04:56:53PM +0100, Pierre Gondois wrote: > v2: > - Update/Add patches for missed cache properties requiring to be > updated for the following platforns: bcm, amazon, arm, exynos, > freescale, marvell, mediatek, nvidia, socinext, tesla, ti. > Missed cache properties were detected using Rob Herring's branch: > https://github.com/robherring/dt-schema/tree/cache-rework > - v1 of exynos, tesla were merged. > - Updated wrong reference in commit message. > - Added received Rb/Acked-by. > > Align arm64 DTS to the DeviceTree specification v0.3 regarding > cache properties. The patch-set mainly adds 'cache-level' or > 'cache' compatibility properties. > For one qcom DTS, level 1 cache nodes are removed as they should > be in the cpu nodes. > > On another node, it seems that the 'cache-unified' is under-used. > cache-unified: > If present, specifies the cache has a unified or- > ganization. If not present, specifies that the > cache has a Harvard architecture with separate > caches for instructions and data. > Only a few l2 cache nodes have this property, and in the absence > of [|d|i]-cache-size properties (or other), the cache is assumed to be > split. > > The l2 cache of the Rockchip RK3308 platform is thus assumed to be > split: > l2: l2-cache { > compatible = "cache"; > cache-level = <2>; > }; > when the platform datasheet advertises a unified cache. > > No modification/check was made to correct that due to the lack of > cache information for most platforms. I suppose in theory a split L2 is possible, but I think in practice that doesn't exist. The Arm ARM allows for such a thing, but this[1] says L2 caches are unified. IMO, we should just define level 2+ is unified in the schema and we can relax that if ever needed. I've updated the cache schema branch[2] with that requirement. Rob [1] https://developer.arm.com/documentation/den0024/a/Caches/Cache-terminology [2] https://github.com/robherring/dt-schema/tree/cache-rework