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pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , "Ayan Kumar Halder" Subject: [XEN v3 00/12] Arm: Enable GICv3 for AArch32 Date: Fri, 11 Nov 2022 14:17:27 +0000 Message-ID: <20221111141739.2872-1-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT105:EE_|DM6PR12MB4060:EE_ X-MS-Office365-Filtering-Correlation-Id: 0c8fdc8a-f5b3-4605-deeb-08dac3ef81d1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?BrO9EfVrG4q9RhJU+JHXIn6pUjHtUfaKzn/WMAecKulffcsEb9aQ7nmY+TZ7?= =?us-ascii?Q?sIPAKeKTtOzbKmAhoFU2k0VS4fsJX51E0wVifc6sp5QUPpKxUUrnC0jVLSRA?= =?us-ascii?Q?0E+9SjZcZO/6io1vEg2cTzo9MQalQ3r5+Llo4zypAPj7uf73qhisMyAT+g2A?= =?us-ascii?Q?0gljOJnB0j0ovsDFwoyOGIW4O4ZmqTRQ+ccT93t2ObTWNyHW9FYkIFCetbul?= =?us-ascii?Q?u5ZsBDDyP+YzFlKqWwAXo+B3/YPVOJfHuWi3aKnDWRiyAo4IzQMQHXL4ai9U?= =?us-ascii?Q?nPCRd6djQINfEAhsQQ/lxjII/aBxVT2xACidQT0KfDkF+wK7nu4qOyBZOKJS?= =?us-ascii?Q?z3gGh32ItLr6p+bXUwIU8PjrZOyDa7166j6K6kIXQWE1ZWj5ukbuF/7Jqohb?= =?us-ascii?Q?PQPT9hYa9qIWklglmcwdfN38lrCOLDSqUu63QJuy0Wz/BjRYnhb6Y96UTGlE?= =?us-ascii?Q?zApvdjujSCAgfVNz1gBhGnmIzKpVKYHCZh5aCJHFjiv/1HwGPjNpaCXUY8XT?= =?us-ascii?Q?8+hps9e7/NhWv4xE1+Dji/ydIxj2uzNo7xc+Z79TCe6NiBmvu1GSr7cI/31/?= =?us-ascii?Q?PEfLtN7MvfiZyP+ZCmOzFVFirRxpqSRA0BrqQL092YFpAY5IHIGCDf1iDhKK?= =?us-ascii?Q?1MfFERH0SxQ3ocNJOBRWenJA0r7Ec9VOKBGLQIVtamlxzJILx2TkWqfny3W/?= =?us-ascii?Q?39um9y+tjYBHTsF3YBFoneCAy9vTD4QnIUzXGpeJWEQm5T9O+ZPgXclW+U9z?= =?us-ascii?Q?r1aC6Fp1XvEVfBz6npDtWej7wEBf9SLsuAUX+MhGyULXrrssb4xQpFqOUDO5?= =?us-ascii?Q?/606iVZ3tMNMz5aIiz4RHsXQurJNjBa5EOAWkSSUj35FX2agUP5Jilotu/Jf?= =?us-ascii?Q?tCeHcTwk8FZGiDuRLP8GxYH1hc2mfcyeEfqsnUNiry5D1DuOsBKEnO+ulFUH?= =?us-ascii?Q?TVBC5kdCc21mf8Y0XpbW6aBMHwNxlBDaXhVXrjYb+yhEPpXiY87oqdrcEXq6?= =?us-ascii?Q?ZKQeSzQT0cI30yLyh34GLYDjjawRIj03qk6OTDMzlU5suxKYm7HpSHGsbm1t?= =?us-ascii?Q?coKKqSPs7Rdq6BO8HFYZqJ2/06RRb+RCFAHrIpl2b59X+KQcLwU0bVV3i7hU?= =?us-ascii?Q?8EzGP0ohnBa80b6pflC+n199CKUa4py/FWYc9FdxUUd5NwizSUlWTPh8mS8i?= =?us-ascii?Q?wZ7A2C1sW4av6jRft+TrqoykSaNmJ2L6sANwZlg6WHhNXAAaOfA1mXQjlUY?= =?us-ascii?Q?=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:5;SRV:;IPV:CAL;SFV:SPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:OSPM;SFS:(13230022)(4636009)(39860400002)(396003)(136003)(376002)(346002)(451199015)(36840700001)(46966006)(40470700004)(36756003)(26005)(82310400005)(356005)(82740400003)(81166007)(36860700001)(5660300002)(426003)(47076005)(2906002)(1076003)(186003)(40460700003)(2616005)(83380400001)(86362001)(41300700001)(8936002)(6666004)(8676002)(70206006)(70586007)(4326008)(478600001)(336012)(103116003)(54906003)(6916009)(316002)(40480700001)(36900700001)(11215385002);DIR:OUT;SFP:1501; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Nov 2022 14:17:46.8180 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0c8fdc8a-f5b3-4605-deeb-08dac3ef81d1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT105.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4060 Hi All, Please find the following patches to enable GICv3 for AArch32. This is a pre-requisite to support Xen on Cortex-R52 (AArch32-v8R system) Let me know your thoughts. The following patches have been reviewed and acked and contain no changes from v2 :- 1. [XEN v3 05/12] xen/Arm: GICv3: Fix GICR_{PENDBASER, PROPBASER} emulation on 32-bit host 2. [XEN v3 06/12] xen/Arm: vGICv3: Fix emulation of ICC_SGI1R on AArch32 Changes from - v1 :- 1. Updated in the changelog for each of the patches. v2 :- 1. Dropped "xen/Arm: GICv3: Move the macros to compute the affnity level to arm64/arm32". The reason being aff3 does not exist on arm32. And aff0..2 is the same between arm32, AArch32 and AArch64. 2. Introduce a new patch "xen/Arm: GICv3: Adapt access to VMPIDR register for AArch32". 3. For the new registers introduced, we have defined the arm32 name and then an alias. 4. Use 'AArch32' across all the patches. 5. Dropped the 'R-b' and 'Ack' in "[XEN v3 08/12] xen/Arm: GICv3: Define ICH_AP0R and ICH_AP1R for AArch32". Ayan Kumar Halder (12): xen/Arm: vGICv3: Sysreg emulation is applicable for AArch64 only xen/Arm: GICv3: Adapt access to VMPIDR register for AArch32 xen/Arm: vreg: Support vreg_reg64_* helpers on AArch32 xen/Arm: vGICv3: Adapt emulation of GICR_TYPER for AArch32 xen/Arm: GICv3: Fix GICR_{PENDBASER, PROPBASER} emulation on 32-bit host xen/Arm: vGICv3: Fix emulation of ICC_SGI1R on AArch32 xen/Arm: GICv3: Define ICH_LR_EL2 on AArch32 xen/Arm: GICv3: Define ICH_AP0R and ICH_AP1R for AArch32 xen/Arm: GICv3: Define remaining GIC registers for AArch32 xen/Arm: GICv3: Use ULL instead of UL for 64bits xen/Arm: GICv3: Define macros to read/write 64 bit xen/Arm: GICv3: Enable GICv3 for AArch32 SUPPORT.md | 7 + xen/arch/arm/Kconfig | 5 +- xen/arch/arm/gic-v3.c | 159 +++++++++++++---------- xen/arch/arm/include/asm/arm32/io.h | 9 ++ xen/arch/arm/include/asm/arm32/sysregs.h | 19 +++ xen/arch/arm/include/asm/arm64/sysregs.h | 4 + xen/arch/arm/include/asm/cpregs.h | 135 +++++++++++++++++++ xen/arch/arm/include/asm/cpufeature.h | 1 + xen/arch/arm/include/asm/gic_v3_defs.h | 24 ++-- xen/arch/arm/include/asm/vreg.h | 86 +++--------- xen/arch/arm/vgic-v3.c | 18 ++- 11 files changed, 312 insertions(+), 155 deletions(-) -- 2.17.1