From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 43564C4332F for ; Wed, 16 Nov 2022 13:55:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=8/ZJrcIJt3IAO0sf+tmHeO/ZUVNUFYATGa2r0fm+83M=; b=Q8HbBqk/cqsQ6u 9C3DgMwkYxw3858NSvkytz+3QH5CBJr/SBpnXeEDSIxiC5APTCMyf6vQW9unCSD++/t+7HY7KeFzx T9Oz1Tp3Adj3HPhdszaKDVKCPEWz1etWxctidRNY7CXqTGY0c9w/MjPVUyITHkcKRSzXDwsvbyN4U sihdTpV9CWfbo+0AMm6fWq1ayDGMdeGEJQj9fu477FKT5xCGNxpw+0f72N+GayTJ6l6gAEETMWAhK e83d8jvS+26sP1whEmD287r+xeowULxPZfSCIin7x+NFwbvyC30LHYFZMyp22gbcFNV+GtpLtotmR jxb5VBG0LwmSTol6ccxg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ovItK-004JbO-3k; Wed, 16 Nov 2022 13:55:50 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ovIst-004JNo-II for linux-riscv@lists.infradead.org; Wed, 16 Nov 2022 13:55:25 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1668606923; x=1700142923; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=h5DisrySeivO+9ObvShvEku9XKX1a+6JwPj8X269yOw=; b=oir3UshlR26dPjhTgul3Y7PC4dIikdTecpd9/Y9J0Uorg/puKmoN1bR7 FDFiV1qkm45HNthsQ3+GfMNrwsvHlNytD/AwIa33XQqPHQ6sfx23OWd+D deRWphabP3S5+95eUhVua/rWeW/4mAuLEUUIgRGdarwYjEBmvhAyTCEgM Cb8nnIgjzaggPLWI9Va0Uk9dKuXKGRyalqamQTtp2OAwnO62o0nH67doO e9/WFuE9efqf4BlnskEtt3JEnG2K87Qd7QTA3yBeuMgCVBMALOR6viJQ1 QCLYMpUvksVPbXd2uBHBMCpDlba7cUowdLOfDZ4jMmE8CBwFG00xSTUuC w==; X-IronPort-AV: E=Sophos;i="5.96,167,1665471600"; d="scan'208";a="200047079" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 16 Nov 2022 06:55:20 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Wed, 16 Nov 2022 06:55:19 -0700 Received: from daire-X570.amer.actel.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Wed, 16 Nov 2022 06:55:16 -0700 From: To: , , , , , , , , , , , CC: Daire McNamara Subject: [PATCH v1 2/9] PCI: microchip: Correct the DED and SEC interrupt bit offsets Date: Wed, 16 Nov 2022 13:54:57 +0000 Message-ID: <20221116135504.258687-3-daire.mcnamara@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221116135504.258687-1-daire.mcnamara@microchip.com> References: <20221116135504.258687-1-daire.mcnamara@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221116_055523_693291_EA7BF045 X-CRM114-Status: UNSURE ( 7.48 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Daire McNamara The SEC and DED interrupt bits were the wrong way round so the SEC interrupt handler attempted to mask, unmask, and clear the DED interrupt and vice versa. Correct the bit offsets so each interrupt handler operates properly. Signed-off-by: Daire McNamara Signed-off-by: Conor Dooley --- drivers/pci/controller/pcie-microchip-host.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/pcie-microchip-host.c b/drivers/pci/controller/pcie-microchip-host.c index 80e7554722ca..30153fd1a2b3 100644 --- a/drivers/pci/controller/pcie-microchip-host.c +++ b/drivers/pci/controller/pcie-microchip-host.c @@ -165,12 +165,12 @@ #define EVENT_PCIE_DLUP_EXIT 2 #define EVENT_SEC_TX_RAM_SEC_ERR 3 #define EVENT_SEC_RX_RAM_SEC_ERR 4 -#define EVENT_SEC_AXI2PCIE_RAM_SEC_ERR 5 -#define EVENT_SEC_PCIE2AXI_RAM_SEC_ERR 6 +#define EVENT_SEC_PCIE2AXI_RAM_SEC_ERR 5 +#define EVENT_SEC_AXI2PCIE_RAM_SEC_ERR 6 #define EVENT_DED_TX_RAM_DED_ERR 7 #define EVENT_DED_RX_RAM_DED_ERR 8 -#define EVENT_DED_AXI2PCIE_RAM_DED_ERR 9 -#define EVENT_DED_PCIE2AXI_RAM_DED_ERR 10 +#define EVENT_DED_PCIE2AXI_RAM_DED_ERR 9 +#define EVENT_DED_AXI2PCIE_RAM_DED_ERR 10 #define EVENT_LOCAL_DMA_END_ENGINE_0 11 #define EVENT_LOCAL_DMA_END_ENGINE_1 12 #define EVENT_LOCAL_DMA_ERROR_ENGINE_0 13 -- 2.25.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6EFE2C433FE for ; Wed, 16 Nov 2022 14:00:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237884AbiKPOAW (ORCPT ); Wed, 16 Nov 2022 09:00:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38132 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233666AbiKPN6S (ORCPT ); Wed, 16 Nov 2022 08:58:18 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2E065264A5; Wed, 16 Nov 2022 05:55:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1668606920; x=1700142920; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=h5DisrySeivO+9ObvShvEku9XKX1a+6JwPj8X269yOw=; b=EaprPu+Ow2V8N3uQFgvwdb9OaoVUXupzC9+k6BSNnL0kcEtKJf+WVRPV hlrCT77j8Bp3Ne3qI8IgujlBumY5pUS6y3fS3eIGcjGJE2eaiz96XDdTn Zk9D9a4qZS9df630XI/ybwThXWELVhotDlGEetbJk1iuvEaLNMYfx4cF7 Raay46KALSZTEbV6ykaPwK00ElTebzYgiT1TdHw3LbW+YzN02lKclPqTt 0l0IRrV59hdtC+BIWVmyA3x5/k1CnPCk+JaaaAwohIcOyhNBubl7a+1Ey Z+GJJzefSQu6ps/yGrV4T4ch8U8FJSkmFrR9wBnW+xdflm7KzehRGcogn A==; X-IronPort-AV: E=Sophos;i="5.96,167,1665471600"; d="scan'208";a="200047079" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 16 Nov 2022 06:55:20 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Wed, 16 Nov 2022 06:55:19 -0700 Received: from daire-X570.amer.actel.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Wed, 16 Nov 2022 06:55:16 -0700 From: To: , , , , , , , , , , , CC: Daire McNamara Subject: [PATCH v1 2/9] PCI: microchip: Correct the DED and SEC interrupt bit offsets Date: Wed, 16 Nov 2022 13:54:57 +0000 Message-ID: <20221116135504.258687-3-daire.mcnamara@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221116135504.258687-1-daire.mcnamara@microchip.com> References: <20221116135504.258687-1-daire.mcnamara@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Daire McNamara The SEC and DED interrupt bits were the wrong way round so the SEC interrupt handler attempted to mask, unmask, and clear the DED interrupt and vice versa. Correct the bit offsets so each interrupt handler operates properly. Signed-off-by: Daire McNamara Signed-off-by: Conor Dooley --- drivers/pci/controller/pcie-microchip-host.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/pcie-microchip-host.c b/drivers/pci/controller/pcie-microchip-host.c index 80e7554722ca..30153fd1a2b3 100644 --- a/drivers/pci/controller/pcie-microchip-host.c +++ b/drivers/pci/controller/pcie-microchip-host.c @@ -165,12 +165,12 @@ #define EVENT_PCIE_DLUP_EXIT 2 #define EVENT_SEC_TX_RAM_SEC_ERR 3 #define EVENT_SEC_RX_RAM_SEC_ERR 4 -#define EVENT_SEC_AXI2PCIE_RAM_SEC_ERR 5 -#define EVENT_SEC_PCIE2AXI_RAM_SEC_ERR 6 +#define EVENT_SEC_PCIE2AXI_RAM_SEC_ERR 5 +#define EVENT_SEC_AXI2PCIE_RAM_SEC_ERR 6 #define EVENT_DED_TX_RAM_DED_ERR 7 #define EVENT_DED_RX_RAM_DED_ERR 8 -#define EVENT_DED_AXI2PCIE_RAM_DED_ERR 9 -#define EVENT_DED_PCIE2AXI_RAM_DED_ERR 10 +#define EVENT_DED_PCIE2AXI_RAM_DED_ERR 9 +#define EVENT_DED_AXI2PCIE_RAM_DED_ERR 10 #define EVENT_LOCAL_DMA_END_ENGINE_0 11 #define EVENT_LOCAL_DMA_END_ENGINE_1 12 #define EVENT_LOCAL_DMA_ERROR_ENGINE_0 13 -- 2.25.1