[PATCH v3 0/3] Add (more) missing PolarFire SoC io regions

[Conor Dooley <conor@kernel.org>]

From: Conor Dooley <conor.dooley@microchip.com>

Hey all,
Apart from DDR (see [1]), these should be the last bits needed to get
recent Linux kernels booting again for Icicle/PolarFire SoC. Previously,
I had been disabling the hwrng and PCI but I keep forgetting that is
required and decided to fix that.

I'm not entirely sure if I have done some sort of no-no thing by
registering the same interrupt with both the IOSCB and SYSREG regions.
The interrupt is raised after the system controller handles a service
via the mailbox. The mailbox's status, control and mailbox registers
are all part of the IOSCB region. It's cleared by a write to a register
in the SYSREG region.
Since my goal here is to add the regions/peripherals without actually
implementing them so that Linux etc, I'm just raising an interrupt
once a guest requests a service & reporting a status indicating that the
service request failed.

Thanks,
Conor.

1 - https://lore.kernel.org/all/Y2+dUCpd8OP52%2FDJ@spud/

Changes since v2:
- fix the actual bits in the register used for the service return
  status
- remove a duplicate irq_lower() in the sysreg bits of patch 3
- move the irq raise to a write function, raising it in the read one was
  causing the irq to get raised twice by the linux driver that works
  properly with the actual hardware. oops.

Conor Dooley (3):
  hw/misc: pfsoc: add fabric clocks to ioscb
  hw/riscv: pfsoc: add missing FICs as unimplemented
  hw/{misc,riscv}: pfsoc: add system controller as unimplemented

 hw/misc/mchp_pfsoc_ioscb.c          |  78 +++++++++++++++++-
 hw/misc/mchp_pfsoc_sysreg.c         |  18 ++++-
 hw/riscv/microchip_pfsoc.c          | 121 ++++++++++++++++------------
 include/hw/misc/mchp_pfsoc_ioscb.h  |   4 +
 include/hw/misc/mchp_pfsoc_sysreg.h |   1 +
 include/hw/riscv/microchip_pfsoc.h  |   3 +
 6 files changed, 167 insertions(+), 58 deletions(-)

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2.37.2