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From: Tom Rini <trini@konsulko.com>
To: Dylan Hung <dylan_hung@aspeedtech.com>
Cc: ryan_chen@aspeedtech.com, chiawei_wang@aspeedtech.com,
	joel@jms.id.au, u-boot@lists.denx.de, BMC-SW@aspeedtech.com
Subject: Re: [PATCH 2/3] ram: ast2600: Improve ddr4 timing and signal quality
Date: Thu, 24 Nov 2022 16:33:12 -0500	[thread overview]
Message-ID: <20221124213312.GI3787616@bill-the-cat> (raw)
In-Reply-To: <20221111073008.16364-3-dylan_hung@aspeedtech.com>

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On Fri, Nov 11, 2022 at 03:30:07PM +0800, Dylan Hung wrote:

> Adjust the following settings to get better timing and signal quality.
> 
> 1. write DQS/DQ delay
> - 1e6e2304[0]
> - 1e6e2304[15:8]
> 
> 2. read DQS/DQ delay
> - 0x1e6e0298[0]
> - 0x1e6e0298[15:8]
> 
> 3. CLK/CA timing
> - 0x1e6e01a8[31]
> 
> 4. Read and write termination
> - change RTT_ROM from 40 ohm to 48 ohm (MR1[10:8])
> - change RTT_PARK from disable to 48 ohm (MR5[8:6])
> - change RTT_WR from 120 ohm to disable (MR2[11:9])
> - change PHY ODT from 40 ohm to 80 ohm (0x1e6e0130[10:8])
> 
> Note1: Both DDR-PHY and DDR controller have their own registers for DDR4
> Mode Registers (MR0~MR6).  This patch introduces macros to synchronize
> the MR value on both sides.
> 
> Note2: the waveform meansurement can be found in item #21 of Aspeed
> AST26x0 Application note (AP note).
> 
> Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>

Applied to u-boot/master, thanks!

-- 
Tom

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  parent reply	other threads:[~2022-11-24 21:33 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-11  7:30 [PATCH 0/3] Improve AST26x0 DDR4 timing and signal quality Dylan Hung
2022-11-11  7:30 ` [PATCH 1/3] ram: ast2600: Fix incorrect statement of the register polling Dylan Hung
2022-11-24  1:22   ` Ryan Chen
2022-11-24 21:33   ` Tom Rini
2022-11-11  7:30 ` [PATCH 2/3] ram: ast2600: Improve ddr4 timing and signal quality Dylan Hung
2022-11-24  1:22   ` Ryan Chen
2022-11-24 21:33   ` Tom Rini [this message]
2022-11-11  7:30 ` [PATCH 3/3] ram: ast2600: Align the RL and WL setting Dylan Hung
2022-11-24  1:23   ` Ryan Chen
2022-11-24 21:33   ` Tom Rini

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