From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 952C0C46467 for ; Sat, 26 Nov 2022 23:41:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229590AbiKZXlq (ORCPT ); Sat, 26 Nov 2022 18:41:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56954 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229502AbiKZXlk (ORCPT ); Sat, 26 Nov 2022 18:41:40 -0500 Received: from out1-smtp.messagingengine.com (out1-smtp.messagingengine.com [66.111.4.25]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1A28EEE1F for ; Sat, 26 Nov 2022 15:41:39 -0800 (PST) Received: from compute3.internal (compute3.nyi.internal [10.202.2.43]) by mailout.nyi.internal (Postfix) with ESMTP id 5FC1E5C0089; Sat, 26 Nov 2022 18:41:38 -0500 (EST) Received: from mailfrontend2 ([10.202.2.163]) by compute3.internal (MEProxy); Sat, 26 Nov 2022 18:41:38 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= cc:cc:content-transfer-encoding:date:date:from:from:in-reply-to :in-reply-to:message-id:mime-version:references:reply-to:sender :subject:subject:to:to; s=fm2; t=1669506098; x=1669592498; bh=Zv VBWKmSl7xxBZYvHtE90BQ1WRQAgayEAOP6BQlkaCs=; b=SjgYiyY/+S4zUa5tKl Cq5BDioncqCbaLz6IfExhT6rEGVgTVEiY5XMUgFwJxUrObXfQLGmIwj8iQEjFKyX QrVM1/rjS5gGEMgjOQiADW+SfFvVKkzUAQgsfTl7asHghlW5mq21olV/bVA6A2EX +rnAyzBsG73Wewm01Cm/269UOTFslFtKHtzUyLm3rf7+hMf69l+EAACCbBkEqA8S VJJ8l0SlXSU/03OXmAvUlkcbFbcgupNce2G029DKafKMuJtbvEaec+jcpxRGnhMy yHhbomkpg4kiBweYpEGKwaqaWRO7V22WfVSdFiZ3svsH4Rid8ccWx20KXWBc3u4r Lg6Q== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding:date:date :feedback-id:feedback-id:from:from:in-reply-to:in-reply-to :message-id:mime-version:references:reply-to:sender:subject :subject:to:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm1; t=1669506098; x=1669592498; bh=ZvVBWKmSl7xxB ZYvHtE90BQ1WRQAgayEAOP6BQlkaCs=; b=WCctj4ZJYSG7ke3JogAFaH9a/pYC/ 7GsYbN8g6AALi2DTzuxojVpXOnPUqvm03CjDmT8fdPfOKZGChQsXe7wrRhMSnnC9 49qvAadRQP8i2yzKoiG81avxhxdTQahft6x7+EiSuZawW5n8/8/olEOxL+Hfh6l2 lajEZPV3grAgD4refxGVtfE1Xgl1JUbXE/wc2ZW7VGmtU6idt0Ur5VtY6QG2SMeU JqX+J9snBGFR9lbwyASwMGoG4z1JK/0u76h+o2m9X9EHmSbTSKpkLvtYjIzSQSVK zFAePkQG5Gcr5ShRHYUezadsyK+z4tbl+LUpyi+PEwpjTPyUorcK3KWPg== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvgedrieekgdduvdcutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenuc fjughrpefhvfevufffkffojghfggfgsedtkeertdertddtnecuhfhrohhmpefurghmuhgv lhcujfholhhlrghnugcuoehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhgqeenucggtf frrghtthgvrhhnpedukeetueduhedtleetvefguddvvdejhfefudelgfduveeggeehgfdu feeitdevteenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhgrihhlfhhroh hmpehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhg X-ME-Proxy: Feedback-ID: i0ad843c9:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Sat, 26 Nov 2022 18:41:37 -0500 (EST) From: Samuel Holland To: Marc Zyngier , Thomas Gleixner , Palmer Dabbelt Cc: linux-riscv@lists.infradead.org, Samuel Holland , Paul Walmsley , linux-kernel@vger.kernel.org Subject: [PATCH 2/3] genirq: Add support for oneshot-safe threaded EOIs Date: Sat, 26 Nov 2022 17:41:33 -0600 Message-Id: <20221126234134.32660-3-samuel@sholland.org> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20221126234134.32660-1-samuel@sholland.org> References: <20221126234134.32660-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org For irqchips such as the SiFive PLIC with a claim/EOI flow, each IRQ is implicitly masked during the claim operation and unmasked after the EOI. By delaying the EOI until after the thread runs, we can support threaded IRQs without any explicit mask/unmask operations. irqchips can declare this capability using the combination of flags IRQCHIP_ONESHOT_SAFE | IRQCHIP_EOI_THREADED. In this case, we still set IRQF_ONESHOT and thus action->thread_mask, so we know based on desc->threads_oneshot when to send the EOI. However, we do not set IRQS_ONESHOT, so we skip the actual mask/unmask operations. Signed-off-by: Samuel Holland --- kernel/irq/chip.c | 4 +++- kernel/irq/manage.c | 15 ++++++++++----- 2 files changed, 13 insertions(+), 6 deletions(-) diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c index 672bad021a1f..7a4b3fa85da0 100644 --- a/kernel/irq/chip.c +++ b/kernel/irq/chip.c @@ -446,7 +446,9 @@ void unmask_threaded_irq(struct irq_desc *desc) if (chip->flags & IRQCHIP_EOI_THREADED) chip->irq_eoi(&desc->irq_data); - unmask_irq(desc); + if (!irqd_irq_disabled(&desc->irq_data) && + (desc->istate & IRQS_ONESHOT)) + unmask_irq(desc); } /* diff --git a/kernel/irq/manage.c b/kernel/irq/manage.c index 40fe7806cc8c..b9edb66428cd 100644 --- a/kernel/irq/manage.c +++ b/kernel/irq/manage.c @@ -1074,9 +1074,10 @@ static int irq_wait_for_interrupt(struct irqaction *action) static void irq_finalize_oneshot(struct irq_desc *desc, struct irqaction *action) { - if (!(desc->istate & IRQS_ONESHOT) || + if (!(action->flags & IRQF_ONESHOT) || action->handler == irq_forced_secondary_handler) return; + again: chip_bus_lock(desc); raw_spin_lock_irq(&desc->lock); @@ -1112,8 +1113,7 @@ static void irq_finalize_oneshot(struct irq_desc *desc, desc->threads_oneshot &= ~action->thread_mask; - if (!desc->threads_oneshot && !irqd_irq_disabled(&desc->irq_data) && - irqd_irq_masked(&desc->irq_data)) + if (!desc->threads_oneshot) unmask_threaded_irq(desc); out_unlock: @@ -1565,8 +1565,12 @@ __setup_irq(unsigned int irq, struct irq_desc *desc, struct irqaction *new) * MSI based interrupts are per se one shot safe. Check the * chip flags, so we can avoid the unmask dance at the end of * the threaded handler for those. + * + * If IRQCHIP_EOI_THREADED is also set, we do an EOI dance + * instead of a mask/unmask dance. */ - if (desc->irq_data.chip->flags & IRQCHIP_ONESHOT_SAFE) + if (desc->irq_data.chip->flags & IRQCHIP_ONESHOT_SAFE && + !(desc->irq_data.chip->flags & IRQCHIP_EOI_THREADED)) new->flags &= ~IRQF_ONESHOT; /* @@ -1755,7 +1759,8 @@ __setup_irq(unsigned int irq, struct irq_desc *desc, struct irqaction *new) if (noirqdebug) irq_settings_set_no_debug(desc); - if (new->flags & IRQF_ONESHOT) + if (new->flags & IRQF_ONESHOT && + !(desc->irq_data.chip->flags & IRQCHIP_ONESHOT_SAFE)) desc->istate |= IRQS_ONESHOT; /* Exclude IRQ from balancing if requested */ -- 2.37.4 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6EA9AC4167B for ; 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Sat, 26 Nov 2022 18:41:37 -0500 (EST) From: Samuel Holland To: Marc Zyngier , Thomas Gleixner , Palmer Dabbelt Cc: linux-riscv@lists.infradead.org, Samuel Holland , Paul Walmsley , linux-kernel@vger.kernel.org Subject: [PATCH 2/3] genirq: Add support for oneshot-safe threaded EOIs Date: Sat, 26 Nov 2022 17:41:33 -0600 Message-Id: <20221126234134.32660-3-samuel@sholland.org> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20221126234134.32660-1-samuel@sholland.org> References: <20221126234134.32660-1-samuel@sholland.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221126_154148_460299_6B1DA3CE X-CRM114-Status: GOOD ( 15.55 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org For irqchips such as the SiFive PLIC with a claim/EOI flow, each IRQ is implicitly masked during the claim operation and unmasked after the EOI. By delaying the EOI until after the thread runs, we can support threaded IRQs without any explicit mask/unmask operations. irqchips can declare this capability using the combination of flags IRQCHIP_ONESHOT_SAFE | IRQCHIP_EOI_THREADED. In this case, we still set IRQF_ONESHOT and thus action->thread_mask, so we know based on desc->threads_oneshot when to send the EOI. However, we do not set IRQS_ONESHOT, so we skip the actual mask/unmask operations. Signed-off-by: Samuel Holland --- kernel/irq/chip.c | 4 +++- kernel/irq/manage.c | 15 ++++++++++----- 2 files changed, 13 insertions(+), 6 deletions(-) diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c index 672bad021a1f..7a4b3fa85da0 100644 --- a/kernel/irq/chip.c +++ b/kernel/irq/chip.c @@ -446,7 +446,9 @@ void unmask_threaded_irq(struct irq_desc *desc) if (chip->flags & IRQCHIP_EOI_THREADED) chip->irq_eoi(&desc->irq_data); - unmask_irq(desc); + if (!irqd_irq_disabled(&desc->irq_data) && + (desc->istate & IRQS_ONESHOT)) + unmask_irq(desc); } /* diff --git a/kernel/irq/manage.c b/kernel/irq/manage.c index 40fe7806cc8c..b9edb66428cd 100644 --- a/kernel/irq/manage.c +++ b/kernel/irq/manage.c @@ -1074,9 +1074,10 @@ static int irq_wait_for_interrupt(struct irqaction *action) static void irq_finalize_oneshot(struct irq_desc *desc, struct irqaction *action) { - if (!(desc->istate & IRQS_ONESHOT) || + if (!(action->flags & IRQF_ONESHOT) || action->handler == irq_forced_secondary_handler) return; + again: chip_bus_lock(desc); raw_spin_lock_irq(&desc->lock); @@ -1112,8 +1113,7 @@ static void irq_finalize_oneshot(struct irq_desc *desc, desc->threads_oneshot &= ~action->thread_mask; - if (!desc->threads_oneshot && !irqd_irq_disabled(&desc->irq_data) && - irqd_irq_masked(&desc->irq_data)) + if (!desc->threads_oneshot) unmask_threaded_irq(desc); out_unlock: @@ -1565,8 +1565,12 @@ __setup_irq(unsigned int irq, struct irq_desc *desc, struct irqaction *new) * MSI based interrupts are per se one shot safe. Check the * chip flags, so we can avoid the unmask dance at the end of * the threaded handler for those. + * + * If IRQCHIP_EOI_THREADED is also set, we do an EOI dance + * instead of a mask/unmask dance. */ - if (desc->irq_data.chip->flags & IRQCHIP_ONESHOT_SAFE) + if (desc->irq_data.chip->flags & IRQCHIP_ONESHOT_SAFE && + !(desc->irq_data.chip->flags & IRQCHIP_EOI_THREADED)) new->flags &= ~IRQF_ONESHOT; /* @@ -1755,7 +1759,8 @@ __setup_irq(unsigned int irq, struct irq_desc *desc, struct irqaction *new) if (noirqdebug) irq_settings_set_no_debug(desc); - if (new->flags & IRQF_ONESHOT) + if (new->flags & IRQF_ONESHOT && + !(desc->irq_data.chip->flags & IRQCHIP_ONESHOT_SAFE)) desc->istate |= IRQS_ONESHOT; /* Exclude IRQ from balancing if requested */ -- 2.37.4 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv