* [PATCH v2 0/2] riscv,isa fixups
@ 2022-11-30 18:04 ` Conor Dooley
0 siblings, 0 replies; 10+ messages in thread
From: Conor Dooley @ 2022-11-30 18:04 UTC (permalink / raw)
To: Palmer Dabbelt, linux-riscv
Cc: Conor Dooley, Conor Dooley, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Albert Ou, Heiko Stuebner, Andrew Jones, Guo Ren,
devicetree, linux-kernel
From: Conor Dooley <conor.dooley@microchip.com>
I noticed ~today~ while looking at the isa manual that I had not
accounted for another couple of edge cases with my regex. As before, I
think attempting to validate the canonical order for multiletter stuff
makes no sense - but we should totally try to avoid false-positives for
combinations that are known to be valid.
All I've changed here for v2 is collecting tags & adding in the missing
commit reference that Heiko pointed out.
@Palmer, either you can take this once the DT folks have ACKed it if you
like, or I will take onto some v6.2-rcN fixes branch. I don't think that
there is any urgency :)
Thanks,
Conor.
CC: Conor Dooley <conor@kernel.org>
CC: Rob Herring <robh+dt@kernel.org>
CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
CC: Paul Walmsley <paul.walmsley@sifive.com>
CC: Palmer Dabbelt <palmer@dabbelt.com>
CC: Albert Ou <aou@eecs.berkeley.edu>
CC: Heiko Stuebner <heiko@sntech.de>
CC: Andrew Jones <ajones@ventanamicro.com>
CC: Guo Ren <guoren@kernel.org>
CC: linux-riscv@lists.infradead.org
CC: devicetree@vger.kernel.org
CC: linux-kernel@vger.kernel.org
Conor Dooley (2):
dt-bindings: riscv: fix underscore requirement for addtional standard
extensions
dt-bindings: riscv: fix single letter canonical order
Documentation/devicetree/bindings/riscv/cpus.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--
2.38.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH v2 1/2] dt-bindings: riscv: fix underscore requirement for addtional standard extensions
2022-11-30 18:04 ` Conor Dooley
@ 2022-11-30 18:04 ` Conor Dooley
-1 siblings, 0 replies; 10+ messages in thread
From: Conor Dooley @ 2022-11-30 18:04 UTC (permalink / raw)
To: Palmer Dabbelt, linux-riscv
Cc: Conor Dooley, Conor Dooley, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Albert Ou, Heiko Stuebner, Andrew Jones, Guo Ren,
devicetree, linux-kernel
From: Conor Dooley <conor.dooley@microchip.com>
The RISC-V ISA Manual allows for the first Additional Standard
Extension having no leading underscore. Only if there are multiple
Additional Standard Extensions is it needed to have an underscore.
The dt-binding does not validate that a multi-letter extension is
canonically ordered, as that'd need an even worse regex than is here,
but it should not fail validation for valid ISA strings.
Allow the first Z multi-letter extension to appear immediately prior
after the single-letter extensions.
Link: https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-unpriv-pdf-from-asciidoc-15112022 # Chapter 29.5
Fixes: 299824e68bd0 ("dt-bindings: riscv: add new riscv,isa strings for emulators")
Acked-by: Guo Ren <guoren@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 90a7cabf58fe..e80c967a4fa4 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -80,7 +80,7 @@ properties:
insensitive, letters in the riscv,isa string must be all
lowercase to simplify parsing.
$ref: "/schemas/types.yaml#/definitions/string"
- pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:_[hsxz](?:[a-z])+)*$
+ pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:z(?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$
# RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
timebase-frequency: false
--
2.38.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v2 1/2] dt-bindings: riscv: fix underscore requirement for addtional standard extensions
@ 2022-11-30 18:04 ` Conor Dooley
0 siblings, 0 replies; 10+ messages in thread
From: Conor Dooley @ 2022-11-30 18:04 UTC (permalink / raw)
To: Palmer Dabbelt, linux-riscv
Cc: Conor Dooley, Conor Dooley, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Albert Ou, Heiko Stuebner, Andrew Jones, Guo Ren,
devicetree, linux-kernel
From: Conor Dooley <conor.dooley@microchip.com>
The RISC-V ISA Manual allows for the first Additional Standard
Extension having no leading underscore. Only if there are multiple
Additional Standard Extensions is it needed to have an underscore.
The dt-binding does not validate that a multi-letter extension is
canonically ordered, as that'd need an even worse regex than is here,
but it should not fail validation for valid ISA strings.
Allow the first Z multi-letter extension to appear immediately prior
after the single-letter extensions.
Link: https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-unpriv-pdf-from-asciidoc-15112022 # Chapter 29.5
Fixes: 299824e68bd0 ("dt-bindings: riscv: add new riscv,isa strings for emulators")
Acked-by: Guo Ren <guoren@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 90a7cabf58fe..e80c967a4fa4 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -80,7 +80,7 @@ properties:
insensitive, letters in the riscv,isa string must be all
lowercase to simplify parsing.
$ref: "/schemas/types.yaml#/definitions/string"
- pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:_[hsxz](?:[a-z])+)*$
+ pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:z(?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$
# RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
timebase-frequency: false
--
2.38.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v2 1/2] dt-bindings: riscv: fix underscore requirement for addtional standard extensions
2022-11-30 18:04 ` Conor Dooley
@ 2022-11-30 18:29 ` Jessica Clarke
-1 siblings, 0 replies; 10+ messages in thread
From: Jessica Clarke @ 2022-11-30 18:29 UTC (permalink / raw)
To: Conor Dooley
Cc: Palmer Dabbelt, linux-riscv, Conor Dooley, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Albert Ou, Heiko Stuebner,
Andrew Jones, Guo Ren, devicetree, linux-kernel
On 30 Nov 2022, at 18:04, Conor Dooley <conor@kernel.org> wrote:
>
> From: Conor Dooley <conor.dooley@microchip.com>
>
> The RISC-V ISA Manual allows for the first Additional Standard
> Extension having no leading underscore. Only if there are multiple
> Additional Standard Extensions is it needed to have an underscore.
>
> The dt-binding does not validate that a multi-letter extension is
> canonically ordered, as that'd need an even worse regex than is here,
> but it should not fail validation for valid ISA strings.
>
> Allow the first Z multi-letter extension to appear immediately prior
> after the single-letter extensions.
>
> Link: https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-unpriv-pdf-from-asciidoc-15112022 # Chapter 29.5
> Fixes: 299824e68bd0 ("dt-bindings: riscv: add new riscv,isa strings for emulators")
> Acked-by: Guo Ren <guoren@kernel.org>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index 90a7cabf58fe..e80c967a4fa4 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -80,7 +80,7 @@ properties:
> insensitive, letters in the riscv,isa string must be all
> lowercase to simplify parsing.
> $ref: "/schemas/types.yaml#/definitions/string"
> - pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:_[hsxz](?:[a-z])+)*$
> + pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:z(?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$
Isn’t it any multi-letter extension, i.e, this should be [hsxz] again?
It certainly used to be at least; we use rv64gcxcheri...
Jess
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH v2 1/2] dt-bindings: riscv: fix underscore requirement for addtional standard extensions
@ 2022-11-30 18:29 ` Jessica Clarke
0 siblings, 0 replies; 10+ messages in thread
From: Jessica Clarke @ 2022-11-30 18:29 UTC (permalink / raw)
To: Conor Dooley
Cc: Palmer Dabbelt, linux-riscv, Conor Dooley, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Albert Ou, Heiko Stuebner,
Andrew Jones, Guo Ren, devicetree, linux-kernel
On 30 Nov 2022, at 18:04, Conor Dooley <conor@kernel.org> wrote:
>
> From: Conor Dooley <conor.dooley@microchip.com>
>
> The RISC-V ISA Manual allows for the first Additional Standard
> Extension having no leading underscore. Only if there are multiple
> Additional Standard Extensions is it needed to have an underscore.
>
> The dt-binding does not validate that a multi-letter extension is
> canonically ordered, as that'd need an even worse regex than is here,
> but it should not fail validation for valid ISA strings.
>
> Allow the first Z multi-letter extension to appear immediately prior
> after the single-letter extensions.
>
> Link: https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-unpriv-pdf-from-asciidoc-15112022 # Chapter 29.5
> Fixes: 299824e68bd0 ("dt-bindings: riscv: add new riscv,isa strings for emulators")
> Acked-by: Guo Ren <guoren@kernel.org>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index 90a7cabf58fe..e80c967a4fa4 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -80,7 +80,7 @@ properties:
> insensitive, letters in the riscv,isa string must be all
> lowercase to simplify parsing.
> $ref: "/schemas/types.yaml#/definitions/string"
> - pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:_[hsxz](?:[a-z])+)*$
> + pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:z(?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$
Isn’t it any multi-letter extension, i.e, this should be [hsxz] again?
It certainly used to be at least; we use rv64gcxcheri...
Jess
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH v2 1/2] dt-bindings: riscv: fix underscore requirement for addtional standard extensions
2022-11-30 18:29 ` Jessica Clarke
@ 2022-11-30 18:35 ` Conor Dooley
-1 siblings, 0 replies; 10+ messages in thread
From: Conor Dooley @ 2022-11-30 18:35 UTC (permalink / raw)
To: Jessica Clarke
Cc: Palmer Dabbelt, linux-riscv, Conor Dooley, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Albert Ou, Heiko Stuebner,
Andrew Jones, Guo Ren, devicetree, linux-kernel
On Wed, Nov 30, 2022 at 06:29:18PM +0000, Jessica Clarke wrote:
> On 30 Nov 2022, at 18:04, Conor Dooley <conor@kernel.org> wrote:
> >
> > From: Conor Dooley <conor.dooley@microchip.com>
> >
> > The RISC-V ISA Manual allows for the first Additional Standard
> > Extension having no leading underscore. Only if there are multiple
> > Additional Standard Extensions is it needed to have an underscore.
> >
> > The dt-binding does not validate that a multi-letter extension is
> > canonically ordered, as that'd need an even worse regex than is here,
> > but it should not fail validation for valid ISA strings.
> >
> > Allow the first Z multi-letter extension to appear immediately prior
> > after the single-letter extensions.
> >
> > Link: https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-unpriv-pdf-from-asciidoc-15112022 # Chapter 29.5
> > Fixes: 299824e68bd0 ("dt-bindings: riscv: add new riscv,isa strings for emulators")
> > Acked-by: Guo Ren <guoren@kernel.org>
> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> > ---
> > Documentation/devicetree/bindings/riscv/cpus.yaml | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > index 90a7cabf58fe..e80c967a4fa4 100644
> > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > @@ -80,7 +80,7 @@ properties:
> > insensitive, letters in the riscv,isa string must be all
> > lowercase to simplify parsing.
> > $ref: "/schemas/types.yaml#/definitions/string"
> > - pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:_[hsxz](?:[a-z])+)*$
> > + pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:z(?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$
>
> Isn’t it any multi-letter extension, i.e, this should be [hsxz] again?
>
> It certainly used to be at least; we use rv64gcxcheri...
<quote>
Non-standard extensions must be listed after all standard extensions.
They must be separated from other multi-letter extensions
by an underscore
<\quote>
Nope, you're right. I realised that the other day with the non-binding
series that was a response to v1. I had that itching feeling that I had
forgotten to do something when I was writing my changelog but could not
remember what...
Thanks Jess!
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH v2 1/2] dt-bindings: riscv: fix underscore requirement for addtional standard extensions
@ 2022-11-30 18:35 ` Conor Dooley
0 siblings, 0 replies; 10+ messages in thread
From: Conor Dooley @ 2022-11-30 18:35 UTC (permalink / raw)
To: Jessica Clarke
Cc: Palmer Dabbelt, linux-riscv, Conor Dooley, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Albert Ou, Heiko Stuebner,
Andrew Jones, Guo Ren, devicetree, linux-kernel
On Wed, Nov 30, 2022 at 06:29:18PM +0000, Jessica Clarke wrote:
> On 30 Nov 2022, at 18:04, Conor Dooley <conor@kernel.org> wrote:
> >
> > From: Conor Dooley <conor.dooley@microchip.com>
> >
> > The RISC-V ISA Manual allows for the first Additional Standard
> > Extension having no leading underscore. Only if there are multiple
> > Additional Standard Extensions is it needed to have an underscore.
> >
> > The dt-binding does not validate that a multi-letter extension is
> > canonically ordered, as that'd need an even worse regex than is here,
> > but it should not fail validation for valid ISA strings.
> >
> > Allow the first Z multi-letter extension to appear immediately prior
> > after the single-letter extensions.
> >
> > Link: https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-unpriv-pdf-from-asciidoc-15112022 # Chapter 29.5
> > Fixes: 299824e68bd0 ("dt-bindings: riscv: add new riscv,isa strings for emulators")
> > Acked-by: Guo Ren <guoren@kernel.org>
> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> > ---
> > Documentation/devicetree/bindings/riscv/cpus.yaml | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > index 90a7cabf58fe..e80c967a4fa4 100644
> > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > @@ -80,7 +80,7 @@ properties:
> > insensitive, letters in the riscv,isa string must be all
> > lowercase to simplify parsing.
> > $ref: "/schemas/types.yaml#/definitions/string"
> > - pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:_[hsxz](?:[a-z])+)*$
> > + pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:z(?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$
>
> Isn’t it any multi-letter extension, i.e, this should be [hsxz] again?
>
> It certainly used to be at least; we use rv64gcxcheri...
<quote>
Non-standard extensions must be listed after all standard extensions.
They must be separated from other multi-letter extensions
by an underscore
<\quote>
Nope, you're right. I realised that the other day with the non-binding
series that was a response to v1. I had that itching feeling that I had
forgotten to do something when I was writing my changelog but could not
remember what...
Thanks Jess!
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 2/2] dt-bindings: riscv: fix single letter canonical order
2022-11-30 18:04 ` Conor Dooley
@ 2022-11-30 18:04 ` Conor Dooley
-1 siblings, 0 replies; 10+ messages in thread
From: Conor Dooley @ 2022-11-30 18:04 UTC (permalink / raw)
To: Palmer Dabbelt, linux-riscv
Cc: Conor Dooley, Conor Dooley, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Albert Ou, Heiko Stuebner, Andrew Jones, Guo Ren,
devicetree, linux-kernel, Palmer Dabbelt
From: Conor Dooley <conor.dooley@microchip.com>
I used the wikipedia table for ordering extensions when updating the
pattern here in commit 299824e68bd0 ("dt-bindings: riscv: add new
riscv,isa strings for emulators").
Unfortunately that table did not match canonical order, as defined by
the RISC-V ISA Manual, which defines extension ordering in (what is
currently) Table 41, "Standard ISA extension names". Fix things up by
re-sorting v (vector) and adding p (packed-simd) & j (dynamic
languages). The e (reduced integer) and g (general) extensions are still
intentionally left out.
Link: https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-unpriv-pdf-from-asciidoc-15112022 # Chapter 29.5
Fixes: 299824e68bd0 ("dt-bindings: riscv: add new riscv,isa strings for emulators")
Acked-by: Guo Ren <guoren@kernel.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index e80c967a4fa4..b7462ea2dbe4 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -80,7 +80,7 @@ properties:
insensitive, letters in the riscv,isa string must be all
lowercase to simplify parsing.
$ref: "/schemas/types.yaml#/definitions/string"
- pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:z(?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$
+ pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:z(?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$
# RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
timebase-frequency: false
--
2.38.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v2 2/2] dt-bindings: riscv: fix single letter canonical order
@ 2022-11-30 18:04 ` Conor Dooley
0 siblings, 0 replies; 10+ messages in thread
From: Conor Dooley @ 2022-11-30 18:04 UTC (permalink / raw)
To: Palmer Dabbelt, linux-riscv
Cc: Conor Dooley, Conor Dooley, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Albert Ou, Heiko Stuebner, Andrew Jones, Guo Ren,
devicetree, linux-kernel, Palmer Dabbelt
From: Conor Dooley <conor.dooley@microchip.com>
I used the wikipedia table for ordering extensions when updating the
pattern here in commit 299824e68bd0 ("dt-bindings: riscv: add new
riscv,isa strings for emulators").
Unfortunately that table did not match canonical order, as defined by
the RISC-V ISA Manual, which defines extension ordering in (what is
currently) Table 41, "Standard ISA extension names". Fix things up by
re-sorting v (vector) and adding p (packed-simd) & j (dynamic
languages). The e (reduced integer) and g (general) extensions are still
intentionally left out.
Link: https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-unpriv-pdf-from-asciidoc-15112022 # Chapter 29.5
Fixes: 299824e68bd0 ("dt-bindings: riscv: add new riscv,isa strings for emulators")
Acked-by: Guo Ren <guoren@kernel.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index e80c967a4fa4..b7462ea2dbe4 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -80,7 +80,7 @@ properties:
insensitive, letters in the riscv,isa string must be all
lowercase to simplify parsing.
$ref: "/schemas/types.yaml#/definitions/string"
- pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:z(?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$
+ pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:z(?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$
# RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
timebase-frequency: false
--
2.38.1
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