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[198.145.64.163]) by smtp.gmail.com with ESMTPSA id 74-20020a62164d000000b0056c0d129edfsm5718087pfw.121.2022.12.02.18.24.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Dec 2022 18:24:43 -0800 (PST) Date: Fri, 2 Dec 2022 18:24:42 -0800 From: Kees Cook To: Rick Edgecombe Cc: x86@kernel.org, "H . Peter Anvin" , Thomas Gleixner , Ingo Molnar , linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-api@vger.kernel.org, Arnd Bergmann , Andy Lutomirski , Balbir Singh , Borislav Petkov , Cyrill Gorcunov , Dave Hansen , Eugene Syromiatnikov , Florian Weimer , "H . J . Lu" , Jann Horn , Jonathan Corbet , Mike Kravetz , Nadav Amit , Oleg Nesterov , Pavel Machek , Peter Zijlstra , Randy Dunlap , Weijiang Yang , "Kirill A . Shutemov" , John Allen , kcc@google.com, eranian@google.com, rppt@kernel.org, jamorris@linux.microsoft.com, dethoma@microsoft.com, akpm@linux-foundation.org, Andrew.Cooper3@citrix.com, christina.schimpe@intel.com, Yu-cheng Yu Subject: Re: [PATCH v4 05/39] x86/fpu/xstate: Introduce CET MSR and XSAVES supervisor states Message-ID: <202212021824.8EE4948F9@keescook> References: <20221203003606.6838-1-rick.p.edgecombe@intel.com> <20221203003606.6838-6-rick.p.edgecombe@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20221203003606.6838-6-rick.p.edgecombe@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Dec 02, 2022 at 04:35:32PM -0800, Rick Edgecombe wrote: > From: Yu-cheng Yu > > Shadow stack register state can be managed with XSAVE. The registers > can logically be separated into two groups: > * Registers controlling user-mode operation > * Registers controlling kernel-mode operation > > The architecture has two new XSAVE state components: one for each group > of those groups of registers. This lets an OS manage them separately if > it chooses. Future patches for host userspace and KVM guests will only > utilize the user-mode registers, so only configure XSAVE to save > user-mode registers. This state will add 16 bytes to the xsave buffer > size. > > Future patches will use the user-mode XSAVE area to save guest user-mode > CET state. However, VMCS includes new fields for guest CET supervisor > states. KVM can use these to save and restore guest supervisor state, so > host supervisor XSAVE support is not required. > > Adding this exacerbates the already unwieldy if statement in > check_xstate_against_struct() that handles warning about un-implemented > xfeatures. So refactor these check's by having XCHECK_SZ() set a bool when > it actually check's the xfeature. This ends up exceeding 80 chars, but was > better on balance than other options explored. Pass the bool as pointer to > make it clear that XCHECK_SZ() can change the variable. > > While configuring user-mode XSAVE, clarify kernel-mode registers are not > managed by XSAVE by defining the xfeature in > XFEATURE_MASK_SUPERVISOR_UNSUPPORTED, like is done for XFEATURE_MASK_PT. > This serves more of a documentation as code purpose, and functionally, > only enables a few safety checks. > > Both XSAVE state components are supervisor states, even the state > controlling user-mode operation. This is a departure from earlier features > like protection keys where the PKRU state is a normal user > (non-supervisor) state. Having the user state be supervisor-managed > ensures there is no direct, unprivileged access to it, making it harder > for an attacker to subvert CET. > > To facilitate this privileged access, define the two user-mode CET MSRs, > and the bits defined in those MSRs relevant to future shadow stack > enablement patches. > > Tested-by: Pengfei Xu > Tested-by: John Allen > Signed-off-by: Yu-cheng Yu Reviewed-by: Kees Cook -- Kees Cook