From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45EB4C4167B for ; Wed, 14 Dec 2022 19:30:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238688AbiLNTac (ORCPT ); Wed, 14 Dec 2022 14:30:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47650 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229558AbiLNTab (ORCPT ); Wed, 14 Dec 2022 14:30:31 -0500 Received: from m-r1.th.seeweb.it (m-r1.th.seeweb.it [IPv6:2001:4b7a:2000:18::170]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1894D286C1; Wed, 14 Dec 2022 11:30:30 -0800 (PST) Received: from SoMainline.org (94-209-172-39.cable.dynamic.v4.ziggo.nl [94.209.172.39]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r1.th.seeweb.it (Postfix) with ESMTPSA id B993820222; Wed, 14 Dec 2022 20:30:27 +0100 (CET) Date: Wed, 14 Dec 2022 20:30:26 +0100 From: Marijn Suijten To: Dmitry Baryshkov Cc: phone-devel@vger.kernel.org, Rob Clark , Abhinav Kumar , Vinod Koul , ~postmarketos/upstreaming@lists.sr.ht, AngeloGioacchino Del Regno , Konrad Dybcio , Martin Botka , Jami Kettunen , Sean Paul , David Airlie , Daniel Vetter , Stephen Boyd , Bjorn Andersson , Jessica Zhang , Ville =?utf-8?B?U3lyasOkbMOk?= , Kuogee Hsieh , Jani Nikula , sunliming , Sam Ravnborg , Haowen Bai , Konrad Dybcio , Loic Poulain , Vinod Polimera , Douglas Anderson , Vladimir Lypak , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: Re: [RFC PATCH 3/6] drm/msm/dpu1: Wire up DSC mask for active CTL configuration Message-ID: <20221214193026.dv2fuubysctcvlkg@SoMainline.org> Mail-Followup-To: Marijn Suijten , Dmitry Baryshkov , phone-devel@vger.kernel.org, Rob Clark , Abhinav Kumar , Vinod Koul , ~postmarketos/upstreaming@lists.sr.ht, AngeloGioacchino Del Regno , Konrad Dybcio , Martin Botka , Jami Kettunen , Sean Paul , David Airlie , Daniel Vetter , Stephen Boyd , Bjorn Andersson , Jessica Zhang , Ville =?utf-8?B?U3lyasOkbMOk?= , Kuogee Hsieh , Jani Nikula , sunliming , Sam Ravnborg , Haowen Bai , Konrad Dybcio , Loic Poulain , Vinod Polimera , Douglas Anderson , Vladimir Lypak , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org References: <20221213232207.113607-1-marijn.suijten@somainline.org> <20221213232207.113607-4-marijn.suijten@somainline.org> <184d22f1-7ed1-4a67-1c25-9fafeb94db83@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <184d22f1-7ed1-4a67-1c25-9fafeb94db83@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 2022-12-14 20:43:29, Dmitry Baryshkov wrote: > On 14/12/2022 01:22, Marijn Suijten wrote: > > Active CTLs have to configure what DSC block(s) have to be enabled, and > > what DSC block(s) have to be flushed; this value was initialized to zero > > resulting in the necessary register writes to never happen (or would > > write zero otherwise). This seems to have gotten lost in the DSC v4->v5 > > series while refactoring how the combination with merge_3d was handled. > > > > Fixes: 58dca9810749 ("drm/msm/disp/dpu1: Add support for DSC in encoder") > > Signed-off-by: Marijn Suijten > > --- > > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 1 + > > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 1 + > > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 2 ++ > > 3 files changed, 4 insertions(+) > > > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c > > index ae28b2b93e69..35791f93c33d 100644 > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c > > @@ -61,6 +61,7 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg( > > intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_CMD; > > intf_cfg.stream_sel = cmd_enc->stream_sel; > > intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); > > + intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc); > > ctl->ops.setup_intf_cfg(ctl, &intf_cfg); > > > > /* setup which pp blk will connect to this intf */ > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > > index 0f71e8fe7be7..9ee3a7306a5f 100644 > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > > @@ -274,6 +274,7 @@ static void dpu_encoder_phys_vid_setup_timing_engine( > > intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_VID; > > intf_cfg.stream_sel = 0; /* Don't care value for video mode */ > > intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); > > + intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc); > > if (phys_enc->hw_pp->merge_3d) > > intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx; > > > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c > > index 7cbcef6efe17..92ddf9995b37 100644 > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c > > @@ -209,6 +209,7 @@ static void dpu_encoder_phys_wb_setup_cdp(struct dpu_encoder_phys *phys_enc) > > > > intf_cfg.intf = DPU_NONE; > > intf_cfg.wb = hw_wb->idx; > > + intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc); > > We usually don't have DSC with the writeback, don't we? I am unsure so ended up adding them in writeback regardless. Downstream uses a separate callback to process intf_cfg.dsc instead of going through setup_intf_cfg(). To prevent these from being missed again (in the case of copy&paste), how about instead having some function that sets up intf_cfg with these default values from a phys_enc? That way most of this remains oblivious to the caller. On the same note, that callback on non-DPU_CTL_ACTIVE_CFG hardware doesn't use the intf_cfg.dsc member anyway, but it was again added to keep the blocks somewhat consistent (in case it ever becomes used?). > > if (mode_3d && hw_pp && hw_pp->merge_3d) > > intf_cfg.merge_3d = hw_pp->merge_3d->idx; > > @@ -230,6 +231,7 @@ static void dpu_encoder_phys_wb_setup_cdp(struct dpu_encoder_phys *phys_enc) > > intf_cfg.wb = hw_wb->idx; > > intf_cfg.mode_3d = > > dpu_encoder_helper_get_3d_blend_mode(phys_enc); > > + intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc); > > phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg); > > } > > } - Marijn From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4DAD7C4332F for ; Wed, 14 Dec 2022 19:31:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 77BC610E45E; Wed, 14 Dec 2022 19:31:04 +0000 (UTC) Received: from relay03.th.seeweb.it (relay03.th.seeweb.it [5.144.164.164]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5926810E469; Wed, 14 Dec 2022 19:31:01 +0000 (UTC) Received: from SoMainline.org (94-209-172-39.cable.dynamic.v4.ziggo.nl [94.209.172.39]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r1.th.seeweb.it (Postfix) with ESMTPSA id B993820222; Wed, 14 Dec 2022 20:30:27 +0100 (CET) Date: Wed, 14 Dec 2022 20:30:26 +0100 From: Marijn Suijten To: Dmitry Baryshkov Subject: Re: [RFC PATCH 3/6] drm/msm/dpu1: Wire up DSC mask for active CTL configuration Message-ID: <20221214193026.dv2fuubysctcvlkg@SoMainline.org> Mail-Followup-To: Marijn Suijten , Dmitry Baryshkov , phone-devel@vger.kernel.org, Rob Clark , Abhinav Kumar , Vinod Koul , ~postmarketos/upstreaming@lists.sr.ht, AngeloGioacchino Del Regno , Konrad Dybcio , Martin Botka , Jami Kettunen , Sean Paul , David Airlie , Daniel Vetter , Stephen Boyd , Bjorn Andersson , Jessica Zhang , Ville =?utf-8?B?U3lyasOkbMOk?= , Kuogee Hsieh , Jani Nikula , sunliming , Sam Ravnborg , Haowen Bai , Konrad Dybcio , Loic Poulain , Vinod Polimera , Douglas Anderson , Vladimir Lypak , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org References: <20221213232207.113607-1-marijn.suijten@somainline.org> <20221213232207.113607-4-marijn.suijten@somainline.org> <184d22f1-7ed1-4a67-1c25-9fafeb94db83@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <184d22f1-7ed1-4a67-1c25-9fafeb94db83@linaro.org> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Konrad Dybcio , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, AngeloGioacchino Del Regno , phone-devel@vger.kernel.org, Sam Ravnborg , Haowen Bai , Vinod Koul , Kuogee Hsieh , Jessica Zhang , Jani Nikula , linux-arm-msm@vger.kernel.org, Abhinav Kumar , Stephen Boyd , Martin Botka , ~postmarketos/upstreaming@lists.sr.ht, Sean Paul , Loic Poulain , Jami Kettunen , Bjorn Andersson , Vladimir Lypak , Douglas Anderson , Konrad Dybcio , sunliming , freedreno@lists.freedesktop.org, Vinod Polimera Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 2022-12-14 20:43:29, Dmitry Baryshkov wrote: > On 14/12/2022 01:22, Marijn Suijten wrote: > > Active CTLs have to configure what DSC block(s) have to be enabled, and > > what DSC block(s) have to be flushed; this value was initialized to zero > > resulting in the necessary register writes to never happen (or would > > write zero otherwise). This seems to have gotten lost in the DSC v4->v5 > > series while refactoring how the combination with merge_3d was handled. > > > > Fixes: 58dca9810749 ("drm/msm/disp/dpu1: Add support for DSC in encoder") > > Signed-off-by: Marijn Suijten > > --- > > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 1 + > > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 1 + > > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 2 ++ > > 3 files changed, 4 insertions(+) > > > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c > > index ae28b2b93e69..35791f93c33d 100644 > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c > > @@ -61,6 +61,7 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg( > > intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_CMD; > > intf_cfg.stream_sel = cmd_enc->stream_sel; > > intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); > > + intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc); > > ctl->ops.setup_intf_cfg(ctl, &intf_cfg); > > > > /* setup which pp blk will connect to this intf */ > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > > index 0f71e8fe7be7..9ee3a7306a5f 100644 > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > > @@ -274,6 +274,7 @@ static void dpu_encoder_phys_vid_setup_timing_engine( > > intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_VID; > > intf_cfg.stream_sel = 0; /* Don't care value for video mode */ > > intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); > > + intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc); > > if (phys_enc->hw_pp->merge_3d) > > intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx; > > > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c > > index 7cbcef6efe17..92ddf9995b37 100644 > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c > > @@ -209,6 +209,7 @@ static void dpu_encoder_phys_wb_setup_cdp(struct dpu_encoder_phys *phys_enc) > > > > intf_cfg.intf = DPU_NONE; > > intf_cfg.wb = hw_wb->idx; > > + intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc); > > We usually don't have DSC with the writeback, don't we? I am unsure so ended up adding them in writeback regardless. Downstream uses a separate callback to process intf_cfg.dsc instead of going through setup_intf_cfg(). To prevent these from being missed again (in the case of copy&paste), how about instead having some function that sets up intf_cfg with these default values from a phys_enc? That way most of this remains oblivious to the caller. On the same note, that callback on non-DPU_CTL_ACTIVE_CFG hardware doesn't use the intf_cfg.dsc member anyway, but it was again added to keep the blocks somewhat consistent (in case it ever becomes used?). > > if (mode_3d && hw_pp && hw_pp->merge_3d) > > intf_cfg.merge_3d = hw_pp->merge_3d->idx; > > @@ -230,6 +231,7 @@ static void dpu_encoder_phys_wb_setup_cdp(struct dpu_encoder_phys *phys_enc) > > intf_cfg.wb = hw_wb->idx; > > intf_cfg.mode_3d = > > dpu_encoder_helper_get_3d_blend_mode(phys_enc); > > + intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc); > > phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg); > > } > > } - Marijn