From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Richard Weinberger <richard@nod.at>,
Vignesh Raghavendra <vigneshr@ti.com>,
Tudor Ambarus <Tudor.Ambarus@microchip.com>,
Pratyush Yadav <pratyush@kernel.org>,
Michael Walle <michael@walle.cc>, <linux-mtd@lists.infradead.org>
Cc: Julien Su <juliensu@mxic.com.tw>,
Jaime Liao <jaimeliao@mxic.com.tw>,
Alvin Zhou <alvinzhou@mxic.com.tw>,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
Miquel Raynal <miquel.raynal@bootlin.com>
Subject: [PATCH v3 3/9] mtd: spi-nor: Add a macro to define more banks
Date: Thu, 15 Dec 2022 09:12:35 +0100 [thread overview]
Message-ID: <20221215081241.407098-4-miquel.raynal@bootlin.com> (raw)
In-Reply-To: <20221215081241.407098-1-miquel.raynal@bootlin.com>
Most of the chips on the market only feature a single bank. However, new
chips may support more than a single bank, with the possibility to
parallelize some operations. Let's introduce an INFOB() macro which also
takes a n_bank parameter.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Pratyush Yadav <pratyush@kernel.org>
---
drivers/mtd/spi-nor/core.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index 8a067d56c995..044d49d749e0 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -553,6 +553,10 @@ struct flash_info {
SPI_NOR_ID((_jedec_id), (_ext_id)), \
SPI_NOR_GEOMETRY((_sector_size), (_n_sectors), 1),
+#define INFOB(_jedec_id, _ext_id, _sector_size, _n_sectors, _n_banks) \
+ SPI_NOR_ID((_jedec_id), (_ext_id)), \
+ SPI_NOR_GEOMETRY((_sector_size), (_n_sectors), (_n_banks)),
+
#define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors) \
SPI_NOR_ID6((_jedec_id), (_ext_id)), \
SPI_NOR_GEOMETRY((_sector_size), (_n_sectors), 1),
--
2.34.1
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next prev parent reply other threads:[~2022-12-15 8:13 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-15 8:12 [PATCH v3 0/9] mtd: spi-nor: read while write support Miquel Raynal
2022-12-15 8:12 ` [PATCH v3 1/9] mtd: spi-nor: Create macros to define chip IDs and geometries Miquel Raynal
2023-01-31 8:58 ` Tudor Ambarus
2022-12-15 8:12 ` [PATCH v3 2/9] mtd: spi-nor: Introduce the concept of bank Miquel Raynal
2023-01-19 16:34 ` Tudor Ambarus
2023-02-01 11:32 ` Miquel Raynal
2023-03-17 3:33 ` Tudor Ambarus
2023-03-24 15:13 ` Miquel Raynal
2022-12-15 8:12 ` Miquel Raynal [this message]
2022-12-15 8:12 ` [PATCH v3 4/9] mtd: spi-nor: Reorder the preparation vs locking steps Miquel Raynal
2023-01-31 5:11 ` Tudor Ambarus
2023-02-01 11:36 ` Miquel Raynal
2022-12-15 8:12 ` [PATCH v3 5/9] mtd: spi-nor: Separate preparation and locking Miquel Raynal
2022-12-15 8:12 ` [PATCH v3 6/9] mtd: spi-nor: Prepare the introduction of a new locking mechanism Miquel Raynal
2023-01-31 5:29 ` Tudor Ambarus
2022-12-15 8:12 ` [PATCH v3 7/9] mtd: spi-nor: Add a RWW flag Miquel Raynal
2022-12-15 8:12 ` [PATCH v3 8/9] mtd: spi-nor: Enhance locking to support reads while writes Miquel Raynal
2022-12-15 8:12 ` [PATCH v3 9/9] mtd: spi-nor: macronix: Add support for mx25uw51245g with RWW Miquel Raynal
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