From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B43FC3DA71 for ; Thu, 15 Dec 2022 21:42:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229811AbiLOVmq (ORCPT ); Thu, 15 Dec 2022 16:42:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42040 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229736AbiLOVmj (ORCPT ); Thu, 15 Dec 2022 16:42:39 -0500 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9BACA5C76B; Thu, 15 Dec 2022 13:42:34 -0800 (PST) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2BFLfnha052913; Thu, 15 Dec 2022 15:41:49 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1671140509; bh=WLpVP2bWfliAogzAGVvfrb8O9z6xT+DatR+7Ps4pVB8=; h=Date:From:To:CC:Subject:References:In-Reply-To; b=YkRW9VrIYluAbll9dwl1NaXdtykQ7/RwaMYW9TfyfocH17R2Oxf/oe4ljablDsk/y 9UlFYgkNzoEhKp8WSsbOz8FJ3YrvKGoM5/qTXEXUa2IhZHLu0AmWmRzwG5U8ew57Kf 2R+TII0CdC9MeRqbpfF+76gxynynnU7qQj+W4C4M= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2BFLfncA110061 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 15 Dec 2022 15:41:49 -0600 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Thu, 15 Dec 2022 15:41:49 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Thu, 15 Dec 2022 15:41:49 -0600 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2BFLfnGb072680; Thu, 15 Dec 2022 15:41:49 -0600 Date: Thu, 15 Dec 2022 15:41:49 -0600 From: Nishanth Menon To: Mark Brown CC: jerome Neanne , Wadim Egorov , "lgirdwood@gmail.com" , "robh+dt@kernel.org" , "kristo@kernel.org" , "dmitry.torokhov@gmail.com" , "krzysztof.kozlowski+dt@linaro.org" , "catalin.marinas@arm.com" , "will@kernel.org" , "lee@kernel.org" , "tony@atomide.com" , "vigneshr@ti.com" , "shawnguo@kernel.org" , "geert+renesas@glider.be" , "dmitry.baryshkov@linaro.org" , "marcel.ziswiler@toradex.com" , "vkoul@kernel.org" , "biju.das.jz@bp.renesas.com" , "arnd@arndb.de" , "jeff@labundy.com" , "afd@ti.com" , "khilman@baylibre.com" , "narmstrong@baylibre.com" , "msp@baylibre.com" , "j-keerthy@ti.com" , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-input@vger.kernel.org" , "linux-omap@vger.kernel.org" Subject: Re: [PATCH v7 1/6] DONOTMERGE: arm64: dts: ti: Add TI TPS65219 PMIC support for AM642 SK board. Message-ID: <20221215214149.whcjdphxxvvedrih@affront> References: <20221104152311.1098603-1-jneanne@baylibre.com> <20221104152311.1098603-2-jneanne@baylibre.com> <20221215175411.znxy3d6ussq2iq5h@grieving> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: User-Agent: NeoMutt/20171215 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 18:22-20221215, Mark Brown wrote: > On Thu, Dec 15, 2022 at 11:54:11AM -0600, Nishanth Menon wrote: > > On 16:09-20221215, Mark Brown wrote: > > > > That proposal looks really non-idiomatic and quite unusual, if there's a > > > fixed voltage supply to the LDO I'd expect to see it modeled as a fixed > > > voltage regulator. I'm not sure what the use of bypass here is trying > > > to accomplish TBH. > > > The problem is this - the default NVM in the PMIC is setup such that > > VSET value =3.3v and bypass bit set (makes sense since the vin=3.3v). > > This implies no voltage drop over the LDO? Sounds a bit suspect. Not the choice I'd probably have made ;) > > > Now the constraint is bypass bit cannot be changed without the LDO > > being switched off. > > > regulator-allow-bypass property allows us to control bypass bit, but we > > should'nt toggle it when LDO is active. Not providing the property > > implies the bit wont be toggled by regulator core either. > > > What we need is a scheme that will disable the bypass bit with the > > intent of operating the LDO with just the vset field. I did'nt find it > > possible atm.. unless I am mistaken.. > > Can the consumer just disable the supply as part of startup? Though > that's starting to feel rather board specific. There's not really a Yeah - this happens to be SDcard supply (at least in my case).. I'd rather not change the mmc host or core layer to handle a case where LDO happened to be in bypass. it is a regulator driver's problem, IMHO how to provide the stated voltage OR fail to transition the voltage. In this driver's case, it happily accepts and set the VSET voltage - for example to 1.8V, but then, since the bypass bit is set, well, voltage sticks around at 3.3v. > good place to put a board specific setup process like that in the kernel > at the minute, you'd ideally want the firmware to leave the device at > least disabled if not actually out of bypass on startup so we don't have > to deal with this. Ugh... Yeah - that would be the other option - I could plug this bypass clear in the u-boot or someplace early so that the LDO behaves Also the reason why I did'nt send the mentioned patch (or the like upstream and the patch was done just a couple of days back) were the following questions: a) Why would'nt we handle the case where bypass bit is set AND voltage change implies bypass bit needs to be disabled? (i would expect it to fail but if i did provide regulator-allow-bypass, then if bypass is set AND requested-voltage != vin-supply, then i'd have expected framework to probably disable bypass and switch voltage to new voltage - which this driver, based on it's constraint will say "nope, cant do" - but that would be better than silently telling me all good, setting vset and leaving the bypass bit on.) b) If I wanted the LDO to poweroff the bypass bit at start (define the startup hardware condition), I dont seem to have a description for that either. -- Regards, Nishanth Menon Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 756F9C4332F for ; Thu, 15 Dec 2022 21:43:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:CC:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=P0yAUTfrFr2lNyUV5wuy9uaqnkzOYMd7tuAlOKb159U=; b=uv5icIhQ4Zqg5o w507YKS+hDWJQfKkzEoTj5h75Thv44OzYGpcO6k3orNmukb4xp+yAHygAUUMVPBM9UUiPbfY2X1ow PrTgk6hOqWO8VacRtCxNuu1iY+LLznJ2KV4ccC3Nei3JUoqfIZWykRhfo0N9wc7C+pfYMz2JyYTwC qX+gTSToY3/AO3BGAnCV4TQHkZrRMzM9c2aDsXpTiCMaqxKelduuWkW10jTWBq20+g1t9ECLdfQhD 5xjIEbo1EuoTr3HuRSR6Qz2oS0l1zGWjrrT67TCAFMYP5iuGKqy08WJFZXJm3oyxHhlzASdgOnrpL U8J6P1n4DkQsqH9d5LMA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1p5vzq-00BVxg-0T; Thu, 15 Dec 2022 21:42:30 +0000 Received: from fllv0016.ext.ti.com ([198.47.19.142]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1p5vzm-00BVvu-Su for linux-arm-kernel@lists.infradead.org; Thu, 15 Dec 2022 21:42:28 +0000 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2BFLfnha052913; Thu, 15 Dec 2022 15:41:49 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1671140509; bh=WLpVP2bWfliAogzAGVvfrb8O9z6xT+DatR+7Ps4pVB8=; h=Date:From:To:CC:Subject:References:In-Reply-To; b=YkRW9VrIYluAbll9dwl1NaXdtykQ7/RwaMYW9TfyfocH17R2Oxf/oe4ljablDsk/y 9UlFYgkNzoEhKp8WSsbOz8FJ3YrvKGoM5/qTXEXUa2IhZHLu0AmWmRzwG5U8ew57Kf 2R+TII0CdC9MeRqbpfF+76gxynynnU7qQj+W4C4M= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2BFLfncA110061 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 15 Dec 2022 15:41:49 -0600 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Thu, 15 Dec 2022 15:41:49 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Thu, 15 Dec 2022 15:41:49 -0600 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2BFLfnGb072680; Thu, 15 Dec 2022 15:41:49 -0600 Date: Thu, 15 Dec 2022 15:41:49 -0600 From: Nishanth Menon To: Mark Brown CC: jerome Neanne , Wadim Egorov , "lgirdwood@gmail.com" , "robh+dt@kernel.org" , "kristo@kernel.org" , "dmitry.torokhov@gmail.com" , "krzysztof.kozlowski+dt@linaro.org" , "catalin.marinas@arm.com" , "will@kernel.org" , "lee@kernel.org" , "tony@atomide.com" , "vigneshr@ti.com" , "shawnguo@kernel.org" , "geert+renesas@glider.be" , "dmitry.baryshkov@linaro.org" , "marcel.ziswiler@toradex.com" , "vkoul@kernel.org" , "biju.das.jz@bp.renesas.com" , "arnd@arndb.de" , "jeff@labundy.com" , "afd@ti.com" , "khilman@baylibre.com" , "narmstrong@baylibre.com" , "msp@baylibre.com" , "j-keerthy@ti.com" , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-input@vger.kernel.org" , "linux-omap@vger.kernel.org" Subject: Re: [PATCH v7 1/6] DONOTMERGE: arm64: dts: ti: Add TI TPS65219 PMIC support for AM642 SK board. Message-ID: <20221215214149.whcjdphxxvvedrih@affront> References: <20221104152311.1098603-1-jneanne@baylibre.com> <20221104152311.1098603-2-jneanne@baylibre.com> <20221215175411.znxy3d6ussq2iq5h@grieving> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: NeoMutt/20171215 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221215_134227_098066_D3FC5FAD X-CRM114-Status: GOOD ( 29.70 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 18:22-20221215, Mark Brown wrote: > On Thu, Dec 15, 2022 at 11:54:11AM -0600, Nishanth Menon wrote: > > On 16:09-20221215, Mark Brown wrote: > > > > That proposal looks really non-idiomatic and quite unusual, if there's a > > > fixed voltage supply to the LDO I'd expect to see it modeled as a fixed > > > voltage regulator. I'm not sure what the use of bypass here is trying > > > to accomplish TBH. > > > The problem is this - the default NVM in the PMIC is setup such that > > VSET value =3.3v and bypass bit set (makes sense since the vin=3.3v). > > This implies no voltage drop over the LDO? Sounds a bit suspect. Not the choice I'd probably have made ;) > > > Now the constraint is bypass bit cannot be changed without the LDO > > being switched off. > > > regulator-allow-bypass property allows us to control bypass bit, but we > > should'nt toggle it when LDO is active. Not providing the property > > implies the bit wont be toggled by regulator core either. > > > What we need is a scheme that will disable the bypass bit with the > > intent of operating the LDO with just the vset field. I did'nt find it > > possible atm.. unless I am mistaken.. > > Can the consumer just disable the supply as part of startup? Though > that's starting to feel rather board specific. There's not really a Yeah - this happens to be SDcard supply (at least in my case).. I'd rather not change the mmc host or core layer to handle a case where LDO happened to be in bypass. it is a regulator driver's problem, IMHO how to provide the stated voltage OR fail to transition the voltage. In this driver's case, it happily accepts and set the VSET voltage - for example to 1.8V, but then, since the bypass bit is set, well, voltage sticks around at 3.3v. > good place to put a board specific setup process like that in the kernel > at the minute, you'd ideally want the firmware to leave the device at > least disabled if not actually out of bypass on startup so we don't have > to deal with this. Ugh... Yeah - that would be the other option - I could plug this bypass clear in the u-boot or someplace early so that the LDO behaves Also the reason why I did'nt send the mentioned patch (or the like upstream and the patch was done just a couple of days back) were the following questions: a) Why would'nt we handle the case where bypass bit is set AND voltage change implies bypass bit needs to be disabled? (i would expect it to fail but if i did provide regulator-allow-bypass, then if bypass is set AND requested-voltage != vin-supply, then i'd have expected framework to probably disable bypass and switch voltage to new voltage - which this driver, based on it's constraint will say "nope, cant do" - but that would be better than silently telling me all good, setting vset and leaving the bypass bit on.) b) If I wanted the LDO to poweroff the bypass bit at start (define the startup hardware condition), I dont seem to have a description for that either. -- Regards, Nishanth Menon Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel