Re: wm8904 and output volume control

From: Charles Keepax <ckeepax@opensource.cirrus.com>
To: Emanuele Ghidoli <ghidoliemanuele@gmail.com>
Cc: alsa-devel@alsa-project.org, Liam Girdwood <lgirdwood@gmail.com>,
	Takashi Iwai <tiwai@suse.com>, Michael Walle <michael@walle.cc>,
	Mark Brown <broonie@kernel.org>,
	Francesco Dolcini <francesco.dolcini@toradex.com>,
	emanuele.ghidoli@toradex.com
Subject: Re: wm8904 and output volume control
Date: Mon, 19 Dec 2022 09:58:46 +0000	[thread overview]
Message-ID: <20221219095846.GC36097@ediswmail.ad.cirrus.com> (raw)
In-Reply-To: <c7864c35-738c-a867-a6a6-ddf9f98df7e7@gmail.com>

On Sat, Dec 17, 2022 at 12:47:14AM +0100, Emanuele Ghidoli wrote:
> Hello,
> I have found that output volume is set to the default value after a
> limited time (~4 seconds) after play stop.
> I have analyzed what is happening:
> - at first play the volume is the expected one
> - After stopping playing + ~4 seconds wm8904_set_bias_level (...,
> SND_SOC_BIAS_OFF) is called
> - Chip is reset and regulator is switched off if "possible" (not in
> our case, it is important to note)
> - at second play wm8904_set_bias_level (..., SND_SOC_BIAS_STANDBY)
> is called. wm8904_hw_params is also called just before.
> 
> I see that all I2C transactions are good, registers are written as
> expected, especially volume control register (even the silly
> HPOUT_VU bit, to do a volume update is correctly written).
> Reading out this register, using i2cget (bypassing regcache), report
> the "expected" value. But the real output volume correspond to the
> default value (hw default, that it is the same value in
> wm8904_reg_defaults structure).
> 
> I checked that SYSCLK_ENA is 0 during register writing (needed if
> MCLK/SYSCLK is not present). I do not know if there is some other
> constrain on these registers.
> 

Yes this might be my guess as well, I wonder if the HPOUT_VU bit
needs SYSCLK to be present to take effect.

> If I rewrite the volume control register, a second time, the volume
> is set (tested with i2cset, from user space. And from kernel space,
> bypassing regcache).
> 

When you write the value the second time is that still before
SYSCLK is present?

Also does just writing one of HPOUT volumes cause the other to
get updated? The HPOUT_VU bit should trigger an update to both.

> I resolve also by reverting e9149b8c00d2 ("ASoC: wm8904: fix
> regcache handling").
> I'm not here to say that the commit is wrong. I analyzed it and seem
> perfect (in few words it align the hw with the regcache avoiding
> potential incoherence).
> 

Yeah I think that commit is fine, I would wager that your system
doesn't turn off the regulators so without that commit the
register retains the old volume across the "power down".

Thanks,
Charles