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From: Zheng Wang <zyytlz.wz@163.com>
To: zhi.a.wang@intel.com
Cc: 1002992920@qq.com, airlied@gmail.com, airlied@linux.ie,
	alex000young@gmail.com, dri-devel@lists.freedesktop.org,
	gregkh@linuxfoundation.org, hackerzheng666@gmail.com,
	intel-gfx@lists.freedesktop.org,
	intel-gvt-dev@lists.freedesktop.org,
	joonas.lahtinen@linux.intel.com, linux-kernel@vger.kernel.org,
	security@kernel.org, tvrtko.ursulin@linux.intel.com,
	zhenyuw@linux.intel.com, zyytlz.wz@163.com
Subject: [RESEND PATCH v4] drm/i915/gvt: fix double free bug in split_2MB_gtt_entry
Date: Mon, 19 Dec 2022 20:52:04 +0800	[thread overview]
Message-ID: <20221219125204.1001149-1-zyytlz.wz@163.com> (raw)
In-Reply-To: <11728bc1-7b59-1623-b517-d1a0d57eb275@intel.com>

If intel_gvt_dma_map_guest_page failed, it will call
 ppgtt_invalidate_spt, which will finally free the spt. But the caller does
 not notice that, it will free spt again in error path.

Fix this by undoing the mapping of DMA address and freeing sub_spt.

Fixes: b901b252b6cf ("drm/i915/gvt: Add 2M huge gtt support")
Signed-off-by: Zheng Wang <zyytlz.wz@163.com>
---
v4:
- fix by undo the mapping of DMA address and free sub_spt suggested by Zhi

v3:
- correct spelling mistake and remove unused variable suggested by Greg

v2: https://lore.kernel.org/all/20221006165845.1735393-1-zyytlz.wz@163.com/

v1: https://lore.kernel.org/all/20220928033340.1063949-1-zyytlz.wz@163.com/
---
 drivers/gpu/drm/i915/gvt/gtt.c | 53 +++++++++++++++++++++++++++++-----
 1 file changed, 46 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index 51e5e8fb505b..b472e021e5a4 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -1192,11 +1192,11 @@ static int split_2MB_gtt_entry(struct intel_vgpu *vgpu,
 {
 	const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
 	struct intel_vgpu_ppgtt_spt *sub_spt;
-	struct intel_gvt_gtt_entry sub_se;
+	struct intel_gvt_gtt_entry sub_se, e;
 	unsigned long start_gfn;
 	dma_addr_t dma_addr;
-	unsigned long sub_index;
-	int ret;
+	unsigned long sub_index, parent_index;
+	int ret, ret1;
 
 	gvt_dbg_mm("Split 2M gtt entry, index %lu\n", index);
 
@@ -1209,10 +1209,8 @@ static int split_2MB_gtt_entry(struct intel_vgpu *vgpu,
 	for_each_shadow_entry(sub_spt, &sub_se, sub_index) {
 		ret = intel_gvt_dma_map_guest_page(vgpu, start_gfn + sub_index,
 						   PAGE_SIZE, &dma_addr);
-		if (ret) {
-			ppgtt_invalidate_spt(spt);
-			return ret;
-		}
+		if (ret)
+			goto err;
 		sub_se.val64 = se->val64;
 
 		/* Copy the PAT field from PDE. */
@@ -1231,6 +1229,47 @@ static int split_2MB_gtt_entry(struct intel_vgpu *vgpu,
 	ops->set_pfn(se, sub_spt->shadow_page.mfn);
 	ppgtt_set_shadow_entry(spt, se, index);
 	return 0;
+err:
+	/* Undone the existing mappings of DMA addr. */
+	for_each_present_shadow_entry(spt, &e, parent_index) {
+		switch (e.type) {
+		case GTT_TYPE_PPGTT_PTE_4K_ENTRY:
+			gvt_vdbg_mm("invalidate 4K entry\n");
+			ppgtt_invalidate_pte(spt, &e);
+			break;
+		case GTT_TYPE_PPGTT_PTE_64K_ENTRY:
+			/* We don't setup 64K shadow entry so far. */
+			WARN(1, "suspicious 64K gtt entry\n");
+			continue;
+		case GTT_TYPE_PPGTT_PTE_2M_ENTRY:
+			gvt_vdbg_mm("invalidate 2M entry\n");
+			continue;
+		case GTT_TYPE_PPGTT_PTE_1G_ENTRY:
+			WARN(1, "GVT doesn't support 1GB page\n");
+			continue;
+		case GTT_TYPE_PPGTT_PML4_ENTRY:
+		case GTT_TYPE_PPGTT_PDP_ENTRY:
+		case GTT_TYPE_PPGTT_PDE_ENTRY:
+			gvt_vdbg_mm("invalidate PMUL4/PDP/PDE entry\n");
+			ret1 = ppgtt_invalidate_spt_by_shadow_entry(
+					spt->vgpu, &e);
+			if (ret1) {
+				gvt_vgpu_err("fail: shadow page %p shadow entry 0x%llx type %d\n",
+				spt, e.val64, e.type);
+				goto free_spt;
+			}
+			break;
+		default:
+			GEM_BUG_ON(1);
+		}
+	}
+	/* Release the new alloced apt. */
+free_spt:
+	trace_spt_change(sub_spt->vgpu->id, "release", sub_spt,
+		sub_spt->guest_page.gfn, sub_spt->shadow_page.type);
+	ppgtt_free_spt(sub_spt);
+	sub_spt = NULL;
+	return ret;
 }
 
 static int split_64KB_gtt_entry(struct intel_vgpu *vgpu,
-- 
2.25.1


WARNING: multiple messages have this Message-ID (diff)
From: Zheng Wang <zyytlz.wz@163.com>
To: zhi.a.wang@intel.com
Cc: alex000young@gmail.com, security@kernel.org,
	intel-gvt-dev@lists.freedesktop.org,
	tvrtko.ursulin@linux.intel.com, airlied@linux.ie,
	gregkh@linuxfoundation.org, intel-gfx@lists.freedesktop.org,
	hackerzheng666@gmail.com, dri-devel@lists.freedesktop.org,
	linux-kernel@vger.kernel.org, 1002992920@qq.com,
	zyytlz.wz@163.com
Subject: [RESEND PATCH v4] drm/i915/gvt: fix double free bug in split_2MB_gtt_entry
Date: Mon, 19 Dec 2022 20:52:04 +0800	[thread overview]
Message-ID: <20221219125204.1001149-1-zyytlz.wz@163.com> (raw)
In-Reply-To: <11728bc1-7b59-1623-b517-d1a0d57eb275@intel.com>

If intel_gvt_dma_map_guest_page failed, it will call
 ppgtt_invalidate_spt, which will finally free the spt. But the caller does
 not notice that, it will free spt again in error path.

Fix this by undoing the mapping of DMA address and freeing sub_spt.

Fixes: b901b252b6cf ("drm/i915/gvt: Add 2M huge gtt support")
Signed-off-by: Zheng Wang <zyytlz.wz@163.com>
---
v4:
- fix by undo the mapping of DMA address and free sub_spt suggested by Zhi

v3:
- correct spelling mistake and remove unused variable suggested by Greg

v2: https://lore.kernel.org/all/20221006165845.1735393-1-zyytlz.wz@163.com/

v1: https://lore.kernel.org/all/20220928033340.1063949-1-zyytlz.wz@163.com/
---
 drivers/gpu/drm/i915/gvt/gtt.c | 53 +++++++++++++++++++++++++++++-----
 1 file changed, 46 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index 51e5e8fb505b..b472e021e5a4 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -1192,11 +1192,11 @@ static int split_2MB_gtt_entry(struct intel_vgpu *vgpu,
 {
 	const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
 	struct intel_vgpu_ppgtt_spt *sub_spt;
-	struct intel_gvt_gtt_entry sub_se;
+	struct intel_gvt_gtt_entry sub_se, e;
 	unsigned long start_gfn;
 	dma_addr_t dma_addr;
-	unsigned long sub_index;
-	int ret;
+	unsigned long sub_index, parent_index;
+	int ret, ret1;
 
 	gvt_dbg_mm("Split 2M gtt entry, index %lu\n", index);
 
@@ -1209,10 +1209,8 @@ static int split_2MB_gtt_entry(struct intel_vgpu *vgpu,
 	for_each_shadow_entry(sub_spt, &sub_se, sub_index) {
 		ret = intel_gvt_dma_map_guest_page(vgpu, start_gfn + sub_index,
 						   PAGE_SIZE, &dma_addr);
-		if (ret) {
-			ppgtt_invalidate_spt(spt);
-			return ret;
-		}
+		if (ret)
+			goto err;
 		sub_se.val64 = se->val64;
 
 		/* Copy the PAT field from PDE. */
@@ -1231,6 +1229,47 @@ static int split_2MB_gtt_entry(struct intel_vgpu *vgpu,
 	ops->set_pfn(se, sub_spt->shadow_page.mfn);
 	ppgtt_set_shadow_entry(spt, se, index);
 	return 0;
+err:
+	/* Undone the existing mappings of DMA addr. */
+	for_each_present_shadow_entry(spt, &e, parent_index) {
+		switch (e.type) {
+		case GTT_TYPE_PPGTT_PTE_4K_ENTRY:
+			gvt_vdbg_mm("invalidate 4K entry\n");
+			ppgtt_invalidate_pte(spt, &e);
+			break;
+		case GTT_TYPE_PPGTT_PTE_64K_ENTRY:
+			/* We don't setup 64K shadow entry so far. */
+			WARN(1, "suspicious 64K gtt entry\n");
+			continue;
+		case GTT_TYPE_PPGTT_PTE_2M_ENTRY:
+			gvt_vdbg_mm("invalidate 2M entry\n");
+			continue;
+		case GTT_TYPE_PPGTT_PTE_1G_ENTRY:
+			WARN(1, "GVT doesn't support 1GB page\n");
+			continue;
+		case GTT_TYPE_PPGTT_PML4_ENTRY:
+		case GTT_TYPE_PPGTT_PDP_ENTRY:
+		case GTT_TYPE_PPGTT_PDE_ENTRY:
+			gvt_vdbg_mm("invalidate PMUL4/PDP/PDE entry\n");
+			ret1 = ppgtt_invalidate_spt_by_shadow_entry(
+					spt->vgpu, &e);
+			if (ret1) {
+				gvt_vgpu_err("fail: shadow page %p shadow entry 0x%llx type %d\n",
+				spt, e.val64, e.type);
+				goto free_spt;
+			}
+			break;
+		default:
+			GEM_BUG_ON(1);
+		}
+	}
+	/* Release the new alloced apt. */
+free_spt:
+	trace_spt_change(sub_spt->vgpu->id, "release", sub_spt,
+		sub_spt->guest_page.gfn, sub_spt->shadow_page.type);
+	ppgtt_free_spt(sub_spt);
+	sub_spt = NULL;
+	return ret;
 }
 
 static int split_64KB_gtt_entry(struct intel_vgpu *vgpu,
-- 
2.25.1


WARNING: multiple messages have this Message-ID (diff)
From: Zheng Wang <zyytlz.wz@163.com>
To: zhi.a.wang@intel.com
Cc: alex000young@gmail.com, security@kernel.org,
	intel-gvt-dev@lists.freedesktop.org, airlied@linux.ie,
	gregkh@linuxfoundation.org, intel-gfx@lists.freedesktop.org,
	hackerzheng666@gmail.com, dri-devel@lists.freedesktop.org,
	linux-kernel@vger.kernel.org, 1002992920@qq.com,
	zyytlz.wz@163.com, airlied@gmail.com
Subject: [Intel-gfx] [RESEND PATCH v4] drm/i915/gvt: fix double free bug in split_2MB_gtt_entry
Date: Mon, 19 Dec 2022 20:52:04 +0800	[thread overview]
Message-ID: <20221219125204.1001149-1-zyytlz.wz@163.com> (raw)
In-Reply-To: <11728bc1-7b59-1623-b517-d1a0d57eb275@intel.com>

If intel_gvt_dma_map_guest_page failed, it will call
 ppgtt_invalidate_spt, which will finally free the spt. But the caller does
 not notice that, it will free spt again in error path.

Fix this by undoing the mapping of DMA address and freeing sub_spt.

Fixes: b901b252b6cf ("drm/i915/gvt: Add 2M huge gtt support")
Signed-off-by: Zheng Wang <zyytlz.wz@163.com>
---
v4:
- fix by undo the mapping of DMA address and free sub_spt suggested by Zhi

v3:
- correct spelling mistake and remove unused variable suggested by Greg

v2: https://lore.kernel.org/all/20221006165845.1735393-1-zyytlz.wz@163.com/

v1: https://lore.kernel.org/all/20220928033340.1063949-1-zyytlz.wz@163.com/
---
 drivers/gpu/drm/i915/gvt/gtt.c | 53 +++++++++++++++++++++++++++++-----
 1 file changed, 46 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index 51e5e8fb505b..b472e021e5a4 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -1192,11 +1192,11 @@ static int split_2MB_gtt_entry(struct intel_vgpu *vgpu,
 {
 	const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
 	struct intel_vgpu_ppgtt_spt *sub_spt;
-	struct intel_gvt_gtt_entry sub_se;
+	struct intel_gvt_gtt_entry sub_se, e;
 	unsigned long start_gfn;
 	dma_addr_t dma_addr;
-	unsigned long sub_index;
-	int ret;
+	unsigned long sub_index, parent_index;
+	int ret, ret1;
 
 	gvt_dbg_mm("Split 2M gtt entry, index %lu\n", index);
 
@@ -1209,10 +1209,8 @@ static int split_2MB_gtt_entry(struct intel_vgpu *vgpu,
 	for_each_shadow_entry(sub_spt, &sub_se, sub_index) {
 		ret = intel_gvt_dma_map_guest_page(vgpu, start_gfn + sub_index,
 						   PAGE_SIZE, &dma_addr);
-		if (ret) {
-			ppgtt_invalidate_spt(spt);
-			return ret;
-		}
+		if (ret)
+			goto err;
 		sub_se.val64 = se->val64;
 
 		/* Copy the PAT field from PDE. */
@@ -1231,6 +1229,47 @@ static int split_2MB_gtt_entry(struct intel_vgpu *vgpu,
 	ops->set_pfn(se, sub_spt->shadow_page.mfn);
 	ppgtt_set_shadow_entry(spt, se, index);
 	return 0;
+err:
+	/* Undone the existing mappings of DMA addr. */
+	for_each_present_shadow_entry(spt, &e, parent_index) {
+		switch (e.type) {
+		case GTT_TYPE_PPGTT_PTE_4K_ENTRY:
+			gvt_vdbg_mm("invalidate 4K entry\n");
+			ppgtt_invalidate_pte(spt, &e);
+			break;
+		case GTT_TYPE_PPGTT_PTE_64K_ENTRY:
+			/* We don't setup 64K shadow entry so far. */
+			WARN(1, "suspicious 64K gtt entry\n");
+			continue;
+		case GTT_TYPE_PPGTT_PTE_2M_ENTRY:
+			gvt_vdbg_mm("invalidate 2M entry\n");
+			continue;
+		case GTT_TYPE_PPGTT_PTE_1G_ENTRY:
+			WARN(1, "GVT doesn't support 1GB page\n");
+			continue;
+		case GTT_TYPE_PPGTT_PML4_ENTRY:
+		case GTT_TYPE_PPGTT_PDP_ENTRY:
+		case GTT_TYPE_PPGTT_PDE_ENTRY:
+			gvt_vdbg_mm("invalidate PMUL4/PDP/PDE entry\n");
+			ret1 = ppgtt_invalidate_spt_by_shadow_entry(
+					spt->vgpu, &e);
+			if (ret1) {
+				gvt_vgpu_err("fail: shadow page %p shadow entry 0x%llx type %d\n",
+				spt, e.val64, e.type);
+				goto free_spt;
+			}
+			break;
+		default:
+			GEM_BUG_ON(1);
+		}
+	}
+	/* Release the new alloced apt. */
+free_spt:
+	trace_spt_change(sub_spt->vgpu->id, "release", sub_spt,
+		sub_spt->guest_page.gfn, sub_spt->shadow_page.type);
+	ppgtt_free_spt(sub_spt);
+	sub_spt = NULL;
+	return ret;
 }
 
 static int split_64KB_gtt_entry(struct intel_vgpu *vgpu,
-- 
2.25.1


  parent reply	other threads:[~2022-12-19 12:52 UTC|newest]

Thread overview: 93+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-18 19:24 [PATCH] drm/i915/gvt: fix double-free bug in split_2MB_gtt_entry Zheng Wang
2022-09-18 19:24 ` [Intel-gfx] " Zheng Wang
2022-09-19  9:30 ` Jani Nikula
2022-09-19  9:30   ` [Intel-gfx] " Jani Nikula
2022-09-19  9:55   ` Zheng Hacker
2022-09-19  9:55     ` [Intel-gfx] " Zheng Hacker
2022-09-19  9:55     ` Zheng Hacker
2022-09-21  9:13   ` Zheng Hacker
2022-09-21  9:13     ` [Intel-gfx] " Zheng Hacker
2022-09-21  9:13     ` Zheng Hacker
2022-09-28  3:33     ` [PATCH] drm/i915/gvt: fix double free " Zheng Wang
2022-09-28  3:33       ` [Intel-gfx] " Zheng Wang
2022-09-28  3:33       ` Zheng Wang
2022-10-02 14:18       ` Greg KH
2022-10-02 14:18         ` [Intel-gfx] " Greg KH
2022-10-02 14:18         ` Greg KH
2022-10-03  4:36         ` Zheng Hacker
2022-10-03  4:36           ` [Intel-gfx] " Zheng Hacker
2022-10-03  4:36           ` Zheng Hacker
2022-10-06 16:58       ` [PATCH v2] " Zheng Wang
2022-10-06 16:58         ` [Intel-gfx] " Zheng Wang
2022-10-06 16:58         ` Zheng Wang
2022-10-06 19:23         ` Greg KH
2022-10-06 19:23           ` [Intel-gfx] " Greg KH
2022-10-06 19:23           ` Greg KH
2022-10-07  0:39           ` Zheng Hacker
2022-10-07  0:39             ` [Intel-gfx] " Zheng Hacker
2022-10-07  0:39             ` Zheng Hacker
2022-10-07  1:37           ` [PATCH v3] " Zheng Wang
2022-10-07  1:37             ` [Intel-gfx] " Zheng Wang
2022-10-07  1:37             ` Zheng Wang
2022-10-27  0:01             ` [Intel-gfx] " Dave Airlie
2022-10-27  0:01               ` Dave Airlie
2022-10-27  0:01               ` Dave Airlie
2022-10-27  3:26               ` Zheng Hacker
2022-10-27  3:26                 ` [Intel-gfx] " Zheng Hacker
2022-10-27  3:26                 ` Zheng Hacker
2022-10-27  5:12                 ` Dave Airlie
2022-10-27  5:12                   ` [Intel-gfx] " Dave Airlie
2022-10-27  5:12                   ` Dave Airlie
2022-10-30 15:10                   ` Zheng Hacker
2022-10-30 15:10                     ` [Intel-gfx] " Zheng Hacker
2022-10-30 15:10                     ` Zheng Hacker
2022-12-15 10:47                   ` Joonas Lahtinen
2022-12-15 10:47                     ` [Intel-gfx] " Joonas Lahtinen
2022-12-15 11:33                     ` Wang, Zhi A
2022-12-15 11:33                       ` [Intel-gfx] " Wang, Zhi A
2022-12-15 13:26                       ` Zheng Hacker
2022-12-15 13:26                         ` [Intel-gfx] " Zheng Hacker
2022-12-15 13:26                         ` Zheng Hacker
2022-12-19  7:57                       ` [Intel-gfx] " Zheng Wang
2022-12-19  7:57                         ` Zheng Wang
2022-12-19  7:57                         ` Zheng Wang
2022-12-19  8:22                         ` Wang, Zhi A
2022-12-19  8:22                           ` Wang, Zhi A
2022-12-19  8:22                           ` Wang, Zhi A
2022-12-19  9:21                           ` Zheng Wang
2022-12-19  9:21                             ` Zheng Wang
2022-12-19  9:21                             ` Zheng Wang
2022-12-19 12:46                           ` [PATCH v4] [PATCH v4] " Zheng Wang
2022-12-19 12:46                             ` [Intel-gfx] " Zheng Wang
2022-12-19 12:46                             ` Zheng Wang
2022-12-19 12:52                           ` Zheng Wang [this message]
2022-12-19 12:52                             ` [Intel-gfx] [RESEND PATCH " Zheng Wang
2022-12-19 12:52                             ` Zheng Wang
2022-12-20  8:22                             ` Zhenyu Wang
2022-12-20  8:22                               ` [Intel-gfx] " Zhenyu Wang
2022-12-20  8:22                               ` Zhenyu Wang
2022-12-20  9:03                               ` Zheng Hacker
2022-12-20  9:03                                 ` [Intel-gfx] " Zheng Hacker
2022-12-20  9:03                                 ` Zheng Hacker
2022-12-20  9:40                           ` [PATCH v5] " Zheng Wang
2022-12-20  9:40                             ` [Intel-gfx] " Zheng Wang
2022-12-20  9:40                             ` Zheng Wang
2022-12-21  2:58                             ` Zhenyu Wang
2022-12-21  2:58                               ` [Intel-gfx] " Zhenyu Wang
2022-12-21  2:58                               ` Zhenyu Wang
2022-12-21  5:01                               ` Zheng Hacker
2022-12-21  5:01                                 ` [Intel-gfx] " Zheng Hacker
2022-12-21  5:01                                 ` Zheng Hacker
2022-12-29 16:56                           ` [PATCH v6] " Zheng Wang
2022-12-29 16:56                             ` [Intel-gfx] " Zheng Wang
2022-12-29 16:56                             ` Zheng Wang
2022-09-19 20:17 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/gvt: fix double-free bug in split_2MB_gtt_entry (rev2) Patchwork
2022-09-29 18:16 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gvt: fix double-free bug in split_2MB_gtt_entry (rev3) Patchwork
2022-09-29 18:40 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-09-30 18:41 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-10-10 15:00 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gvt: fix double-free bug in split_2MB_gtt_entry (rev5) Patchwork
2022-10-10 15:30 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-12-22 12:25 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gvt: fix double-free bug in split_2MB_gtt_entry (rev8) Patchwork
2022-12-22 12:53 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-12-22 18:13 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-12-29 17:57 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gvt: fix double-free bug in split_2MB_gtt_entry (rev9) Patchwork

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