From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D5958C4332F for ; Mon, 19 Dec 2022 14:48:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232443AbiLSOsn (ORCPT ); Mon, 19 Dec 2022 09:48:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47410 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232073AbiLSOr3 (ORCPT ); Mon, 19 Dec 2022 09:47:29 -0500 Received: from post.baikalelectronics.com (post.baikalelectronics.com [213.79.110.86]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id AEB47F6E; Mon, 19 Dec 2022 06:47:19 -0800 (PST) Received: from post.baikalelectronics.com (localhost.localdomain [127.0.0.1]) by post.baikalelectronics.com (Proxmox) with ESMTP id 50B13E0EB3; Mon, 19 Dec 2022 17:47:19 +0300 (MSK) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= baikalelectronics.ru; h=cc:cc:content-transfer-encoding :content-type:content-type:date:from:from:in-reply-to:message-id :mime-version:references:reply-to:subject:subject:to:to; s=post; bh=vuyhOpYNrdoe/gaMvhO2CJK7UJ9/diTNg13E3xchg9A=; b=dkS05lJcDSQp 4Im7It3h3pN1Zm417Q/7BxIc6z3s9yJQ3CNkfBotp7bVT4Y9hNIEGyXi9QIj/AFz 5cicqdnCFSNW9hjhMT3VFpf1Yzct1VRe/AM0mzWBKCeSI9yk1YbWStrlraUwfz68 Cvv6fwsKYFxtfaX2SlDirVb7wsu9bXE= Received: from mail.baikal.int (mail.baikal.int [192.168.51.25]) by post.baikalelectronics.com (Proxmox) with ESMTP id 41207E0E70; Mon, 19 Dec 2022 17:47:19 +0300 (MSK) Received: from localhost (10.8.30.14) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 19 Dec 2022 17:47:18 +0300 From: Serge Semin To: Gustavo Pimentel , Vinod Koul , Rob Herring , Bjorn Helgaas , Lorenzo Pieralisi , Cai Huoqing , Robin Murphy , Jingoo Han , Frank Li , Manivannan Sadhasivam , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= CC: Serge Semin , Serge Semin , Alexey Malahov , Pavel Parkhomenko , caihuoqing , Yoshihiro Shimoda , , , Subject: [PATCH v8 24/26] PCI: dwc: Set coherent DMA-mask on MSI-address allocation Date: Mon, 19 Dec 2022 17:46:55 +0300 Message-ID: <20221219144658.26620-25-Sergey.Semin@baikalelectronics.ru> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221219144658.26620-1-Sergey.Semin@baikalelectronics.ru> References: <20221219144658.26620-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.8.30.14] X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org The MSI target address requires to be reserved within the lowest 4GB memory in order to support the PCIe peripherals with no 64-bit MSI TLPs support. Since the allocation is done from the DMA-coherent memory let's modify the allocation procedure to setting the coherent DMA-mask only and avoiding the streaming DMA-mask modification. Thus at least the streaming DMA operations would work with no artificial limitations. It will be specifically useful for the eDMA-capable controllers so the corresponding DMA-engine clients would map the DMA buffers with no need in the SWIOTLB intervention for the buffers allocated above the 4GB memory region. While at it let's add a brief comment about the reason of having the MSI target address allocated from the DMA-coherent memory limited with the 4GB upper bound. Signed-off-by: Serge Semin --- Changelog v8: - This is a new patch added on v8 stage of the series. (@Robin, @Christoph) --- drivers/pci/controller/dwc/pcie-designware-host.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 3ab6ae3712c4..e10608af39b4 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -366,7 +366,16 @@ static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp) dw_chained_msi_isr, pp); } - ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); + /* + * Even though the iMSI-RX Module supports 64-bit addresses some + * peripheral PCIe devices may lack the 64-bit messages support. In + * order not to miss MSI TLPs from those devices the MSI target address + * has to be reserved within the lowest 4GB. + * Note until there is a better alternative found the reservation is + * done by allocating from the artificially limited DMA-coherent + * memory. + */ + ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32)); if (ret) dev_warn(dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n"); -- 2.38.1