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From: Fan Ni <fan.ni@samsung.com>
To: "linux-cxl@vger.kernel.org" <linux-cxl@vger.kernel.org>
Cc: "dan.j.williams@intel.com" <dan.j.williams@intel.com>,
	"vishal.l.verma@intel.com" <vishal.l.verma@intel.com>,
	"dave@stgolabs.net" <dave@stgolabs.net>,
	Adam Manzanares <a.manzanares@samsung.com>,
	"sunfishho12@gmail.com" <sunfishho12@gmail.com>,
	Fan Ni <fan.ni@samsung.com>
Subject: [ndctl PATCH 0/2] cxl-list: Construct CXL topology graph images
Date: Tue, 20 Dec 2022 18:26:20 +0000	[thread overview]
Message-ID: <20221220182510.2734032-1-fan.ni@samsung.com> (raw)
In-Reply-To: CGME20221220182621uscas1p22da97d084545a7b00f7bf7ea4df7ee3c@uscas1p2.samsung.com

This patch series extends the `cxl list` subcommand to show the cxl
topology visually. Mattew Ho first worked on the code and provided an
initial patch as list below[1].

This patch series includes the following two patches,
1) Patch 1 adds a parent_dport attribute to ports and type 3 memory devices to
show which downstream port a component is attached. This attribute will be used
in patch 2 to generate the cxl topology graph.
2) Patch 2 extends the `cxl list` subcommand to dump the cxl topology to a
json format file or generate a graph showing the cxl topology. To use the
extended function, the option `-o output.suffix` is added. Acceptable output
suffixes include .jpeg, .jpg and .png for generating a graph and for other
suffix, it will dump the json-formatted cxl topology to the file, which
can be used the input file (with --input option) to generate the graph
later.

Patch 2 reuses the plotting functions in Matthew Ho's patch, which are updated
to work with parent_dport attribute in patch 1. Also, some bugs are
fixed. More detailed changes are listed in Patch 2's commit log.

The patch series is tested with the following different cxl topologies,
1) a single memdev attached the only root port of the single HB in the system;
2) two memdevs attached to the two root ports of the single HB in the system;
3) four memdevs attached to two HBs, each of which has two root ports;
4) four memdevs attached to the downstream ports of a cxl switch which is
attached to one of the two root ports of a HB in the system.


[1] Mattew Ho's patch:
https://lore.kernel.org/linux-cxl/cover.1660895649.git.sunfishho12@gmail.com/





Fan Ni (2):
  cxl-list: add `parent_dport` to cxl_port/memdev objects
  cxl-list: Construct CXL topology graph images

 Documentation/cxl/cxl-list.txt |  16 ++
 cxl/filter.c                   |  45 +++-
 cxl/filter.h                   |   5 +
 cxl/graph.c                    | 409 +++++++++++++++++++++++++++++++++
 cxl/graph.h                    |  20 ++
 cxl/json.c                     |  11 +
 cxl/lib/libcxl.c               |  43 ++++
 cxl/lib/libcxl.sym             |   6 +
 cxl/lib/private.h              |   1 +
 cxl/libcxl.h                   |   3 +
 cxl/list.c                     |  31 +++
 cxl/meson.build                |   2 +
 meson.build                    |   1 +
 util/json.c                    |   2 +-
 14 files changed, 590 insertions(+), 5 deletions(-)
 create mode 100644 cxl/graph.c
 create mode 100644 cxl/graph.h

-- 
2.25.1

       reply	other threads:[~2022-12-20 18:26 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <CGME20221220182621uscas1p22da97d084545a7b00f7bf7ea4df7ee3c@uscas1p2.samsung.com>
2022-12-20 18:26 ` Fan Ni [this message]
     [not found]   ` <CGME20221220182641uscas1p24e70ddc9f912de0f3912028420854fb1@uscas1p2.samsung.com>
2022-12-20 18:26     ` [ndctl PATCH 1/2] cxl-list: add `parent_dport` to cxl_port/memdev objects Fan Ni
     [not found]   ` <CGME20221220182644uscas1p17dabe2b8d3a4d1eeb6ab1a0fd89cc178@uscas1p1.samsung.com>
2022-12-20 18:26     ` [ndctl PATCH 2/2] cxl-list: Construct CXL topology graph images Fan Ni
2023-01-03 19:05   ` [ndctl PATCH 0/2] " Dan Williams
2023-01-03 21:43     ` Fan Ni
2023-01-04  6:59       ` Verma, Vishal L
2023-01-04  8:34         ` Dan Williams
2023-01-04 16:21         ` Davidlohr Bueso

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